Back to home page

LXR

 
 

    


0001 /*
0002  * Copyright (C) 2015 Broadcom
0003  *
0004  * This program is free software; you can redistribute it and/or modify
0005  * it under the terms of the GNU General Public License version 2 as
0006  * published by the Free Software Foundation.
0007  */
0008 
0009 /**
0010  * DOC: VC4 plane module
0011  *
0012  * Each DRM plane is a layer of pixels being scanned out by the HVS.
0013  *
0014  * At atomic modeset check time, we compute the HVS display element
0015  * state that would be necessary for displaying the plane (giving us a
0016  * chance to figure out if a plane configuration is invalid), then at
0017  * atomic flush time the CRTC will ask us to write our element state
0018  * into the region of the HVS that it has allocated for us.
0019  */
0020 
0021 #include "vc4_drv.h"
0022 #include "vc4_regs.h"
0023 #include "drm_atomic_helper.h"
0024 #include "drm_fb_cma_helper.h"
0025 #include "drm_plane_helper.h"
0026 
0027 enum vc4_scaling_mode {
0028     VC4_SCALING_NONE,
0029     VC4_SCALING_TPZ,
0030     VC4_SCALING_PPF,
0031 };
0032 
0033 struct vc4_plane_state {
0034     struct drm_plane_state base;
0035     /* System memory copy of the display list for this element, computed
0036      * at atomic_check time.
0037      */
0038     u32 *dlist;
0039     u32 dlist_size; /* Number of dwords allocated for the display list */
0040     u32 dlist_count; /* Number of used dwords in the display list. */
0041 
0042     /* Offset in the dlist to various words, for pageflip or
0043      * cursor updates.
0044      */
0045     u32 pos0_offset;
0046     u32 pos2_offset;
0047     u32 ptr0_offset;
0048 
0049     /* Offset where the plane's dlist was last stored in the
0050      * hardware at vc4_crtc_atomic_flush() time.
0051      */
0052     u32 __iomem *hw_dlist;
0053 
0054     /* Clipped coordinates of the plane on the display. */
0055     int crtc_x, crtc_y, crtc_w, crtc_h;
0056     /* Clipped area being scanned from in the FB. */
0057     u32 src_x, src_y;
0058 
0059     u32 src_w[2], src_h[2];
0060 
0061     /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
0062     enum vc4_scaling_mode x_scaling[2], y_scaling[2];
0063     bool is_unity;
0064     bool is_yuv;
0065 
0066     /* Offset to start scanning out from the start of the plane's
0067      * BO.
0068      */
0069     u32 offsets[3];
0070 
0071     /* Our allocation in LBM for temporary storage during scaling. */
0072     struct drm_mm_node lbm;
0073 };
0074 
0075 static inline struct vc4_plane_state *
0076 to_vc4_plane_state(struct drm_plane_state *state)
0077 {
0078     return (struct vc4_plane_state *)state;
0079 }
0080 
0081 static const struct hvs_format {
0082     u32 drm; /* DRM_FORMAT_* */
0083     u32 hvs; /* HVS_FORMAT_* */
0084     u32 pixel_order;
0085     bool has_alpha;
0086     bool flip_cbcr;
0087 } hvs_formats[] = {
0088     {
0089         .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
0090         .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
0091     },
0092     {
0093         .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
0094         .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
0095     },
0096     {
0097         .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
0098         .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = true,
0099     },
0100     {
0101         .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
0102         .pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = false,
0103     },
0104     {
0105         .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
0106         .pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
0107     },
0108     {
0109         .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
0110         .pixel_order = HVS_PIXEL_ORDER_XBGR, .has_alpha = false,
0111     },
0112     {
0113         .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
0114         .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
0115     },
0116     {
0117         .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
0118         .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
0119     },
0120     {
0121         .drm = DRM_FORMAT_YUV422,
0122         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
0123     },
0124     {
0125         .drm = DRM_FORMAT_YVU422,
0126         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
0127         .flip_cbcr = true,
0128     },
0129     {
0130         .drm = DRM_FORMAT_YUV420,
0131         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
0132     },
0133     {
0134         .drm = DRM_FORMAT_YVU420,
0135         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
0136         .flip_cbcr = true,
0137     },
0138     {
0139         .drm = DRM_FORMAT_NV12,
0140         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
0141     },
0142     {
0143         .drm = DRM_FORMAT_NV16,
0144         .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
0145     },
0146 };
0147 
0148 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
0149 {
0150     unsigned i;
0151 
0152     for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
0153         if (hvs_formats[i].drm == drm_format)
0154             return &hvs_formats[i];
0155     }
0156 
0157     return NULL;
0158 }
0159 
0160 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
0161 {
0162     if (dst > src)
0163         return VC4_SCALING_PPF;
0164     else if (dst < src)
0165         return VC4_SCALING_TPZ;
0166     else
0167         return VC4_SCALING_NONE;
0168 }
0169 
0170 static bool plane_enabled(struct drm_plane_state *state)
0171 {
0172     return state->fb && state->crtc;
0173 }
0174 
0175 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
0176 {
0177     struct vc4_plane_state *vc4_state;
0178 
0179     if (WARN_ON(!plane->state))
0180         return NULL;
0181 
0182     vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
0183     if (!vc4_state)
0184         return NULL;
0185 
0186     memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
0187 
0188     __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
0189 
0190     if (vc4_state->dlist) {
0191         vc4_state->dlist = kmemdup(vc4_state->dlist,
0192                        vc4_state->dlist_count * 4,
0193                        GFP_KERNEL);
0194         if (!vc4_state->dlist) {
0195             kfree(vc4_state);
0196             return NULL;
0197         }
0198         vc4_state->dlist_size = vc4_state->dlist_count;
0199     }
0200 
0201     return &vc4_state->base;
0202 }
0203 
0204 static void vc4_plane_destroy_state(struct drm_plane *plane,
0205                     struct drm_plane_state *state)
0206 {
0207     struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
0208     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0209 
0210     if (vc4_state->lbm.allocated) {
0211         unsigned long irqflags;
0212 
0213         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
0214         drm_mm_remove_node(&vc4_state->lbm);
0215         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
0216     }
0217 
0218     kfree(vc4_state->dlist);
0219     __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
0220     kfree(state);
0221 }
0222 
0223 /* Called during init to allocate the plane's atomic state. */
0224 static void vc4_plane_reset(struct drm_plane *plane)
0225 {
0226     struct vc4_plane_state *vc4_state;
0227 
0228     WARN_ON(plane->state);
0229 
0230     vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
0231     if (!vc4_state)
0232         return;
0233 
0234     plane->state = &vc4_state->base;
0235     vc4_state->base.plane = plane;
0236 }
0237 
0238 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
0239 {
0240     if (vc4_state->dlist_count == vc4_state->dlist_size) {
0241         u32 new_size = max(4u, vc4_state->dlist_count * 2);
0242         u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL);
0243 
0244         if (!new_dlist)
0245             return;
0246         memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
0247 
0248         kfree(vc4_state->dlist);
0249         vc4_state->dlist = new_dlist;
0250         vc4_state->dlist_size = new_size;
0251     }
0252 
0253     vc4_state->dlist[vc4_state->dlist_count++] = val;
0254 }
0255 
0256 /* Returns the scl0/scl1 field based on whether the dimensions need to
0257  * be up/down/non-scaled.
0258  *
0259  * This is a replication of a table from the spec.
0260  */
0261 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
0262 {
0263     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0264 
0265     switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
0266     case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
0267         return SCALER_CTL0_SCL_H_PPF_V_PPF;
0268     case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
0269         return SCALER_CTL0_SCL_H_TPZ_V_PPF;
0270     case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
0271         return SCALER_CTL0_SCL_H_PPF_V_TPZ;
0272     case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
0273         return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
0274     case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
0275         return SCALER_CTL0_SCL_H_PPF_V_NONE;
0276     case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
0277         return SCALER_CTL0_SCL_H_NONE_V_PPF;
0278     case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
0279         return SCALER_CTL0_SCL_H_NONE_V_TPZ;
0280     case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
0281         return SCALER_CTL0_SCL_H_TPZ_V_NONE;
0282     default:
0283     case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
0284         /* The unity case is independently handled by
0285          * SCALER_CTL0_UNITY.
0286          */
0287         return 0;
0288     }
0289 }
0290 
0291 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
0292 {
0293     struct drm_plane *plane = state->plane;
0294     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0295     struct drm_framebuffer *fb = state->fb;
0296     struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
0297     u32 subpixel_src_mask = (1 << 16) - 1;
0298     u32 format = fb->pixel_format;
0299     int num_planes = drm_format_num_planes(format);
0300     u32 h_subsample = 1;
0301     u32 v_subsample = 1;
0302     int i;
0303 
0304     for (i = 0; i < num_planes; i++)
0305         vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
0306 
0307     /* We don't support subpixel source positioning for scaling. */
0308     if ((state->src_x & subpixel_src_mask) ||
0309         (state->src_y & subpixel_src_mask) ||
0310         (state->src_w & subpixel_src_mask) ||
0311         (state->src_h & subpixel_src_mask)) {
0312         return -EINVAL;
0313     }
0314 
0315     vc4_state->src_x = state->src_x >> 16;
0316     vc4_state->src_y = state->src_y >> 16;
0317     vc4_state->src_w[0] = state->src_w >> 16;
0318     vc4_state->src_h[0] = state->src_h >> 16;
0319 
0320     vc4_state->crtc_x = state->crtc_x;
0321     vc4_state->crtc_y = state->crtc_y;
0322     vc4_state->crtc_w = state->crtc_w;
0323     vc4_state->crtc_h = state->crtc_h;
0324 
0325     vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
0326                                vc4_state->crtc_w);
0327     vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
0328                                vc4_state->crtc_h);
0329 
0330     if (num_planes > 1) {
0331         vc4_state->is_yuv = true;
0332 
0333         h_subsample = drm_format_horz_chroma_subsampling(format);
0334         v_subsample = drm_format_vert_chroma_subsampling(format);
0335         vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
0336         vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
0337 
0338         vc4_state->x_scaling[1] =
0339             vc4_get_scaling_mode(vc4_state->src_w[1],
0340                          vc4_state->crtc_w);
0341         vc4_state->y_scaling[1] =
0342             vc4_get_scaling_mode(vc4_state->src_h[1],
0343                          vc4_state->crtc_h);
0344 
0345         /* YUV conversion requires that scaling be enabled,
0346          * even on a plane that's otherwise 1:1.  Choose TPZ
0347          * for simplicity.
0348          */
0349         if (vc4_state->x_scaling[0] == VC4_SCALING_NONE)
0350             vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
0351         if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
0352             vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
0353     }
0354 
0355     vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
0356                    vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
0357                    vc4_state->x_scaling[1] == VC4_SCALING_NONE &&
0358                    vc4_state->y_scaling[1] == VC4_SCALING_NONE);
0359 
0360     /* No configuring scaling on the cursor plane, since it gets
0361        non-vblank-synced updates, and scaling requires requires
0362        LBM changes which have to be vblank-synced.
0363      */
0364     if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
0365         return -EINVAL;
0366 
0367     /* Clamp the on-screen start x/y to 0.  The hardware doesn't
0368      * support negative y, and negative x wastes bandwidth.
0369      */
0370     if (vc4_state->crtc_x < 0) {
0371         for (i = 0; i < num_planes; i++) {
0372             u32 cpp = drm_format_plane_cpp(fb->pixel_format, i);
0373             u32 subs = ((i == 0) ? 1 : h_subsample);
0374 
0375             vc4_state->offsets[i] += (cpp *
0376                           (-vc4_state->crtc_x) / subs);
0377         }
0378         vc4_state->src_w[0] += vc4_state->crtc_x;
0379         vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
0380         vc4_state->crtc_x = 0;
0381     }
0382 
0383     if (vc4_state->crtc_y < 0) {
0384         for (i = 0; i < num_planes; i++) {
0385             u32 subs = ((i == 0) ? 1 : v_subsample);
0386 
0387             vc4_state->offsets[i] += (fb->pitches[i] *
0388                           (-vc4_state->crtc_y) / subs);
0389         }
0390         vc4_state->src_h[0] += vc4_state->crtc_y;
0391         vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
0392         vc4_state->crtc_y = 0;
0393     }
0394 
0395     return 0;
0396 }
0397 
0398 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
0399 {
0400     u32 scale, recip;
0401 
0402     scale = (1 << 16) * src / dst;
0403 
0404     /* The specs note that while the reciprocal would be defined
0405      * as (1<<32)/scale, ~0 is close enough.
0406      */
0407     recip = ~0 / scale;
0408 
0409     vc4_dlist_write(vc4_state,
0410             VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
0411             VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
0412     vc4_dlist_write(vc4_state,
0413             VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
0414 }
0415 
0416 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
0417 {
0418     u32 scale = (1 << 16) * src / dst;
0419 
0420     vc4_dlist_write(vc4_state,
0421             SCALER_PPF_AGC |
0422             VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
0423             VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
0424 }
0425 
0426 static u32 vc4_lbm_size(struct drm_plane_state *state)
0427 {
0428     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0429     /* This is the worst case number.  One of the two sizes will
0430      * be used depending on the scaling configuration.
0431      */
0432     u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
0433     u32 lbm;
0434 
0435     if (!vc4_state->is_yuv) {
0436         if (vc4_state->is_unity)
0437             return 0;
0438         else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
0439             lbm = pix_per_line * 8;
0440         else {
0441             /* In special cases, this multiplier might be 12. */
0442             lbm = pix_per_line * 16;
0443         }
0444     } else {
0445         /* There are cases for this going down to a multiplier
0446          * of 2, but according to the firmware source, the
0447          * table in the docs is somewhat wrong.
0448          */
0449         lbm = pix_per_line * 16;
0450     }
0451 
0452     lbm = roundup(lbm, 32);
0453 
0454     return lbm;
0455 }
0456 
0457 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
0458                      int channel)
0459 {
0460     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0461 
0462     /* Ch0 H-PPF Word 0: Scaling Parameters */
0463     if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
0464         vc4_write_ppf(vc4_state,
0465                   vc4_state->src_w[channel], vc4_state->crtc_w);
0466     }
0467 
0468     /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
0469     if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
0470         vc4_write_ppf(vc4_state,
0471                   vc4_state->src_h[channel], vc4_state->crtc_h);
0472         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
0473     }
0474 
0475     /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
0476     if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
0477         vc4_write_tpz(vc4_state,
0478                   vc4_state->src_w[channel], vc4_state->crtc_w);
0479     }
0480 
0481     /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
0482     if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
0483         vc4_write_tpz(vc4_state,
0484                   vc4_state->src_h[channel], vc4_state->crtc_h);
0485         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
0486     }
0487 }
0488 
0489 /* Writes out a full display list for an active plane to the plane's
0490  * private dlist state.
0491  */
0492 static int vc4_plane_mode_set(struct drm_plane *plane,
0493                   struct drm_plane_state *state)
0494 {
0495     struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
0496     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0497     struct drm_framebuffer *fb = state->fb;
0498     u32 ctl0_offset = vc4_state->dlist_count;
0499     const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
0500     int num_planes = drm_format_num_planes(format->drm);
0501     u32 scl0, scl1;
0502     u32 lbm_size;
0503     unsigned long irqflags;
0504     int ret, i;
0505 
0506     ret = vc4_plane_setup_clipping_and_scaling(state);
0507     if (ret)
0508         return ret;
0509 
0510     /* Allocate the LBM memory that the HVS will use for temporary
0511      * storage due to our scaling/format conversion.
0512      */
0513     lbm_size = vc4_lbm_size(state);
0514     if (lbm_size) {
0515         if (!vc4_state->lbm.allocated) {
0516             spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
0517             ret = drm_mm_insert_node(&vc4->hvs->lbm_mm,
0518                          &vc4_state->lbm,
0519                          lbm_size, 32, 0);
0520             spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
0521         } else {
0522             WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
0523         }
0524     }
0525 
0526     if (ret)
0527         return ret;
0528 
0529     /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
0530      * and 4:4:4, scl1 should be set to scl0 so both channels of
0531      * the scaler do the same thing.  For YUV, the Y plane needs
0532      * to be put in channel 1 and Cb/Cr in channel 0, so we swap
0533      * the scl fields here.
0534      */
0535     if (num_planes == 1) {
0536         scl0 = vc4_get_scl_field(state, 1);
0537         scl1 = scl0;
0538     } else {
0539         scl0 = vc4_get_scl_field(state, 1);
0540         scl1 = vc4_get_scl_field(state, 0);
0541     }
0542 
0543     /* Control word */
0544     vc4_dlist_write(vc4_state,
0545             SCALER_CTL0_VALID |
0546             (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
0547             (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
0548             (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
0549             VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
0550             VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
0551 
0552     /* Position Word 0: Image Positions and Alpha Value */
0553     vc4_state->pos0_offset = vc4_state->dlist_count;
0554     vc4_dlist_write(vc4_state,
0555             VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
0556             VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
0557             VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
0558 
0559     /* Position Word 1: Scaled Image Dimensions. */
0560     if (!vc4_state->is_unity) {
0561         vc4_dlist_write(vc4_state,
0562                 VC4_SET_FIELD(vc4_state->crtc_w,
0563                           SCALER_POS1_SCL_WIDTH) |
0564                 VC4_SET_FIELD(vc4_state->crtc_h,
0565                           SCALER_POS1_SCL_HEIGHT));
0566     }
0567 
0568     /* Position Word 2: Source Image Size, Alpha Mode */
0569     vc4_state->pos2_offset = vc4_state->dlist_count;
0570     vc4_dlist_write(vc4_state,
0571             VC4_SET_FIELD(format->has_alpha ?
0572                       SCALER_POS2_ALPHA_MODE_PIPELINE :
0573                       SCALER_POS2_ALPHA_MODE_FIXED,
0574                       SCALER_POS2_ALPHA_MODE) |
0575             VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
0576             VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
0577 
0578     /* Position Word 3: Context.  Written by the HVS. */
0579     vc4_dlist_write(vc4_state, 0xc0c0c0c0);
0580 
0581 
0582     /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
0583      *
0584      * The pointers may be any byte address.
0585      */
0586     vc4_state->ptr0_offset = vc4_state->dlist_count;
0587     if (!format->flip_cbcr) {
0588         for (i = 0; i < num_planes; i++)
0589             vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
0590     } else {
0591         WARN_ON_ONCE(num_planes != 3);
0592         vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
0593         vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
0594         vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
0595     }
0596 
0597     /* Pointer Context Word 0/1/2: Written by the HVS */
0598     for (i = 0; i < num_planes; i++)
0599         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
0600 
0601     /* Pitch word 0/1/2 */
0602     for (i = 0; i < num_planes; i++) {
0603         vc4_dlist_write(vc4_state,
0604                 VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
0605     }
0606 
0607     /* Colorspace conversion words */
0608     if (vc4_state->is_yuv) {
0609         vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
0610         vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
0611         vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
0612     }
0613 
0614     if (!vc4_state->is_unity) {
0615         /* LBM Base Address. */
0616         if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
0617             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
0618             vc4_dlist_write(vc4_state, vc4_state->lbm.start);
0619         }
0620 
0621         if (num_planes > 1) {
0622             /* Emit Cb/Cr as channel 0 and Y as channel
0623              * 1. This matches how we set up scl0/scl1
0624              * above.
0625              */
0626             vc4_write_scaling_parameters(state, 1);
0627         }
0628         vc4_write_scaling_parameters(state, 0);
0629 
0630         /* If any PPF setup was done, then all the kernel
0631          * pointers get uploaded.
0632          */
0633         if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
0634             vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
0635             vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
0636             vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
0637             u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
0638                            SCALER_PPF_KERNEL_OFFSET);
0639 
0640             /* HPPF plane 0 */
0641             vc4_dlist_write(vc4_state, kernel);
0642             /* VPPF plane 0 */
0643             vc4_dlist_write(vc4_state, kernel);
0644             /* HPPF plane 1 */
0645             vc4_dlist_write(vc4_state, kernel);
0646             /* VPPF plane 1 */
0647             vc4_dlist_write(vc4_state, kernel);
0648         }
0649     }
0650 
0651     vc4_state->dlist[ctl0_offset] |=
0652         VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
0653 
0654     return 0;
0655 }
0656 
0657 /* If a modeset involves changing the setup of a plane, the atomic
0658  * infrastructure will call this to validate a proposed plane setup.
0659  * However, if a plane isn't getting updated, this (and the
0660  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
0661  * compute the dlist here and have all active plane dlists get updated
0662  * in the CRTC's flush.
0663  */
0664 static int vc4_plane_atomic_check(struct drm_plane *plane,
0665                   struct drm_plane_state *state)
0666 {
0667     struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
0668 
0669     vc4_state->dlist_count = 0;
0670 
0671     if (plane_enabled(state))
0672         return vc4_plane_mode_set(plane, state);
0673     else
0674         return 0;
0675 }
0676 
0677 static void vc4_plane_atomic_update(struct drm_plane *plane,
0678                     struct drm_plane_state *old_state)
0679 {
0680     /* No contents here.  Since we don't know where in the CRTC's
0681      * dlist we should be stored, our dlist is uploaded to the
0682      * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
0683      * time.
0684      */
0685 }
0686 
0687 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
0688 {
0689     struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
0690     int i;
0691 
0692     vc4_state->hw_dlist = dlist;
0693 
0694     /* Can't memcpy_toio() because it needs to be 32-bit writes. */
0695     for (i = 0; i < vc4_state->dlist_count; i++)
0696         writel(vc4_state->dlist[i], &dlist[i]);
0697 
0698     return vc4_state->dlist_count;
0699 }
0700 
0701 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
0702 {
0703     const struct vc4_plane_state *vc4_state =
0704         container_of(state, typeof(*vc4_state), base);
0705 
0706     return vc4_state->dlist_count;
0707 }
0708 
0709 /* Updates the plane to immediately (well, once the FIFO needs
0710  * refilling) scan out from at a new framebuffer.
0711  */
0712 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
0713 {
0714     struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
0715     struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
0716     uint32_t addr;
0717 
0718     /* We're skipping the address adjustment for negative origin,
0719      * because this is only called on the primary plane.
0720      */
0721     WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
0722     addr = bo->paddr + fb->offsets[0];
0723 
0724     /* Write the new address into the hardware immediately.  The
0725      * scanout will start from this address as soon as the FIFO
0726      * needs to refill with pixels.
0727      */
0728     writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
0729 
0730     /* Also update the CPU-side dlist copy, so that any later
0731      * atomic updates that don't do a new modeset on our plane
0732      * also use our updated address.
0733      */
0734     vc4_state->dlist[vc4_state->ptr0_offset] = addr;
0735 }
0736 
0737 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
0738     .atomic_check = vc4_plane_atomic_check,
0739     .atomic_update = vc4_plane_atomic_update,
0740 };
0741 
0742 static void vc4_plane_destroy(struct drm_plane *plane)
0743 {
0744     drm_plane_helper_disable(plane);
0745     drm_plane_cleanup(plane);
0746 }
0747 
0748 /* Implements immediate (non-vblank-synced) updates of the cursor
0749  * position, or falls back to the atomic helper otherwise.
0750  */
0751 static int
0752 vc4_update_plane(struct drm_plane *plane,
0753          struct drm_crtc *crtc,
0754          struct drm_framebuffer *fb,
0755          int crtc_x, int crtc_y,
0756          unsigned int crtc_w, unsigned int crtc_h,
0757          uint32_t src_x, uint32_t src_y,
0758          uint32_t src_w, uint32_t src_h)
0759 {
0760     struct drm_plane_state *plane_state;
0761     struct vc4_plane_state *vc4_state;
0762 
0763     if (plane != crtc->cursor)
0764         goto out;
0765 
0766     plane_state = plane->state;
0767     vc4_state = to_vc4_plane_state(plane_state);
0768 
0769     if (!plane_state)
0770         goto out;
0771 
0772     /* If we're changing the cursor contents, do that in the
0773      * normal vblank-synced atomic path.
0774      */
0775     if (fb != plane_state->fb)
0776         goto out;
0777 
0778     /* No configuring new scaling in the fast path. */
0779     if (crtc_w != plane_state->crtc_w ||
0780         crtc_h != plane_state->crtc_h ||
0781         src_w != plane_state->src_w ||
0782         src_h != plane_state->src_h) {
0783         goto out;
0784     }
0785 
0786     /* Set the cursor's position on the screen.  This is the
0787      * expected change from the drm_mode_cursor_universal()
0788      * helper.
0789      */
0790     plane_state->crtc_x = crtc_x;
0791     plane_state->crtc_y = crtc_y;
0792 
0793     /* Allow changing the start position within the cursor BO, if
0794      * that matters.
0795      */
0796     plane_state->src_x = src_x;
0797     plane_state->src_y = src_y;
0798 
0799     /* Update the display list based on the new crtc_x/y. */
0800     vc4_plane_atomic_check(plane, plane_state);
0801 
0802     /* Note that we can't just call vc4_plane_write_dlist()
0803      * because that would smash the context data that the HVS is
0804      * currently using.
0805      */
0806     writel(vc4_state->dlist[vc4_state->pos0_offset],
0807            &vc4_state->hw_dlist[vc4_state->pos0_offset]);
0808     writel(vc4_state->dlist[vc4_state->pos2_offset],
0809            &vc4_state->hw_dlist[vc4_state->pos2_offset]);
0810     writel(vc4_state->dlist[vc4_state->ptr0_offset],
0811            &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
0812 
0813     return 0;
0814 
0815 out:
0816     return drm_atomic_helper_update_plane(plane, crtc, fb,
0817                           crtc_x, crtc_y,
0818                           crtc_w, crtc_h,
0819                           src_x, src_y,
0820                           src_w, src_h);
0821 }
0822 
0823 static const struct drm_plane_funcs vc4_plane_funcs = {
0824     .update_plane = vc4_update_plane,
0825     .disable_plane = drm_atomic_helper_disable_plane,
0826     .destroy = vc4_plane_destroy,
0827     .set_property = NULL,
0828     .reset = vc4_plane_reset,
0829     .atomic_duplicate_state = vc4_plane_duplicate_state,
0830     .atomic_destroy_state = vc4_plane_destroy_state,
0831 };
0832 
0833 struct drm_plane *vc4_plane_init(struct drm_device *dev,
0834                  enum drm_plane_type type)
0835 {
0836     struct drm_plane *plane = NULL;
0837     struct vc4_plane *vc4_plane;
0838     u32 formats[ARRAY_SIZE(hvs_formats)];
0839     u32 num_formats = 0;
0840     int ret = 0;
0841     unsigned i;
0842 
0843     vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
0844                  GFP_KERNEL);
0845     if (!vc4_plane) {
0846         ret = -ENOMEM;
0847         goto fail;
0848     }
0849 
0850     for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
0851         /* Don't allow YUV in cursor planes, since that means
0852          * tuning on the scaler, which we don't allow for the
0853          * cursor.
0854          */
0855         if (type != DRM_PLANE_TYPE_CURSOR ||
0856             hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
0857             formats[num_formats++] = hvs_formats[i].drm;
0858         }
0859     }
0860     plane = &vc4_plane->base;
0861     ret = drm_universal_plane_init(dev, plane, 0,
0862                        &vc4_plane_funcs,
0863                        formats, num_formats,
0864                        type, NULL);
0865 
0866     drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
0867 
0868     return plane;
0869 fail:
0870     if (plane)
0871         vc4_plane_destroy(plane);
0872 
0873     return ERR_PTR(ret);
0874 }