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0001 #ifndef _ASM_M32R_ASSEMBLER_H
0002 #define _ASM_M32R_ASSEMBLER_H
0003 
0004 /*
0005  * linux/asm-m32r/assembler.h
0006  *
0007  * Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
0008  *
0009  * This file contains M32R architecture specific macro definitions.
0010  */
0011 
0012 #include <linux/stringify.h>
0013 
0014 #undef __STR
0015 
0016 #ifdef __ASSEMBLY__
0017 #define __STR(x) x
0018 #else
0019 #define __STR(x) __stringify(x)
0020 #endif
0021 
0022 #ifdef CONFIG_SMP
0023 #define M32R_LOCK   __STR(lock)
0024 #define M32R_UNLOCK __STR(unlock)
0025 #else
0026 #define M32R_LOCK   __STR(ld)
0027 #define M32R_UNLOCK __STR(st)
0028 #endif
0029 
0030 #ifdef __ASSEMBLY__
0031 #undef ENTRY
0032 #define ENTRY(name) ENTRY_M name
0033     .macro  ENTRY_M name
0034     .global \name
0035     ALIGN
0036 \name:
0037     .endm
0038 #endif
0039 
0040 
0041 /**
0042  * LDIMM - load immediate value
0043  * STI - enable interruption
0044  * CLI - disable interruption
0045  */
0046 
0047 #ifdef __ASSEMBLY__
0048 
0049 #define LDIMM(reg,x) LDIMM reg x
0050     .macro LDIMM reg x
0051     seth    \reg, #high(\x)
0052     or3 \reg, \reg, #low(\x)
0053     .endm
0054 
0055 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
0056 #define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
0057     .macro ENABLE_INTERRUPTS reg
0058     setpsw  #0x40       ->  nop
0059     ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
0060     .endm
0061 
0062 #define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
0063     .macro DISABLE_INTERRUPTS reg
0064     clrpsw  #0x40       ->  nop
0065     ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
0066     .endm
0067 #else   /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
0068 #define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
0069     .macro ENABLE_INTERRUPTS reg
0070     mvfc    \reg, psw
0071     or3 \reg, \reg, #0x0040
0072     mvtc    \reg, psw
0073     .endm
0074 
0075 #define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
0076     .macro DISABLE_INTERRUPTS reg
0077     mvfc    \reg, psw
0078     and3    \reg, \reg, #0xffbf
0079     mvtc    \reg, psw
0080     .endm
0081 #endif  /* CONFIG_CHIP_M32102 */
0082 
0083     .macro  SAVE_ALL
0084     push    r0      ; orig_r0
0085     push    sp      ; spi (r15)
0086     push    lr      ; r14
0087     push    r13
0088     mvfc    r13, cr3    ; spu
0089     push    r13
0090     mvfc    r13, bbpc
0091     push    r13
0092     mvfc    r13, bbpsw
0093     push    r13
0094     mvfc    r13, bpc
0095     push    r13
0096     mvfc    r13, psw
0097     push    r13
0098 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
0099     mvfaclo r13, a1
0100     push    r13
0101     mvfachi r13, a1
0102     push    r13
0103     mvfaclo r13, a0
0104     push    r13
0105     mvfachi r13, a0
0106     push    r13
0107 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
0108     mvfaclo r13
0109     push    r13
0110     mvfachi r13
0111     push    r13
0112     ldi r13, #0
0113     push    r13     ; dummy push acc1h
0114     push    r13     ; dummy push acc1l
0115 #else
0116 #error unknown isa configuration
0117 #endif
0118     ldi r13, #-1
0119     push    r13     ; syscall_nr (default: -1)
0120     push    r12
0121     push    r11
0122     push    r10
0123     push    r9
0124     push    r8
0125     push    r7
0126     push    r3
0127     push    r2
0128     push    r1
0129     push    r0
0130     addi    sp, #-4     ; room for implicit pt_regs parameter
0131     push    r6
0132     push    r5
0133     push    r4
0134     .endm
0135 
0136     .macro  RESTORE_ALL
0137     pop r4
0138     pop r5
0139     pop r6
0140     addi    sp, #4
0141     pop r0
0142     pop r1
0143     pop r2
0144     pop r3
0145     pop r7
0146     pop r8
0147     pop r9
0148     pop r10
0149     pop r11
0150     pop r12
0151     addi    r15, #4     ; Skip syscall number
0152 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
0153     pop r13
0154     mvtachi r13, a0
0155     pop r13
0156     mvtaclo r13, a0
0157     pop r13
0158     mvtachi r13, a1
0159     pop r13
0160     mvtaclo r13, a1
0161 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
0162     pop r13     ; dummy pop acc1h
0163     pop r13     ; dummy pop acc1l
0164     pop r13
0165     mvtachi r13
0166     pop r13
0167     mvtaclo r13
0168 #else
0169 #error unknown isa configuration
0170 #endif
0171     pop r14
0172     mvtc    r14, psw
0173     pop r14
0174     mvtc    r14, bpc
0175     addi    sp, #8      ; Skip bbpsw, bbpc
0176     pop r14
0177     mvtc    r14, cr3    ; spu
0178     pop r13
0179     pop lr      ; r14
0180     pop sp      ; spi (r15)
0181     addi    sp, #4      ; Skip orig_r0
0182     .fillinsn
0183 1:  rte
0184     .section .fixup,"ax"
0185 2:  bl  do_exit
0186     .previous
0187     .section __ex_table,"a"
0188     ALIGN
0189     .long   1b, 2b
0190     .previous
0191     .endm
0192 
0193 #define GET_CURRENT(reg)  get_current reg
0194     .macro get_current reg
0195     ldi  \reg, #-8192
0196     and  \reg, sp
0197     .endm
0198 
0199 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
0200     .macro  SWITCH_TO_KERNEL_STACK
0201     ; switch to kernel stack (spi)
0202     clrpsw  #0x80       ->  nop
0203     .endm
0204 #else   /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
0205     .macro  SWITCH_TO_KERNEL_STACK
0206     push    r0      ; save r0 for working
0207     mvfc    r0, psw
0208     and3    r0, r0, #0x00ff7f
0209     mvtc    r0, psw
0210     slli    r0, #16
0211     bltz    r0, 1f      ; check BSM-bit
0212 ;
0213     ;; called from kernel context: previous stack = spi
0214     pop r0      ; retrieve r0
0215     bra 2f
0216     .fillinsn
0217 1:
0218     ;; called from user context: previous stack = spu
0219     mvfc    r0, cr3     ; spu
0220     addi    r0, #4
0221     mvtc    r0, cr3     ; spu
0222     ld  r0, @(-4,r0)    ; retrieve r0
0223     .fillinsn
0224 2:
0225     .endm
0226 #endif  /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
0227 
0228 #endif  /* __ASSEMBLY__ */
0229 
0230 #endif  /* _ASM_M32R_ASSEMBLER_H */