Back to home page

LXR

 
 

    


0001 /* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation
0002  *
0003  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
0004  * Written by David Howells (dhowells@redhat.com)
0005  *
0006  * This program is free software; you can redistribute it and/or
0007  * modify it under the terms of the GNU General Public License
0008  * as published by the Free Software Foundation; either version
0009  * 2 of the License, or (at your option) any later version.
0010  */
0011 
0012 #include <linux/init.h>
0013 #include <linux/threads.h>
0014 #include <linux/linkage.h>
0015 #include <asm/ptrace.h>
0016 #include <asm/page.h>
0017 #include <asm/spr-regs.h>
0018 #include <asm/mb86943a.h>
0019 #include "head.inc"
0020 
0021 
0022 #define __551_DARS0 0xfeff0100
0023 #define __551_DARS1 0xfeff0104
0024 #define __551_DARS2 0xfeff0108
0025 #define __551_DARS3 0xfeff010c
0026 #define __551_DAMK0 0xfeff0110
0027 #define __551_DAMK1 0xfeff0114
0028 #define __551_DAMK2 0xfeff0118
0029 #define __551_DAMK3 0xfeff011c
0030 #define __551_LCR   0xfeff1100
0031 #define __551_LSBR  0xfeff1c00
0032 
0033     __INIT
0034     .balign     4
0035 
0036 ###############################################################################
0037 #
0038 # describe the position and layout of the SDRAM controller registers
0039 #
0040 #   ENTRY:          EXIT:
0041 # GR5   -           cacheline size
0042 # GR11  -           displacement of 2nd SDRAM addr reg from GR14
0043 # GR12  -           displacement of 3rd SDRAM addr reg from GR14
0044 # GR13  -           displacement of 4th SDRAM addr reg from GR14
0045 # GR14  -           address of 1st SDRAM addr reg
0046 # GR15  -           amount to shift address by to match SDRAM addr reg
0047 # GR26  &__head_reference   [saved]
0048 # GR30  LED address     [saved]
0049 # CC0   -           T if DARS0 is present
0050 # CC1   -           T if DARS1 is present
0051 # CC2   -           T if DARS2 is present
0052 # CC3   -           T if DARS3 is present
0053 #
0054 ###############################################################################
0055     .globl      __head_fr555_describe_sdram
0056 __head_fr555_describe_sdram:
0057     sethi.p     %hi(__551_DARS0),gr14
0058     setlo       %lo(__551_DARS0),gr14
0059     setlos.p    #__551_DARS1-__551_DARS0,gr11
0060     setlos      #__551_DARS2-__551_DARS0,gr12
0061     setlos.p    #__551_DARS3-__551_DARS0,gr13
0062     setlos      #64,gr5         ; cacheline size
0063     setlos      #20,gr15        ; amount to shift addr by
0064     setlos      #0x00ff,gr4
0065     movgs       gr4,cccr        ; extant DARS/DAMK regs
0066     bralr
0067 
0068 ###############################################################################
0069 #
0070 # rearrange the bus controller registers
0071 #
0072 #   ENTRY:          EXIT:
0073 # GR26  &__head_reference   [saved]
0074 # GR30  LED address     revised LED address
0075 #
0076 ###############################################################################
0077     .globl      __head_fr555_set_busctl
0078 __head_fr555_set_busctl:
0079     LEDS        0x100f
0080     sethi.p     %hi(__551_LSBR),gr10
0081     setlo       %lo(__551_LSBR),gr10
0082     sethi.p     %hi(__551_LCR),gr11
0083     setlo       %lo(__551_LCR),gr11
0084 
0085     # set the bus controller
0086     sethi.p     %hi(__region_CS1),gr4
0087     setlo       %lo(__region_CS1),gr4
0088     sethi.p     %hi(__region_CS1_M),gr5
0089     setlo       %lo(__region_CS1_M),gr5
0090     sethi.p     %hi(__region_CS1_C),gr6
0091     setlo       %lo(__region_CS1_C),gr6
0092     sti     gr4,@(gr10,#1*0x08)
0093     sti     gr5,@(gr10,#1*0x08+0x100)
0094     sti     gr6,@(gr11,#1*0x08)
0095     sethi.p     %hi(__region_CS2),gr4
0096     setlo       %lo(__region_CS2),gr4
0097     sethi.p     %hi(__region_CS2_M),gr5
0098     setlo       %lo(__region_CS2_M),gr5
0099     sethi.p     %hi(__region_CS2_C),gr6
0100     setlo       %lo(__region_CS2_C),gr6
0101     sti     gr4,@(gr10,#2*0x08)
0102     sti     gr5,@(gr10,#2*0x08+0x100)
0103     sti     gr6,@(gr11,#2*0x08)
0104     sethi.p     %hi(__region_CS3),gr4
0105     setlo       %lo(__region_CS3),gr4
0106     sethi.p     %hi(__region_CS3_M),gr5
0107     setlo       %lo(__region_CS3_M),gr5
0108     sethi.p     %hi(__region_CS3_C),gr6
0109     setlo       %lo(__region_CS3_C),gr6
0110     sti     gr4,@(gr10,#3*0x08)
0111     sti     gr5,@(gr10,#3*0x08+0x100)
0112     sti     gr6,@(gr11,#3*0x08)
0113     sethi.p     %hi(__region_CS4),gr4
0114     setlo       %lo(__region_CS4),gr4
0115     sethi.p     %hi(__region_CS4_M),gr5
0116     setlo       %lo(__region_CS4_M),gr5
0117     sethi.p     %hi(__region_CS4_C),gr6
0118     setlo       %lo(__region_CS4_C),gr6
0119     sti     gr4,@(gr10,#4*0x08)
0120     sti     gr5,@(gr10,#4*0x08+0x100)
0121     sti     gr6,@(gr11,#4*0x08)
0122     sethi.p     %hi(__region_CS5),gr4
0123     setlo       %lo(__region_CS5),gr4
0124     sethi.p     %hi(__region_CS5_M),gr5
0125     setlo       %lo(__region_CS5_M),gr5
0126     sethi.p     %hi(__region_CS5_C),gr6
0127     setlo       %lo(__region_CS5_C),gr6
0128     sti     gr4,@(gr10,#5*0x08)
0129     sti     gr5,@(gr10,#5*0x08+0x100)
0130     sti     gr6,@(gr11,#5*0x08)
0131     sethi.p     %hi(__region_CS6),gr4
0132     setlo       %lo(__region_CS6),gr4
0133     sethi.p     %hi(__region_CS6_M),gr5
0134     setlo       %lo(__region_CS6_M),gr5
0135     sethi.p     %hi(__region_CS6_C),gr6
0136     setlo       %lo(__region_CS6_C),gr6
0137     sti     gr4,@(gr10,#6*0x08)
0138     sti     gr5,@(gr10,#6*0x08+0x100)
0139     sti     gr6,@(gr11,#6*0x08)
0140     sethi.p     %hi(__region_CS7),gr4
0141     setlo       %lo(__region_CS7),gr4
0142     sethi.p     %hi(__region_CS7_M),gr5
0143     setlo       %lo(__region_CS7_M),gr5
0144     sethi.p     %hi(__region_CS7_C),gr6
0145     setlo       %lo(__region_CS7_C),gr6
0146     sti     gr4,@(gr10,#7*0x08)
0147     sti     gr5,@(gr10,#7*0x08+0x100)
0148     sti     gr6,@(gr11,#7*0x08)
0149     membar
0150     bar
0151 
0152     # adjust LED bank address
0153 #ifdef CONFIG_MB93091_VDK
0154     sethi.p     %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
0155     setlo       %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
0156 #endif
0157     bralr
0158 
0159 ###############################################################################
0160 #
0161 # determine the total SDRAM size
0162 #
0163 #   ENTRY:          EXIT:
0164 # GR25  -           SDRAM size
0165 # GR26  &__head_reference   [saved]
0166 # GR30  LED address     [saved]
0167 #
0168 ###############################################################################
0169     .globl      __head_fr555_survey_sdram
0170 __head_fr555_survey_sdram:
0171     sethi.p     %hi(__551_DAMK0),gr11
0172     setlo       %lo(__551_DAMK0),gr11
0173     sethi.p     %hi(__551_DARS0),gr12
0174     setlo       %lo(__551_DARS0),gr12
0175 
0176     sethi.p     %hi(0xfff),gr17         ; unused SDRAM AMK value
0177     setlo       %lo(0xfff),gr17
0178     setlos      #0,gr25
0179 
0180     ldi     @(gr11,#0x00),gr6       ; DAMK0: bits 11:0 match addr 11:0
0181     subcc       gr6,gr17,gr0,icc0
0182     beq     icc0,#0,__head_no_DCS0
0183     ldi     @(gr12,#0x00),gr4       ; DARS0
0184     add     gr25,gr6,gr25
0185     addi        gr25,#1,gr25
0186 __head_no_DCS0:
0187 
0188     ldi     @(gr11,#0x04),gr6       ; DAMK1: bits 11:0 match addr 11:0
0189     subcc       gr6,gr17,gr0,icc0
0190     beq     icc0,#0,__head_no_DCS1
0191     ldi     @(gr12,#0x04),gr4       ; DARS1
0192     add     gr25,gr6,gr25
0193     addi        gr25,#1,gr25
0194 __head_no_DCS1:
0195 
0196     ldi     @(gr11,#0x8),gr6        ; DAMK2: bits 11:0 match addr 11:0
0197     subcc       gr6,gr17,gr0,icc0
0198     beq     icc0,#0,__head_no_DCS2
0199     ldi     @(gr12,#0x8),gr4        ; DARS2
0200     add     gr25,gr6,gr25
0201     addi        gr25,#1,gr25
0202 __head_no_DCS2:
0203 
0204     ldi     @(gr11,#0xc),gr6        ; DAMK3: bits 11:0 match addr 11:0
0205     subcc       gr6,gr17,gr0,icc0
0206     beq     icc0,#0,__head_no_DCS3
0207     ldi     @(gr12,#0xc),gr4        ; DARS3
0208     add     gr25,gr6,gr25
0209     addi        gr25,#1,gr25
0210 __head_no_DCS3:
0211 
0212     slli        gr25,#20,gr25           ; shift [11:0] -> [31:20]
0213     bralr
0214 
0215 ###############################################################################
0216 #
0217 # set the protection map with the I/DAMPR registers
0218 #
0219 #   ENTRY:          EXIT:
0220 # GR25  SDRAM size      saved
0221 # GR30  LED address     saved
0222 #
0223 ###############################################################################
0224     .globl      __head_fr555_set_protection
0225 __head_fr555_set_protection:
0226     movsg       lr,gr27
0227 
0228     sethi.p     %hi(0xfff00000),gr11
0229     setlo       %lo(0xfff00000),gr11
0230 
0231     # set the I/O region protection registers for FR555
0232     sethi.p     %hi(__region_IO),gr7
0233     setlo       %lo(__region_IO),gr7
0234     ori     gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
0235     movgs       gr0,iampr15
0236     movgs       gr0,iamlr15
0237     movgs       gr5,dampr15
0238     movgs       gr7,damlr15
0239 
0240     # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
0241     # - start with the highest numbered registers
0242     sethi.p     %hi(__kernel_image_end),gr8
0243     setlo       %lo(__kernel_image_end),gr8
0244     sethi.p     %hi(32768),gr4          ; allow for a maximal allocator bitmap
0245     setlo       %lo(32768),gr4
0246     add     gr8,gr4,gr8
0247     sethi.p     %hi(1024*2048-1),gr4        ; round up to nearest 2MiB
0248     setlo       %lo(1024*2048-1),gr4
0249     add.p       gr8,gr4,gr8
0250     not     gr4,gr4
0251     and     gr8,gr4,gr8
0252 
0253     sethi.p     %hi(__page_offset),gr9
0254     setlo       %lo(__page_offset),gr9
0255     add     gr9,gr25,gr9
0256 
0257     # GR8 = base of uncovered RAM
0258     # GR9 = top of uncovered RAM
0259     # GR11 - mask for DAMLR/IAMLR regs
0260     #
0261     call        __head_split_region
0262     movgs       gr4,iampr14
0263     movgs       gr6,iamlr14
0264     movgs       gr5,dampr14
0265     movgs       gr7,damlr14
0266     call        __head_split_region
0267     movgs       gr4,iampr13
0268     movgs       gr6,iamlr13
0269     movgs       gr5,dampr13
0270     movgs       gr7,damlr13
0271     call        __head_split_region
0272     movgs       gr4,iampr12
0273     movgs       gr6,iamlr12
0274     movgs       gr5,dampr12
0275     movgs       gr7,damlr12
0276     call        __head_split_region
0277     movgs       gr4,iampr11
0278     movgs       gr6,iamlr11
0279     movgs       gr5,dampr11
0280     movgs       gr7,damlr11
0281     call        __head_split_region
0282     movgs       gr4,iampr10
0283     movgs       gr6,iamlr10
0284     movgs       gr5,dampr10
0285     movgs       gr7,damlr10
0286     call        __head_split_region
0287     movgs       gr4,iampr9
0288     movgs       gr6,iamlr9
0289     movgs       gr5,dampr9
0290     movgs       gr7,damlr9
0291     call        __head_split_region
0292     movgs       gr4,iampr8
0293     movgs       gr6,iamlr8
0294     movgs       gr5,dampr8
0295     movgs       gr7,damlr8
0296 
0297     call        __head_split_region
0298     movgs       gr4,iampr7
0299     movgs       gr6,iamlr7
0300     movgs       gr5,dampr7
0301     movgs       gr7,damlr7
0302     call        __head_split_region
0303     movgs       gr4,iampr6
0304     movgs       gr6,iamlr6
0305     movgs       gr5,dampr6
0306     movgs       gr7,damlr6
0307     call        __head_split_region
0308     movgs       gr4,iampr5
0309     movgs       gr6,iamlr5
0310     movgs       gr5,dampr5
0311     movgs       gr7,damlr5
0312     call        __head_split_region
0313     movgs       gr4,iampr4
0314     movgs       gr6,iamlr4
0315     movgs       gr5,dampr4
0316     movgs       gr7,damlr4
0317     call        __head_split_region
0318     movgs       gr4,iampr3
0319     movgs       gr6,iamlr3
0320     movgs       gr5,dampr3
0321     movgs       gr7,damlr3
0322     call        __head_split_region
0323     movgs       gr4,iampr2
0324     movgs       gr6,iamlr2
0325     movgs       gr5,dampr2
0326     movgs       gr7,damlr2
0327     call        __head_split_region
0328     movgs       gr4,iampr1
0329     movgs       gr6,iamlr1
0330     movgs       gr5,dampr1
0331     movgs       gr7,damlr1
0332 
0333     # cover kernel core image with kernel-only segment
0334     sethi.p     %hi(__page_offset),gr8
0335     setlo       %lo(__page_offset),gr8
0336     call        __head_split_region
0337 
0338 #ifdef CONFIG_PROTECT_KERNEL
0339     ori.p       gr4,#xAMPRx_S_KERNEL,gr4
0340     ori     gr5,#xAMPRx_S_KERNEL,gr5
0341 #endif
0342 
0343     movgs       gr4,iampr0
0344     movgs       gr6,iamlr0
0345     movgs       gr5,dampr0
0346     movgs       gr7,damlr0
0347     jmpl        @(gr27,gr0)