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0001 /* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation
0002  *
0003  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
0004  * Written by David Howells (dhowells@redhat.com)
0005  *
0006  * This program is free software; you can redistribute it and/or
0007  * modify it under the terms of the GNU General Public License
0008  * as published by the Free Software Foundation; either version
0009  * 2 of the License, or (at your option) any later version.
0010  */
0011 
0012 #include <linux/init.h>
0013 #include <linux/threads.h>
0014 #include <linux/linkage.h>
0015 #include <asm/ptrace.h>
0016 #include <asm/page.h>
0017 #include <asm/mem-layout.h>
0018 #include <asm/spr-regs.h>
0019 #include <asm/mb86943a.h>
0020 #include "head.inc"
0021 
0022 
0023 #define __400_DBR0  0xfe000e00
0024 #define __400_DBR1  0xfe000e08
0025 #define __400_DBR2  0xfe000e10
0026 #define __400_DBR3  0xfe000e18
0027 #define __400_DAM0  0xfe000f00
0028 #define __400_DAM1  0xfe000f08
0029 #define __400_DAM2  0xfe000f10
0030 #define __400_DAM3  0xfe000f18
0031 #define __400_LGCR  0xfe000010
0032 #define __400_LCR   0xfe000100
0033 #define __400_LSBR  0xfe000c00
0034 
0035     __INIT
0036     .balign     4
0037 
0038 ###############################################################################
0039 #
0040 # describe the position and layout of the SDRAM controller registers
0041 #
0042 #   ENTRY:          EXIT:
0043 # GR5   -           cacheline size
0044 # GR11  -           displacement of 2nd SDRAM addr reg from GR14
0045 # GR12  -           displacement of 3rd SDRAM addr reg from GR14
0046 # GR13  -           displacement of 4th SDRAM addr reg from GR14
0047 # GR14  -           address of 1st SDRAM addr reg
0048 # GR15  -           amount to shift address by to match SDRAM addr reg
0049 # GR26  &__head_reference   [saved]
0050 # GR30  LED address     [saved]
0051 # CC0   -           T if DBR0 is present
0052 # CC1   -           T if DBR1 is present
0053 # CC2   -           T if DBR2 is present
0054 # CC3   -           T if DBR3 is present
0055 #
0056 ###############################################################################
0057     .globl      __head_fr451_describe_sdram
0058 __head_fr451_describe_sdram:
0059     sethi.p     %hi(__400_DBR0),gr14
0060     setlo       %lo(__400_DBR0),gr14
0061     setlos.p    #__400_DBR1-__400_DBR0,gr11
0062     setlos      #__400_DBR2-__400_DBR0,gr12
0063     setlos.p    #__400_DBR3-__400_DBR0,gr13
0064     setlos      #32,gr5         ; cacheline size
0065     setlos.p    #0,gr15         ; amount to shift addr reg by
0066     setlos      #0x00ff,gr4
0067     movgs       gr4,cccr        ; extant DARS/DAMK regs
0068     bralr
0069 
0070 ###############################################################################
0071 #
0072 # rearrange the bus controller registers
0073 #
0074 #   ENTRY:          EXIT:
0075 # GR26  &__head_reference   [saved]
0076 # GR30  LED address     revised LED address
0077 #
0078 ###############################################################################
0079     .globl      __head_fr451_set_busctl
0080 __head_fr451_set_busctl:
0081     sethi.p     %hi(__400_LGCR),gr4
0082     setlo       %lo(__400_LGCR),gr4
0083     sethi.p     %hi(__400_LSBR),gr10
0084     setlo       %lo(__400_LSBR),gr10
0085     sethi.p     %hi(__400_LCR),gr11
0086     setlo       %lo(__400_LCR),gr11
0087 
0088     # set the bus controller
0089     ldi     @(gr4,#0),gr5
0090     ori     gr5,#0xff,gr5       ; make sure all chip-selects are enabled
0091     sti     gr5,@(gr4,#0)
0092 
0093     sethi.p     %hi(__region_CS1),gr4
0094     setlo       %lo(__region_CS1),gr4
0095     sethi.p     %hi(__region_CS1_M),gr5
0096     setlo       %lo(__region_CS1_M),gr5
0097     sethi.p     %hi(__region_CS1_C),gr6
0098     setlo       %lo(__region_CS1_C),gr6
0099     sti     gr4,@(gr10,#1*0x08)
0100     sti     gr5,@(gr10,#1*0x08+0x100)
0101     sti     gr6,@(gr11,#1*0x08)
0102     sethi.p     %hi(__region_CS2),gr4
0103     setlo       %lo(__region_CS2),gr4
0104     sethi.p     %hi(__region_CS2_M),gr5
0105     setlo       %lo(__region_CS2_M),gr5
0106     sethi.p     %hi(__region_CS2_C),gr6
0107     setlo       %lo(__region_CS2_C),gr6
0108     sti     gr4,@(gr10,#2*0x08)
0109     sti     gr5,@(gr10,#2*0x08+0x100)
0110     sti     gr6,@(gr11,#2*0x08)
0111     sethi.p     %hi(__region_CS3),gr4
0112     setlo       %lo(__region_CS3),gr4
0113     sethi.p     %hi(__region_CS3_M),gr5
0114     setlo       %lo(__region_CS3_M),gr5
0115     sethi.p     %hi(__region_CS3_C),gr6
0116     setlo       %lo(__region_CS3_C),gr6
0117     sti     gr4,@(gr10,#3*0x08)
0118     sti     gr5,@(gr10,#3*0x08+0x100)
0119     sti     gr6,@(gr11,#3*0x08)
0120     sethi.p     %hi(__region_CS4),gr4
0121     setlo       %lo(__region_CS4),gr4
0122     sethi.p     %hi(__region_CS4_M),gr5
0123     setlo       %lo(__region_CS4_M),gr5
0124     sethi.p     %hi(__region_CS4_C),gr6
0125     setlo       %lo(__region_CS4_C),gr6
0126     sti     gr4,@(gr10,#4*0x08)
0127     sti     gr5,@(gr10,#4*0x08+0x100)
0128     sti     gr6,@(gr11,#4*0x08)
0129     sethi.p     %hi(__region_CS5),gr4
0130     setlo       %lo(__region_CS5),gr4
0131     sethi.p     %hi(__region_CS5_M),gr5
0132     setlo       %lo(__region_CS5_M),gr5
0133     sethi.p     %hi(__region_CS5_C),gr6
0134     setlo       %lo(__region_CS5_C),gr6
0135     sti     gr4,@(gr10,#5*0x08)
0136     sti     gr5,@(gr10,#5*0x08+0x100)
0137     sti     gr6,@(gr11,#5*0x08)
0138     sethi.p     %hi(__region_CS6),gr4
0139     setlo       %lo(__region_CS6),gr4
0140     sethi.p     %hi(__region_CS6_M),gr5
0141     setlo       %lo(__region_CS6_M),gr5
0142     sethi.p     %hi(__region_CS6_C),gr6
0143     setlo       %lo(__region_CS6_C),gr6
0144     sti     gr4,@(gr10,#6*0x08)
0145     sti     gr5,@(gr10,#6*0x08+0x100)
0146     sti     gr6,@(gr11,#6*0x08)
0147     sethi.p     %hi(__region_CS7),gr4
0148     setlo       %lo(__region_CS7),gr4
0149     sethi.p     %hi(__region_CS7_M),gr5
0150     setlo       %lo(__region_CS7_M),gr5
0151     sethi.p     %hi(__region_CS7_C),gr6
0152     setlo       %lo(__region_CS7_C),gr6
0153     sti     gr4,@(gr10,#7*0x08)
0154     sti     gr5,@(gr10,#7*0x08+0x100)
0155     sti     gr6,@(gr11,#7*0x08)
0156     membar
0157     bar
0158 
0159     # adjust LED bank address
0160 #ifdef CONFIG_MB93091_VDK
0161     sethi.p     %hi(__region_CS2 + 0x01200004),gr30
0162     setlo       %lo(__region_CS2 + 0x01200004),gr30
0163 #endif
0164     bralr
0165 
0166 ###############################################################################
0167 #
0168 # determine the total SDRAM size
0169 #
0170 #   ENTRY:          EXIT:
0171 # GR25  -           SDRAM size
0172 # GR26  &__head_reference   [saved]
0173 # GR30  LED address     [saved]
0174 #
0175 ###############################################################################
0176     .globl      __head_fr451_survey_sdram
0177 __head_fr451_survey_sdram:
0178     sethi.p     %hi(__400_DAM0),gr11
0179     setlo       %lo(__400_DAM0),gr11
0180     sethi.p     %hi(__400_DBR0),gr12
0181     setlo       %lo(__400_DBR0),gr12
0182 
0183     sethi.p     %hi(0xfe000000),gr17        ; unused SDRAM DBR value
0184     setlo       %lo(0xfe000000),gr17
0185     setlos      #0,gr25
0186 
0187     ldi     @(gr12,#0x00),gr4       ; DAR0
0188     subcc       gr4,gr17,gr0,icc0
0189     beq     icc0,#0,__head_no_DCS0
0190     ldi     @(gr11,#0x00),gr6       ; DAM0: bits 31:20 match addr 31:20
0191     add     gr25,gr6,gr25
0192     addi        gr25,#1,gr25
0193 __head_no_DCS0:
0194 
0195     ldi     @(gr12,#0x08),gr4       ; DAR1
0196     subcc       gr4,gr17,gr0,icc0
0197     beq     icc0,#0,__head_no_DCS1
0198     ldi     @(gr11,#0x08),gr6       ; DAM1: bits 31:20 match addr 31:20
0199     add     gr25,gr6,gr25
0200     addi        gr25,#1,gr25
0201 __head_no_DCS1:
0202 
0203     ldi     @(gr12,#0x10),gr4       ; DAR2
0204     subcc       gr4,gr17,gr0,icc0
0205     beq     icc0,#0,__head_no_DCS2
0206     ldi     @(gr11,#0x10),gr6       ; DAM2: bits 31:20 match addr 31:20
0207     add     gr25,gr6,gr25
0208     addi        gr25,#1,gr25
0209 __head_no_DCS2:
0210 
0211     ldi     @(gr12,#0x18),gr4       ; DAR3
0212     subcc       gr4,gr17,gr0,icc0
0213     beq     icc0,#0,__head_no_DCS3
0214     ldi     @(gr11,#0x18),gr6       ; DAM3: bits 31:20 match addr 31:20
0215     add     gr25,gr6,gr25
0216     addi        gr25,#1,gr25
0217 __head_no_DCS3:
0218     bralr
0219 
0220 ###############################################################################
0221 #
0222 # set the protection map with the I/DAMPR registers
0223 #
0224 #   ENTRY:          EXIT:
0225 # GR25  SDRAM size      [saved]
0226 # GR26  &__head_reference   [saved]
0227 # GR30  LED address     [saved]
0228 #
0229 #
0230 # Using this map:
0231 #   REGISTERS   ADDRESS RANGE       VIEW
0232 #   =============== ======================  ===============================
0233 #   IAMPR0/DAMPR0   0xC0000000-0xCFFFFFFF   Cached kernel RAM Window
0234 #   DAMPR11     0xE0000000-0xFFFFFFFF   Uncached I/O
0235 #
0236 ###############################################################################
0237     .globl      __head_fr451_set_protection
0238 __head_fr451_set_protection:
0239     movsg       lr,gr27
0240 
0241     # set the I/O region protection registers for FR451 in MMU mode
0242 #define PGPROT_IO   xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V
0243 
0244     sethi.p     %hi(__region_IO),gr5
0245     setlo       %lo(__region_IO),gr5
0246     setlos      #PGPROT_IO|xAMPRx_SS_512Mb,gr4
0247     or      gr4,gr5,gr4
0248     movgs       gr5,damlr11         ; General I/O tile
0249     movgs       gr4,dampr11
0250 
0251     # need to open a window onto at least part of the RAM for the kernel's use
0252     sethi.p     %hi(__sdram_base),gr8
0253     setlo       %lo(__sdram_base),gr8       ; physical address
0254     sethi.p     %hi(__page_offset),gr9
0255     setlo       %lo(__page_offset),gr9      ; virtual address
0256 
0257     setlos      #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11
0258     or      gr8,gr11,gr8
0259 
0260     movgs       gr9,iamlr0          ; mapped from real address 0
0261     movgs       gr8,iampr0          ; cached kernel memory at 0xC0000000
0262     movgs       gr9,damlr0
0263     movgs       gr8,dampr0
0264 
0265     # set a temporary mapping for the kernel running at address 0 until we've turned on the MMU
0266     sethi.p     %hi(__sdram_base),gr9
0267     setlo       %lo(__sdram_base),gr9       ; virtual address
0268 
0269     and.p       gr4,gr11,gr4
0270     and     gr5,gr11,gr5
0271     or.p        gr4,gr11,gr4
0272     or      gr5,gr11,gr5
0273 
0274     movgs       gr9,iamlr1          ; mapped from real address 0
0275     movgs       gr8,iampr1          ; cached kernel memory at 0x00000000
0276     movgs       gr9,damlr1
0277     movgs       gr8,dampr1
0278 
0279     # we use DAMR2-10 for kmap_atomic(), cache flush and TLB management
0280     # since the DAMLR regs are not going to change, we can set them now
0281     # also set up IAMLR2 to the same as DAMLR5
0282     sethi.p     %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4
0283     setlo       %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4
0284     sethi.p     %hi(PAGE_SIZE),gr5
0285     setlo       %lo(PAGE_SIZE),gr5
0286 
0287     movgs       gr4,damlr2
0288     movgs       gr4,iamlr2
0289     add     gr4,gr5,gr4
0290     movgs       gr4,damlr3
0291     add     gr4,gr5,gr4
0292     movgs       gr4,damlr4
0293     add     gr4,gr5,gr4
0294     movgs       gr4,damlr5
0295     add     gr4,gr5,gr4
0296     movgs       gr4,damlr6
0297     add     gr4,gr5,gr4
0298     movgs       gr4,damlr7
0299     add     gr4,gr5,gr4
0300     movgs       gr4,damlr8
0301     add     gr4,gr5,gr4
0302     movgs       gr4,damlr9
0303     add     gr4,gr5,gr4
0304     movgs       gr4,damlr10
0305 
0306     movgs       gr0,dampr2
0307     movgs       gr0,dampr4
0308     movgs       gr0,dampr5
0309     movgs       gr0,dampr6
0310     movgs       gr0,dampr7
0311     movgs       gr0,dampr8
0312     movgs       gr0,dampr9
0313     movgs       gr0,dampr10
0314 
0315     movgs       gr0,iamlr3
0316     movgs       gr0,iamlr4
0317     movgs       gr0,iamlr5
0318     movgs       gr0,iamlr6
0319     movgs       gr0,iamlr7
0320 
0321     movgs       gr0,iampr2
0322     movgs       gr0,iampr3
0323     movgs       gr0,iampr4
0324     movgs       gr0,iampr5
0325     movgs       gr0,iampr6
0326     movgs       gr0,iampr7
0327 
0328     # start in TLB context 0 with the swapper's page tables
0329     movgs       gr0,cxnr
0330 
0331     sethi.p     %hi(swapper_pg_dir),gr4
0332     setlo       %lo(swapper_pg_dir),gr4
0333     sethi.p     %hi(__page_offset),gr5
0334     setlo       %lo(__page_offset),gr5
0335     sub     gr4,gr5,gr4
0336     movgs       gr4,ttbr
0337     setlos      #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
0338     or      gr4,gr5,gr4
0339     movgs       gr4,dampr3
0340 
0341     # the FR451 also has an extra trap base register
0342     movsg       tbr,gr4
0343     movgs       gr4,btbr
0344 
0345     LEDS        0x3300
0346     jmpl        @(gr27,gr0)
0347 
0348 ###############################################################################
0349 #
0350 # finish setting up the protection registers
0351 #
0352 ###############################################################################
0353     .globl      __head_fr451_finalise_protection
0354 __head_fr451_finalise_protection:
0355     # turn on the timers as appropriate
0356     movgs       gr0,timerh
0357     movgs       gr0,timerl
0358     movgs       gr0,timerd
0359     movsg       hsr0,gr4
0360     sethi.p     %hi(HSR0_ETMI),gr5
0361     setlo       %lo(HSR0_ETMI),gr5
0362     or      gr4,gr5,gr4
0363     movgs       gr4,hsr0
0364 
0365     # clear the TLB entry cache
0366     movgs       gr0,iamlr1
0367     movgs       gr0,iampr1
0368     movgs       gr0,damlr1
0369     movgs       gr0,dampr1
0370 
0371     # clear the PGE cache
0372     sethi.p     %hi(__flush_tlb_all),gr4
0373     setlo       %lo(__flush_tlb_all),gr4
0374     jmpl        @(gr4,gr0)