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0001 /*
0002  * DRAM/SDRAM initialization - alter with care
0003  * This file is intended to be included from other assembler files
0004  *
0005  * Note: This file may not modify r9 because r9 is used to carry
0006  *       information from the decompressor to the kernel
0007  *
0008  * Copyright (C) 2000-2012 Axis Communications AB
0009  *
0010  */
0011 
0012 /* Just to be certain the config file is included, we include it here
0013  * explicitly instead of depending on it being included in the file that
0014  * uses this code.
0015  */
0016 
0017 
0018     ;; WARNING! The registers r8 and r9 are used as parameters carrying
0019     ;; information from the decompressor (if the kernel was compressed).
0020     ;; They should not be used in the code below.
0021 
0022     move.d   CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
0023     move.d   $r0, [R_WAITSTATES]
0024 
0025     move.d   CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
0026     move.d   $r0, [R_BUS_CONFIG]
0027 
0028 #ifndef CONFIG_ETRAX_SDRAM
0029     move.d   CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
0030     move.d   $r0, [R_DRAM_CONFIG]
0031 
0032     move.d   CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
0033     move.d   $r0, [R_DRAM_TIMING]
0034 #else
0035     ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
0036     moveq    2, $r6 
0037 _sdram_init:
0038 
0039     ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
0040 
0041     ; Bank configuration
0042     move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
0043     move.d   $r0, [R_SDRAM_CONFIG]
0044 
0045     ; Calculate value of mrs_data
0046     ; CAS latency = 2 && bus_width = 32 => 0x40
0047     ; CAS latency = 3 && bus_width = 32 => 0x60
0048     ; CAS latency = 2 && bus_width = 16 => 0x20
0049     ; CAS latency = 3 && bus_width = 16 => 0x30
0050 
0051     ; Check if value is already supplied in kernel config
0052     move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
0053     and.d    0x00ff0000, $r2
0054     bne  _set_timing
0055     lsrq     16, $r2
0056 
0057     move.d   0x40, $r2       ; Assume 32 bits and CAS latency = 2
0058     move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
0059     move.d   $r1, $r3
0060     and.d    0x03, $r1       ; Get CAS latency
0061     and.d    0x1000, $r3     ; 50 or 100 MHz?
0062     beq      _speed_50
0063     nop
0064 _speed_100:
0065     cmp.d    0x00, $r1  ; CAS latency = 2?
0066     beq      _bw_check
0067     nop
0068     or.d     0x20, $r2  ; CAS latency = 3
0069     ba       _bw_check
0070     nop
0071 _speed_50:
0072     cmp.d    0x01, $r1  ; CAS latency = 2?
0073     beq      _bw_check
0074     nop
0075     or.d     0x20, $r2       ; CAS latency = 3
0076 _bw_check:
0077     move.d   CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
0078     and.d    0x800000, $r1  ; DRAM width is bit 23
0079     bne      _set_timing
0080     nop
0081     lsrq     1, $r2     ;  16 bits. Shift down value.
0082 
0083     ; Set timing parameters. Starts master clock
0084 _set_timing:
0085     move.d   CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
0086     and.d    0x8000f9ff, $r1 ; Make sure mrs data and command is 0
0087     or.d     0x80000000, $r1    ; Make sure sdram enable bit is set
0088     move.d   $r1, $r5
0089     or.d     0x0000c000, $r1 ; ref = disable
0090     lslq     16, $r2        ; mrs data starts at bit 16
0091     or.d     $r2, $r1
0092     move.d   $r1, [R_SDRAM_TIMING]
0093 
0094     ; Wait 200us
0095     move.d   10000, $r2
0096 1:  bne      1b
0097     subq     1, $r2
0098 
0099     ; Issue initialization command sequence
0100     move.d   _sdram_commands_start, $r2
0101     and.d    0x000fffff, $r2 ; Make sure commands are read from flash
0102     move.d   _sdram_commands_end,  $r3
0103     and.d    0x000fffff, $r3
0104 1:  clear.d  $r4
0105     move.b   [$r2+], $r4
0106     lslq     9, $r4 ; Command starts at bit 9
0107     or.d     $r1, $r4
0108     move.d   $r4, [R_SDRAM_TIMING]
0109     nop     ; Wait five nop cycles between each command
0110     nop
0111     nop
0112     nop
0113     nop
0114     cmp.d    $r2, $r3
0115     bne      1b
0116     nop
0117     move.d   $r5, [R_SDRAM_TIMING]
0118     subq     1, $r6
0119     bne      _sdram_init
0120     nop
0121     ba       _sdram_commands_end
0122     nop
0123 
0124 _sdram_commands_start:
0125     .byte   3   ; Precharge
0126     .byte   0       ; nop
0127     .byte   2   ; refresh
0128     .byte   0   ; nop
0129     .byte   2   ; refresh
0130     .byte   0   ; nop
0131     .byte   2   ; refresh
0132     .byte   0   ; nop
0133     .byte   2   ; refresh
0134     .byte   0   ; nop
0135     .byte   2   ; refresh
0136     .byte   0   ; nop
0137     .byte   2   ; refresh
0138     .byte   0   ; nop
0139     .byte   2   ; refresh
0140     .byte   0   ; nop
0141     .byte   2   ; refresh
0142     .byte   0   ; nop
0143     .byte   1   ; mrs
0144     .byte   0   ; nop
0145 _sdram_commands_end:
0146 #endif