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0001 /*
0002  *  linux/arch/arm/kernel/head-nommu.S
0003  *
0004  *  Copyright (C) 1994-2002 Russell King
0005  *  Copyright (C) 2003-2006 Hyok S. Choi
0006  *
0007  * This program is free software; you can redistribute it and/or modify
0008  * it under the terms of the GNU General Public License version 2 as
0009  * published by the Free Software Foundation.
0010  *
0011  *  Common kernel startup code (non-paged MM)
0012  *
0013  */
0014 #include <linux/linkage.h>
0015 #include <linux/init.h>
0016 
0017 #include <asm/assembler.h>
0018 #include <asm/ptrace.h>
0019 #include <asm/asm-offsets.h>
0020 #include <asm/memory.h>
0021 #include <asm/cp15.h>
0022 #include <asm/thread_info.h>
0023 #include <asm/v7m.h>
0024 #include <asm/mpu.h>
0025 #include <asm/page.h>
0026 
0027 /*
0028  * Kernel startup entry point.
0029  * ---------------------------
0030  *
0031  * This is normally called from the decompressor code.  The requirements
0032  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
0033  * r1 = machine nr.
0034  *
0035  * See linux/arch/arm/tools/mach-types for the complete list of machine
0036  * numbers for r1.
0037  *
0038  */
0039 
0040     __HEAD
0041 
0042 #ifdef CONFIG_CPU_THUMBONLY
0043     .thumb
0044 ENTRY(stext)
0045 #else
0046     .arm
0047 ENTRY(stext)
0048 
0049  THUMB( badr    r9, 1f      )   @ Kernel is always entered in ARM.
0050  THUMB( bx  r9      )   @ If this is a Thumb-2 kernel,
0051  THUMB( .thumb          )   @ switch to Thumb now.
0052  THUMB(1:           )
0053 #endif
0054 
0055     setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
0056                         @ and irqs disabled
0057 #if defined(CONFIG_CPU_CP15)
0058     mrc p15, 0, r9, c0, c0      @ get processor id
0059 #elif defined(CONFIG_CPU_V7M)
0060     ldr r9, =BASEADDR_V7M_SCB
0061     ldr r9, [r9, V7M_SCB_CPUID]
0062 #else
0063     ldr r9, =CONFIG_PROCESSOR_ID
0064 #endif
0065     bl  __lookup_processor_type     @ r5=procinfo r9=cpuid
0066     movs    r10, r5             @ invalid processor (r5=0)?
0067     beq __error_p               @ yes, error 'p'
0068 
0069 #ifdef CONFIG_ARM_MPU
0070     /* Calculate the size of a region covering just the kernel */
0071     ldr r5, =PLAT_PHYS_OFFSET       @ Region start: PHYS_OFFSET
0072     ldr     r6, =(_end)         @ Cover whole kernel
0073     sub r6, r6, r5          @ Minimum size of region to map
0074     clz r6, r6              @ Region size must be 2^N...
0075     rsb r6, r6, #31         @ ...so round up region size
0076     lsl r6, r6, #MPU_RSR_SZ     @ Put size in right field
0077     orr r6, r6, #(1 << MPU_RSR_EN)  @ Set region enabled bit
0078     bl  __setup_mpu
0079 #endif
0080 
0081     badr    lr, 1f              @ return (PIC) address
0082     ldr r12, [r10, #PROCINFO_INITFUNC]
0083     add r12, r12, r10
0084     ret r12
0085 1:  bl  __after_proc_init
0086     b   __mmap_switched
0087 ENDPROC(stext)
0088 
0089 #ifdef CONFIG_SMP
0090     .text
0091 ENTRY(secondary_startup)
0092     /*
0093      * Common entry point for secondary CPUs.
0094      *
0095      * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
0096      * the processor type - there is no need to check the machine type
0097      * as it has already been validated by the primary processor.
0098      */
0099     setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
0100 #ifndef CONFIG_CPU_CP15
0101     ldr r9, =CONFIG_PROCESSOR_ID
0102 #else
0103     mrc p15, 0, r9, c0, c0      @ get processor id
0104 #endif
0105     bl  __lookup_processor_type     @ r5=procinfo r9=cpuid
0106     movs    r10, r5             @ invalid processor?
0107     beq __error_p           @ yes, error 'p'
0108 
0109     ldr r7, __secondary_data
0110 
0111 #ifdef CONFIG_ARM_MPU
0112     /* Use MPU region info supplied by __cpu_up */
0113     ldr r6, [r7]            @ get secondary_data.mpu_szr
0114     bl      __setup_mpu         @ Initialize the MPU
0115 #endif
0116 
0117     badr    lr, 1f              @ return (PIC) address
0118     ldr r12, [r10, #PROCINFO_INITFUNC]
0119     add r12, r12, r10
0120     ret r12
0121 1:  bl  __after_proc_init
0122     ldr sp, [r7, #12]           @ set up the stack pointer
0123     mov fp, #0
0124     b   secondary_start_kernel
0125 ENDPROC(secondary_startup)
0126 
0127     .type   __secondary_data, %object
0128 __secondary_data:
0129     .long   secondary_data
0130 #endif /* CONFIG_SMP */
0131 
0132 /*
0133  * Set the Control Register and Read the process ID.
0134  */
0135 __after_proc_init:
0136 #ifdef CONFIG_CPU_CP15
0137     /*
0138      * CP15 system control register value returned in r0 from
0139      * the CPU init function.
0140      */
0141 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
0142     orr r0, r0, #CR_A
0143 #else
0144     bic r0, r0, #CR_A
0145 #endif
0146 #ifdef CONFIG_CPU_DCACHE_DISABLE
0147     bic r0, r0, #CR_C
0148 #endif
0149 #ifdef CONFIG_CPU_BPREDICT_DISABLE
0150     bic r0, r0, #CR_Z
0151 #endif
0152 #ifdef CONFIG_CPU_ICACHE_DISABLE
0153     bic r0, r0, #CR_I
0154 #endif
0155 #ifdef CONFIG_CPU_HIGH_VECTOR
0156     orr r0, r0, #CR_V
0157 #else
0158     bic r0, r0, #CR_V
0159 #endif
0160     mcr p15, 0, r0, c1, c0, 0       @ write control reg
0161 #elif defined (CONFIG_CPU_V7M)
0162     /* For V7M systems we want to modify the CCR similarly to the SCTLR */
0163 #ifdef CONFIG_CPU_DCACHE_DISABLE
0164     bic r0, r0, #V7M_SCB_CCR_DC
0165 #endif
0166 #ifdef CONFIG_CPU_BPREDICT_DISABLE
0167     bic r0, r0, #V7M_SCB_CCR_BP
0168 #endif
0169 #ifdef CONFIG_CPU_ICACHE_DISABLE
0170     bic r0, r0, #V7M_SCB_CCR_IC
0171 #endif
0172     movw    r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
0173     movt    r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
0174     str r0, [r3]
0175 #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
0176     ret lr
0177 ENDPROC(__after_proc_init)
0178     .ltorg
0179 
0180 #ifdef CONFIG_ARM_MPU
0181 
0182 
0183 /* Set which MPU region should be programmed */
0184 .macro set_region_nr tmp, rgnr
0185     mov \tmp, \rgnr         @ Use static region numbers
0186     mcr p15, 0, \tmp, c6, c2, 0     @ Write RGNR
0187 .endm
0188 
0189 /* Setup a single MPU region, either D or I side (D-side for unified) */
0190 .macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
0191     mcr p15, 0, \bar, c6, c1, (0 + \side)   @ I/DRBAR
0192     mcr p15, 0, \acr, c6, c1, (4 + \side)   @ I/DRACR
0193     mcr p15, 0, \sr, c6, c1, (2 + \side)        @ I/DRSR
0194 .endm
0195 
0196 /*
0197  * Setup the MPU and initial MPU Regions. We create the following regions:
0198  * Region 0: Use this for probing the MPU details, so leave disabled.
0199  * Region 1: Background region - covers the whole of RAM as strongly ordered
0200  * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
0201  * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
0202  *
0203  * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
0204 */
0205 
0206 ENTRY(__setup_mpu)
0207 
0208     /* Probe for v7 PMSA compliance */
0209     mrc p15, 0, r0, c0, c1, 4       @ Read ID_MMFR0
0210     and r0, r0, #(MMFR0_PMSA)       @ PMSA field
0211     teq r0, #(MMFR0_PMSAv7)     @ PMSA v7
0212     bne __error_p           @ Fail: ARM_MPU on NOT v7 PMSA
0213 
0214     /* Determine whether the D/I-side memory map is unified. We set the
0215      * flags here and continue to use them for the rest of this function */
0216     mrc p15, 0, r0, c0, c0, 4       @ MPUIR
0217     ands    r5, r0, #MPUIR_DREGION_SZMASK   @ 0 size d region => No MPU
0218     beq __error_p           @ Fail: ARM_MPU and no MPU
0219     tst r0, #MPUIR_nU           @ MPUIR_nU = 0 for unified
0220 
0221     /* Setup second region first to free up r6 */
0222     set_region_nr r0, #MPU_RAM_REGION
0223     isb
0224     /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
0225     ldr r0, =PLAT_PHYS_OFFSET       @ RAM starts at PHYS_OFFSET
0226     ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
0227 
0228     setup_region r0, r5, r6, MPU_DATA_SIDE  @ PHYS_OFFSET, shared, enabled
0229     beq 1f              @ Memory-map not unified
0230     setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
0231 1:  isb
0232 
0233     /* First/background region */
0234     set_region_nr r0, #MPU_BG_REGION
0235     isb
0236     /* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
0237     mov r0, #0              @ BG region starts at 0x0
0238     ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
0239     mov r6, #MPU_RSR_ALL_MEM        @ 4GB region, enabled
0240 
0241     setup_region r0, r5, r6, MPU_DATA_SIDE  @ 0x0, BG region, enabled
0242     beq 2f              @ Memory-map not unified
0243     setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
0244 2:  isb
0245 
0246     /* Vectors region */
0247     set_region_nr r0, #MPU_VECTORS_REGION
0248     isb
0249     /* Shared, inaccessible to PL0, rw PL1 */
0250     mov r0, #CONFIG_VECTORS_BASE    @ Cover from VECTORS_BASE
0251     ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
0252     /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
0253     mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
0254 
0255     setup_region r0, r5, r6, MPU_DATA_SIDE  @ VECTORS_BASE, PL0 NA, enabled
0256     beq 3f              @ Memory-map not unified
0257     setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
0258 3:  isb
0259 
0260     /* Enable the MPU */
0261     mrc p15, 0, r0, c1, c0, 0       @ Read SCTLR
0262     bic     r0, r0, #CR_BR          @ Disable the 'default mem-map'
0263     orr r0, r0, #CR_M           @ Set SCTRL.M (MPU on)
0264     mcr p15, 0, r0, c1, c0, 0       @ Enable MPU
0265     isb
0266     ret lr
0267 ENDPROC(__setup_mpu)
0268 #endif
0269 #include "head-common.S"