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0001 /*
0002  * TLB Exception Handling for ARC
0003  *
0004  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License version 2 as
0008  * published by the Free Software Foundation.
0009  *
0010  * Vineetg: April 2011 :
0011  *  -MMU v1: moved out legacy code into a seperate file
0012  *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
0013  *      helps avoid a shift when preparing PD0 from PTE
0014  *
0015  * Vineetg: July 2009
0016  *  -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
0017  *   entry, so that it doesn't knock out it's I-TLB entry
0018  *  -Some more fine tuning:
0019  *   bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
0020  *
0021  * Vineetg: July 2009
0022  *  -Practically rewrote the I/D TLB Miss handlers
0023  *   Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
0024  *   Hence Leaner by 1.5 K
0025  *   Used Conditional arithmetic to replace excessive branching
0026  *   Also used short instructions wherever possible
0027  *
0028  * Vineetg: Aug 13th 2008
0029  *  -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
0030  *   more information in case of a Fatality
0031  *
0032  * Vineetg: March 25th Bug #92690
0033  *  -Added Debug Code to check if sw-ASID == hw-ASID
0034 
0035  * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
0036  */
0037 
0038 #include <linux/linkage.h>
0039 #include <asm/entry.h>
0040 #include <asm/mmu.h>
0041 #include <asm/pgtable.h>
0042 #include <asm/arcregs.h>
0043 #include <asm/cache.h>
0044 #include <asm/processor.h>
0045 #include <asm/tlb-mmu1.h>
0046 
0047 #ifdef CONFIG_ISA_ARCOMPACT
0048 ;-----------------------------------------------------------------
0049 ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
0050 ; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
0051 ;
0052 ; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
0053 ; "global" is used to free-up FIRST core reg to be able to code the rest of
0054 ; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
0055 ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
0056 ; need to be saved as well by extending the "global" to be 4 words. Hence
0057 ;   ".size   ex_saved_reg1, 16"
0058 ; [All of this dance is to avoid stack switching for each TLB Miss, since we
0059 ; only need to save only a handful of regs, as opposed to complete reg file]
0060 ;
0061 ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
0062 ; core reg as it will not be SMP safe.
0063 ; Thus scratch AUX reg is used (and no longer used to cache task PGD).
0064 ; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
0065 ; Epilogue thus has to locate the "per-cpu" storage for regs.
0066 ; To avoid cache line bouncing the per-cpu global is aligned/sized per
0067 ; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
0068 ;   ".size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
0069 
0070 ; As simple as that....
0071 ;--------------------------------------------------------------------------
0072 
0073 ; scratch memory to save [r0-r3] used to code TLB refill Handler
0074 ARCFP_DATA ex_saved_reg1
0075     .align 1 << L1_CACHE_SHIFT
0076     .type   ex_saved_reg1, @object
0077 #ifdef CONFIG_SMP
0078     .size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
0079 ex_saved_reg1:
0080     .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
0081 #else
0082     .size   ex_saved_reg1, 16
0083 ex_saved_reg1:
0084     .zero 16
0085 #endif
0086 
0087 .macro TLBMISS_FREEUP_REGS
0088 #ifdef CONFIG_SMP
0089     sr  r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
0090     GET_CPU_ID  r0          ; get to per cpu scratch mem,
0091     asl r0, r0, L1_CACHE_SHIFT  ; cache line wide per cpu
0092     add r0, @ex_saved_reg1, r0
0093 #else
0094     st    r0, [@ex_saved_reg1]
0095     mov_s r0, @ex_saved_reg1
0096 #endif
0097     st_s  r1, [r0, 4]
0098     st_s  r2, [r0, 8]
0099     st_s  r3, [r0, 12]
0100 
0101     ; VERIFY if the ASID in MMU-PID Reg is same as
0102     ; one in Linux data structures
0103 
0104     tlb_paranoid_check_asm
0105 .endm
0106 
0107 .macro TLBMISS_RESTORE_REGS
0108 #ifdef CONFIG_SMP
0109     GET_CPU_ID  r0          ; get to per cpu scratch mem
0110     asl r0, r0, L1_CACHE_SHIFT  ; each is cache line wide
0111     add r0, @ex_saved_reg1, r0
0112     ld_s  r3, [r0,12]
0113     ld_s  r2, [r0, 8]
0114     ld_s  r1, [r0, 4]
0115     lr    r0, [ARC_REG_SCRATCH_DATA0]
0116 #else
0117     mov_s r0, @ex_saved_reg1
0118     ld_s  r3, [r0,12]
0119     ld_s  r2, [r0, 8]
0120     ld_s  r1, [r0, 4]
0121     ld_s  r0, [r0]
0122 #endif
0123 .endm
0124 
0125 #else   /* ARCv2 */
0126 
0127 .macro TLBMISS_FREEUP_REGS
0128     PUSH  r0
0129     PUSH  r1
0130     PUSH  r2
0131     PUSH  r3
0132 .endm
0133 
0134 .macro TLBMISS_RESTORE_REGS
0135     POP   r3
0136     POP   r2
0137     POP   r1
0138     POP   r0
0139 .endm
0140 
0141 #endif
0142 
0143 ;============================================================================
0144 ;  Troubleshooting Stuff
0145 ;============================================================================
0146 
0147 ; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
0148 ; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
0149 ; we use the MMU PID Reg to get current ASID.
0150 ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
0151 ; So we try to detect this in TLB Mis shandler
0152 
0153 .macro tlb_paranoid_check_asm
0154 
0155 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
0156 
0157     GET_CURR_TASK_ON_CPU  r3
0158     ld r0, [r3, TASK_ACT_MM]
0159     ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
0160     breq r0, 0, 55f ; Error if no ASID allocated
0161 
0162     lr r1, [ARC_REG_PID]
0163     and r1, r1, 0xFF
0164 
0165     and r2, r0, 0xFF    ; MMU PID bits only for comparison
0166     breq r1, r2, 5f
0167 
0168 55:
0169     ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
0170     lr  r2, [erstatus]
0171     bbit0 r2, STATUS_U_BIT, 5f
0172 
0173     ; We sure are in troubled waters, Flag the error, but to do so
0174     ; need to switch to kernel mode stack to call error routine
0175     GET_TSK_STACK_BASE   r3, sp
0176 
0177     ; Call printk to shoutout aloud
0178     mov r2, 1
0179     j print_asid_mismatch
0180 
0181 5:  ; ASIDs match so proceed normally
0182     nop
0183 
0184 #endif
0185 
0186 .endm
0187 
0188 ;============================================================================
0189 ;TLB Miss handling Code
0190 ;============================================================================
0191 
0192 ;-----------------------------------------------------------------------------
0193 ; This macro does the page-table lookup for the faulting address.
0194 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
0195 .macro LOAD_FAULT_PTE
0196 
0197     lr  r2, [efa]
0198 
0199 #ifndef CONFIG_SMP
0200     lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
0201 #else
0202     GET_CURR_TASK_ON_CPU  r1
0203     ld  r1, [r1, TASK_ACT_MM]
0204     ld  r1, [r1, MM_PGD]
0205 #endif
0206 
0207     lsr     r0, r2, PGDIR_SHIFT     ; Bits for indexing into PGD
0208     ld.as   r3, [r1, r0]            ; PGD entry corresp to faulting addr
0209     tst r3, r3
0210     bz  do_slow_path_pf         ; if no Page Table, do page fault
0211 
0212 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0213     and.f   0, r3, _PAGE_HW_SZ  ; Is this Huge PMD (thp)
0214     add2.nz r1, r1, r0
0215     bnz.d   2f      ; YES: PGD == PMD has THP PTE: stop pgd walk
0216     mov.nz  r0, r3
0217 
0218 #endif
0219     and r1, r3, PAGE_MASK
0220 
0221     ; Get the PTE entry: The idea is
0222     ; (1) x = addr >> PAGE_SHIFT    -> masks page-off bits from @fault-addr
0223     ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
0224     ; (3) z = (pgtbl + y * 4)
0225 
0226 #ifdef CONFIG_ARC_HAS_PAE40
0227 #define PTE_SIZE_LOG    3   /* 8 == 2 ^ 3 */
0228 #else
0229 #define PTE_SIZE_LOG    2   /* 4 == 2 ^ 2 */
0230 #endif
0231 
0232     ; multiply in step (3) above avoided by shifting lesser in step (1)
0233     lsr     r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
0234     and     r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
0235     ld.aw   r0, [r1, r0]            ; r0: PTE (lower word only for PAE40)
0236                     ; r1: PTE ptr
0237 
0238 2:
0239 
0240 .endm
0241 
0242 ;-----------------------------------------------------------------
0243 ; Convert Linux PTE entry into TLB entry
0244 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
0245 ;    (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
0246 ; IN: r0 = PTE, r1 = ptr to PTE
0247 
0248 .macro CONV_PTE_TO_TLB
0249     and    r3, r0, PTE_BITS_RWX ;          r  w  x
0250     asl    r2, r3, 3        ; Kr Kw Kx 0  0  0 (GLOBAL, kernel only)
0251     and.f  0,  r0, _PAGE_GLOBAL
0252     or.z   r2, r2, r3       ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
0253 
0254     and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
0255     or  r3, r3, r2
0256 
0257     sr  r3, [ARC_REG_TLBPD1]        ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
0258 #ifdef  CONFIG_ARC_HAS_PAE40
0259     ld  r3, [r1, 4]     ; paddr[39..32]
0260     sr  r3, [ARC_REG_TLBPD1HI]
0261 #endif
0262 
0263     and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
0264 
0265     lr  r3,[ARC_REG_TLBPD0]     ; MMU prepares PD0 with vaddr and asid
0266 
0267     or  r3, r3, r2              ; S | vaddr | {sasid|asid}
0268     sr  r3,[ARC_REG_TLBPD0]     ; rewrite PD0
0269 .endm
0270 
0271 ;-----------------------------------------------------------------
0272 ; Commit the TLB entry into MMU
0273 
0274 .macro COMMIT_ENTRY_TO_MMU
0275 #if (CONFIG_ARC_MMU_VER < 4)
0276 
0277     /* Get free TLB slot: Set = computed from vaddr, way = random */
0278     sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
0279 
0280     /* Commit the Write */
0281 #if (CONFIG_ARC_MMU_VER >= 2)   /* introduced in v2 */
0282     sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
0283 #else
0284     sr TLBWrite, [ARC_REG_TLBCOMMAND]
0285 #endif
0286 
0287 #else
0288     sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
0289 #endif
0290 .endm
0291 
0292 
0293 ARCFP_CODE  ;Fast Path Code, candidate for ICCM
0294 
0295 ;-----------------------------------------------------------------------------
0296 ; I-TLB Miss Exception Handler
0297 ;-----------------------------------------------------------------------------
0298 
0299 ENTRY(EV_TLBMissI)
0300 
0301     TLBMISS_FREEUP_REGS
0302 
0303     ;----------------------------------------------------------------
0304     ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
0305     LOAD_FAULT_PTE
0306 
0307     ;----------------------------------------------------------------
0308     ; VERIFY_PTE: Check if PTE permissions approp for executing code
0309     cmp_s   r2, VMALLOC_START
0310     mov_s   r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
0311     or.hs   r2, r2, _PAGE_GLOBAL
0312 
0313     and     r3, r0, r2  ; Mask out NON Flag bits from PTE
0314     xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )
0315     bnz     do_slow_path_pf
0316 
0317     ; Let Linux VM know that the page was accessed
0318     or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit
0319     st_s    r0, [r1]                ; Write back PTE
0320 
0321     CONV_PTE_TO_TLB
0322     COMMIT_ENTRY_TO_MMU
0323     TLBMISS_RESTORE_REGS
0324 EV_TLBMissI_fast_ret:   ; additional label for VDK OS-kit instrumentation
0325     rtie
0326 
0327 END(EV_TLBMissI)
0328 
0329 ;-----------------------------------------------------------------------------
0330 ; D-TLB Miss Exception Handler
0331 ;-----------------------------------------------------------------------------
0332 
0333 ENTRY(EV_TLBMissD)
0334 
0335     TLBMISS_FREEUP_REGS
0336 
0337     ;----------------------------------------------------------------
0338     ; Get the PTE corresponding to V-addr accessed
0339     ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
0340     LOAD_FAULT_PTE
0341 
0342     ;----------------------------------------------------------------
0343     ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
0344 
0345     cmp_s   r2, VMALLOC_START
0346     mov_s   r2, _PAGE_PRESENT   ; common bit for K/U PTE
0347     or.hs   r2, r2, _PAGE_GLOBAL    ; kernel PTE only
0348 
0349     ; Linux PTE [RWX] bits are semantically overloaded:
0350     ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
0351     ; -Otherwise they are user-mode permissions, and those are exactly
0352     ;  same for kernel mode as well (e.g. copy_(to|from)_user)
0353 
0354     lr      r3, [ecr]
0355     btst_s  r3, ECR_C_BIT_DTLB_LD_MISS  ; Read Access
0356     or.nz   r2, r2, _PAGE_READ          ; chk for Read flag in PTE
0357     btst_s  r3, ECR_C_BIT_DTLB_ST_MISS  ; Write Access
0358     or.nz   r2, r2, _PAGE_WRITE         ; chk for Write flag in PTE
0359     ; Above laddering takes care of XCHG access (both R and W)
0360 
0361     ; By now, r2 setup with all the Flags we need to check in PTE
0362     and     r3, r0, r2              ; Mask out NON Flag bits from PTE
0363     brne.d  r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
0364 
0365     ;----------------------------------------------------------------
0366     ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
0367     lr      r3, [ecr]
0368     or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
0369     btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?
0370     or.nz   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
0371     st_s    r0, [r1]                      ; Write back PTE
0372 
0373     CONV_PTE_TO_TLB
0374 
0375 #if (CONFIG_ARC_MMU_VER == 1)
0376     ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
0377     ; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
0378     ; But only for old MMU or one with Metal Fix
0379     TLB_WRITE_HEURISTICS
0380 #endif
0381 
0382     COMMIT_ENTRY_TO_MMU
0383     TLBMISS_RESTORE_REGS
0384 EV_TLBMissD_fast_ret:   ; additional label for VDK OS-kit instrumentation
0385     rtie
0386 
0387 ;-------- Common routine to call Linux Page Fault Handler -----------
0388 do_slow_path_pf:
0389 
0390     ; Restore the 4-scratch regs saved by fast path miss handler
0391     TLBMISS_RESTORE_REGS
0392 
0393     ; Slow path TLB Miss handled as a regular ARC Exception
0394     ; (stack switching / save the complete reg-file).
0395     b  call_do_page_fault
0396 END(EV_TLBMissD)