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0001 /*
0002  * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
0003  *
0004  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
0005  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0006  *
0007  * This program is free software; you can redistribute it and/or modify
0008  * it under the terms of the GNU General Public License version 2 as
0009  * published by the Free Software Foundation.
0010  *
0011  * vineetg: May 2011
0012  *  -Userspace unaligned access emulation
0013  *
0014  * vineetg: Feb 2011 (ptrace low level code fixes)
0015  *  -traced syscall return code (r0) was not saved into pt_regs for restoring
0016  *   into user reg-file when traded task rets to user space.
0017  *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
0018  *   were not invoking post-syscall trace hook (jumping directly into
0019  *   ret_from_system_call)
0020  *
0021  * vineetg: Nov 2010:
0022  *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
0023  *  -To maintain the slot size of 8 bytes/vector, added nop, which is
0024  *   not executed at runtime.
0025  *
0026  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
0027  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
0028  *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
0029  *   need ptregs anymore
0030  *
0031  * Vineetg: Oct 2009
0032  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
0033  *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
0034  *   active (AE bit enabled).  This causes a double fault for a subseq valid
0035  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
0036  *   Instr Error could also cause similar scenario, so same there as well.
0037  *
0038  * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
0039  *
0040  * Vineetg: Aug 28th 2008: Bug #94984
0041  *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
0042  *   Normally CPU does this automatically, however when doing FAKE rtie,
0043  *   we need to explicitly do this. The problem in macros
0044  *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
0045  *   was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
0046  *   setting it and not clearing it clears ZOL context
0047  *
0048  * Vineetg: May 16th, 2008
0049  *  - r25 now contains the Current Task when in kernel
0050  *
0051  * Vineetg: Dec 22, 2007
0052  *    Minor Surgery of Low Level ISR to make it SMP safe
0053  *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
0054  *    - _current_task is made an array of NR_CPUS
0055  *    - Access of _current_task wrapped inside a macro so that if hardware
0056  *       team agrees for a dedicated reg, no other code is touched
0057  *
0058  * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
0059  */
0060 
0061 #include <linux/errno.h>
0062 #include <linux/linkage.h>  /* {EXTRY,EXIT} */
0063 #include <asm/entry.h>
0064 #include <asm/irqflags.h>
0065 
0066     .cpu A7
0067 
0068 ;############################ Vector Table #################################
0069 
0070 .macro VECTOR  lbl
0071 #if 1   /* Just in case, build breaks */
0072     j   \lbl
0073 #else
0074     b   \lbl
0075     nop
0076 #endif
0077 .endm
0078 
0079     .section .vector, "ax",@progbits
0080     .align 4
0081 
0082 /* Each entry in the vector table must occupy 2 words. Since it is a jump
0083  * across sections (.vector to .text) we are gauranteed that 'j somewhere'
0084  * will use the 'j limm' form of the intrsuction as long as somewhere is in
0085  * a section other than .vector.
0086  */
0087 
0088 ; ********* Critical System Events **********************
0089 VECTOR   res_service             ; 0x0, Reset Vector    (0x0)
0090 VECTOR   mem_service             ; 0x8, Mem exception   (0x1)
0091 VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)
0092 
0093 ; ******************** Device ISRs **********************
0094 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
0095 VECTOR   handle_interrupt_level2
0096 #else
0097 VECTOR   handle_interrupt_level1
0098 #endif
0099 
0100 .rept   28
0101 VECTOR   handle_interrupt_level1 ; Other devices
0102 .endr
0103 
0104 /* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
0105 
0106 ; ******************** Exceptions **********************
0107 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
0108 VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
0109 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
0110 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
0111                  ;         or Misaligned Access
0112 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
0113 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
0114 VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
0115 
0116 .rept   24
0117 VECTOR   reserved                ; Reserved Exceptions
0118 .endr
0119 
0120 
0121 ;##################### Scratch Mem for IRQ stack switching #############
0122 
0123 ARCFP_DATA int1_saved_reg
0124     .align 32
0125     .type   int1_saved_reg, @object
0126     .size   int1_saved_reg, 4
0127 int1_saved_reg:
0128     .zero 4
0129 
0130 /* Each Interrupt level needs its own scratch */
0131 ARCFP_DATA int2_saved_reg
0132     .type   int2_saved_reg, @object
0133     .size   int2_saved_reg, 4
0134 int2_saved_reg:
0135     .zero 4
0136 
0137 ; ---------------------------------------------
0138     .section .text, "ax",@progbits
0139 
0140 
0141 reserved:
0142     flag 1      ; Unexpected event, halt
0143 
0144 ;##################### Interrupt Handling ##############################
0145 
0146 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
0147 ; ---------------------------------------------
0148 ;  Level 2 ISR: Can interrupt a Level 1 ISR
0149 ; ---------------------------------------------
0150 ENTRY(handle_interrupt_level2)
0151 
0152     INTERRUPT_PROLOGUE 2
0153 
0154     ;------------------------------------------------------
0155     ; if L2 IRQ interrupted a L1 ISR, disable preemption
0156     ;
0157     ; This is to avoid a potential L1-L2-L1 scenario
0158     ;  -L1 IRQ taken
0159     ;  -L2 interrupts L1 (before L1 ISR could run)
0160     ;  -preemption off IRQ, user task in syscall picked to run
0161     ;  -RTIE to userspace
0162     ;   Returns from L2 context fine
0163     ;   But both L1 and L2 re-enabled, so another L1 can be taken
0164     ;   while prev L1 is still unserviced
0165     ;
0166     ;------------------------------------------------------
0167 
0168     ; L2 interrupting L1 implies both L2 and L1 active
0169     ; However both A2 and A1 are NOT set in STATUS32, thus
0170     ; need to check STATUS32_L2 to determine if L1 was active
0171 
0172     ld r9, [sp, PT_status32]        ; get statu32_l2 (saved in pt_regs)
0173     bbit0 r9, STATUS_A1_BIT, 1f     ; L1 not active when L2 IRQ, so normal
0174 
0175     ; bump thread_info->preempt_count (Disable preemption)
0176     GET_CURR_THR_INFO_FROM_SP   r10
0177     ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
0178     add     r9, r9, 1
0179     st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
0180 
0181 1:
0182     ;------------------------------------------------------
0183     ; setup params for Linux common ISR and invoke it
0184     ;------------------------------------------------------
0185     lr  r0, [icause2]
0186     and r0, r0, 0x1f
0187 
0188     bl.d  @arch_do_IRQ
0189     mov r1, sp
0190 
0191     mov r8,0x2
0192     sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
0193 
0194     b   ret_from_exception
0195 
0196 END(handle_interrupt_level2)
0197 
0198 #endif
0199 
0200 ; ---------------------------------------------
0201 ; User Mode Memory Bus Error Interrupt Handler
0202 ; (Kernel mode memory errors handled via seperate exception vectors)
0203 ; ---------------------------------------------
0204 ENTRY(mem_service)
0205 
0206     INTERRUPT_PROLOGUE 2
0207 
0208     mov r0, ilink2
0209     mov r1, sp
0210 
0211     ; User process needs to be killed with SIGBUS, but first need to get
0212     ; out of the L2 interrupt context (drop to pure kernel mode) and jump
0213     ; off to "C" code where SIGBUS in enqueued
0214     lr  r3, [status32]
0215     bclr r3, r3, STATUS_A2_BIT
0216     or  r3, r3, (STATUS_E1_MASK|STATUS_E2_MASK)
0217     sr  r3, [status32_l2]
0218     mov ilink2, 1f
0219     rtie
0220 1:
0221     bl  do_memory_error
0222     b   ret_from_exception
0223 END(mem_service)
0224 
0225 ; ---------------------------------------------
0226 ;  Level 1 ISR
0227 ; ---------------------------------------------
0228 ENTRY(handle_interrupt_level1)
0229 
0230     INTERRUPT_PROLOGUE 1
0231 
0232     lr  r0, [icause1]
0233     and r0, r0, 0x1f
0234 
0235 #ifdef CONFIG_TRACE_IRQFLAGS
0236     ; icause1 needs to be read early, before calling tracing, which
0237     ; can clobber scratch regs, hence use of stack to stash it
0238     push r0
0239     TRACE_ASM_IRQ_DISABLE
0240     pop  r0
0241 #endif
0242 
0243     bl.d  @arch_do_IRQ
0244     mov r1, sp
0245 
0246     mov r8,0x1
0247     sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
0248 
0249     b   ret_from_exception
0250 END(handle_interrupt_level1)
0251 
0252 ;################### Non TLB Exception Handling #############################
0253 
0254 ; ---------------------------------------------
0255 ; Protection Violation Exception Handler
0256 ; ---------------------------------------------
0257 
0258 ENTRY(EV_TLBProtV)
0259 
0260     EXCEPTION_PROLOGUE
0261 
0262     mov r2, r9  ; ECR set into r9 already
0263     lr  r0, [efa]   ; Faulting Data address (not part of pt_regs saved above)
0264 
0265     ; Exception auto-disables further Intr/exceptions.
0266     ; Re-enable them by pretending to return from exception
0267     ; (so rest of handler executes in pure K mode)
0268 
0269     FAKE_RET_FROM_EXCPN
0270 
0271     mov   r1, sp    ; Handle to pt_regs
0272 
0273     ;------ (5) Type of Protection Violation? ----------
0274     ;
0275     ; ProtV Hardware Exception is triggered for Access Faults of 2 types
0276     ;   -Access Violaton    : 00_23_(00|01|02|03)_00
0277     ;                    x  r  w  r+w
0278     ;   -Unaligned Access   : 00_23_04_00
0279     ;
0280     bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
0281 
0282     ;========= (6a) Access Violation Processing ========
0283     bl  do_page_fault
0284     b   ret_from_exception
0285 
0286     ;========== (6b) Non aligned access ============
0287 4:
0288 
0289     SAVE_CALLEE_SAVED_USER
0290     mov r2, sp              ; callee_regs
0291 
0292     bl  do_misaligned_access
0293 
0294     ; TBD: optimize - do this only if a callee reg was involved
0295     ; either a dst of emulated LD/ST or src with address-writeback
0296     RESTORE_CALLEE_SAVED_USER
0297 
0298     b   ret_from_exception
0299 
0300 END(EV_TLBProtV)
0301 
0302 ; Wrapper for Linux page fault handler called from EV_TLBMiss*
0303 ; Very similar to ProtV handler case (6a) above, but avoids the extra checks
0304 ; for Misaligned access
0305 ;
0306 ENTRY(call_do_page_fault)
0307 
0308     EXCEPTION_PROLOGUE
0309     lr  r0, [efa]   ; Faulting Data address
0310     mov   r1, sp
0311     FAKE_RET_FROM_EXCPN
0312 
0313     mov blink, ret_from_exception
0314     b  do_page_fault
0315 
0316 END(call_do_page_fault)
0317 
0318 ;############# Common Handlers for ARCompact and ARCv2 ##############
0319 
0320 #include "entry.S"
0321 
0322 ;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
0323 ;
0324 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
0325 ; IRQ shd definitely not happen between now and rtie
0326 ; All 2 entry points to here already disable interrupts
0327 
0328 .Lrestore_regs:
0329 
0330     # Interrpts are actually disabled from this point on, but will get
0331     # reenabled after we return from interrupt/exception.
0332     # But irq tracer needs to be told now...
0333     TRACE_ASM_IRQ_ENABLE
0334 
0335     lr  r10, [status32]
0336 
0337     ; Restore REG File. In case multiple Events outstanding,
0338     ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
0339     ; Note that we use realtime STATUS32 (not pt_regs->status32) to
0340     ; decide that.
0341 
0342     and.f   0, r10, (STATUS_A1_MASK|STATUS_A2_MASK)
0343     bz  .Lexcep_or_pure_K_ret
0344 
0345     ; Returning from Interrupts (Level 1 or 2)
0346 
0347 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
0348 
0349     ; Level 2 interrupt return Path - from hardware standpoint
0350     bbit0  r10, STATUS_A2_BIT, not_level2_interrupt
0351 
0352     ;------------------------------------------------------------------
0353     ; However the context returning might not have taken L2 intr itself
0354     ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
0355     ; Special considerations needed for the context which took L2 intr
0356 
0357     ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
0358     brne r9, event_IRQ2, 149f
0359 
0360     ;------------------------------------------------------------------
0361     ; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
0362     ; so that sched doesn't move to new task, causing L1 to be delayed
0363     ; undeterministically. Now that we've achieved that, let's reset
0364     ; things to what they were, before returning from L2 context
0365     ;----------------------------------------------------------------
0366 
0367     ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
0368     bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal
0369 
0370     ; decrement thread_info->preempt_count (re-enable preemption)
0371     GET_CURR_THR_INFO_FROM_SP   r10
0372     ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
0373 
0374     ; paranoid check, given A1 was active when A2 happened, preempt count
0375     ; must not be 0 because we would have incremented it.
0376     ; If this does happen we simply HALT as it means a BUG !!!
0377     cmp     r9, 0
0378     bnz     2f
0379     flag 1
0380 
0381 2:
0382     sub     r9, r9, 1
0383     st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
0384 
0385 149:
0386     INTERRUPT_EPILOGUE 2    ; return from level 2 interrupt
0387 debug_marker_l2:
0388     rtie
0389 
0390 not_level2_interrupt:
0391 
0392 #endif
0393 
0394     INTERRUPT_EPILOGUE 1    ; return from level 1 interrupt
0395 debug_marker_l1:
0396     rtie
0397 
0398 .Lexcep_or_pure_K_ret:
0399 
0400     ;this case is for syscalls or Exceptions or pure kernel mode
0401 
0402     EXCEPTION_EPILOGUE
0403 debug_marker_syscall:
0404     rtie
0405 
0406 END(ret_from_exception)