selftests/sgx/test_encl_bootstrap.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright(c) 2016-20 Intel Corporation.
0004  */
0005
0006     .macro ENCLU
0007     .byte 0x0f, 0x01, 0xd7
0008     .endm
0009
0010     .section ".tcs", "aw"
0011     .balign 4096
0012
0013     .fill   1, 8, 0         # STATE (set by CPU)
0014     .fill   1, 8, 0         # FLAGS
0015     .quad   encl_ssa_tcs1       # OSSA
0016     .fill   1, 4, 0         # CSSA (set by CPU)
0017     .fill   1, 4, 1         # NSSA
0018     .quad   encl_entry      # OENTRY
0019     .fill   1, 8, 0         # AEP (set by EENTER and ERESUME)
0020     .fill   1, 8, 0         # OFSBASE
0021     .fill   1, 8, 0         # OGSBASE
0022     .fill   1, 4, 0xFFFFFFFF    # FSLIMIT
0023     .fill   1, 4, 0xFFFFFFFF    # GSLIMIT
0024     .fill   4024, 1, 0      # Reserved
0025
0026     # TCS2
0027     .fill   1, 8, 0         # STATE (set by CPU)
0028     .fill   1, 8, 0         # FLAGS
0029     .quad   encl_ssa_tcs2       # OSSA
0030     .fill   1, 4, 0         # CSSA (set by CPU)
0031     .fill   1, 4, 1         # NSSA
0032     .quad   encl_entry      # OENTRY
0033     .fill   1, 8, 0         # AEP (set by EENTER and ERESUME)
0034     .fill   1, 8, 0         # OFSBASE
0035     .fill   1, 8, 0         # OGSBASE
0036     .fill   1, 4, 0xFFFFFFFF    # FSLIMIT
0037     .fill   1, 4, 0xFFFFFFFF    # GSLIMIT
0038     .fill   4024, 1, 0      # Reserved
0039
0040     .text
0041
0042 encl_entry:
0043     # RBX contains the base address for TCS, which is the first address
0044     # inside the enclave for TCS #1 and one page into the enclave for
0045     # TCS #2. By adding the value of encl_stack to it, we get
0046     # the absolute address for the stack.
0047     lea (encl_stack)(%rbx), %rax
0048     jmp encl_entry_core
0049 encl_dyn_entry:
0050     # Entry point for dynamically created TCS page expected to follow
0051     # its stack directly.
0052     lea -1(%rbx), %rax
0053 encl_entry_core:
0054     xchg    %rsp, %rax
0055     push    %rax
0056
0057     push    %rcx # push the address after EENTER
0058     push    %rbx # push the enclave base address
0059
0060     call    encl_body
0061
0062     pop %rbx # pop the enclave base address
0063
0064     /* Clear volatile GPRs, except RAX (EEXIT function). */
0065     xor     %rcx, %rcx
0066     xor     %rdx, %rdx
0067     xor     %rdi, %rdi
0068     xor     %rsi, %rsi
0069     xor     %r8, %r8
0070     xor     %r9, %r9
0071     xor     %r10, %r10
0072     xor     %r11, %r11
0073
0074     # Reset status flags.
0075     add     %rdx, %rdx # OF = SF = AF = CF = 0; ZF = PF = 1
0076
0077     # Prepare EEXIT target by popping the address of the instruction after
0078     # EENTER to RBX.
0079     pop %rbx
0080
0081     # Restore the caller stack.
0082     pop %rax
0083     mov %rax, %rsp
0084
0085     # EEXIT
0086     mov $4, %rax
0087     enclu
0088
0089     .section ".data", "aw"
0090
0091 encl_ssa_tcs1:
0092     .space 4096
0093 encl_ssa_tcs2:
0094     .space 4096
0095
0096     .balign 4096
0097     # Stack of TCS #1
0098     .space 4096
0099 encl_stack:
0100     .balign 4096
0101     # Stack of TCS #2
0102     .space 4096