0001
0002
0003
0004
0005
0006
0007 #include "ptrace.h"
0008 #include "tm.h"
0009 #include "ptrace-vsx.h"
0010
0011 int shm_id;
0012 int *cptr, *pptr;
0013
0014 unsigned long fp_load[VEC_MAX];
0015 unsigned long fp_load_new[VEC_MAX];
0016 unsigned long fp_store[VEC_MAX];
0017 unsigned long fp_load_ckpt[VEC_MAX];
0018 unsigned long fp_load_ckpt_new[VEC_MAX];
0019
0020 __attribute__((used)) void load_vsx(void)
0021 {
0022 loadvsx(fp_load, 0);
0023 }
0024
0025 __attribute__((used)) void load_vsx_new(void)
0026 {
0027 loadvsx(fp_load_new, 0);
0028 }
0029
0030 __attribute__((used)) void load_vsx_ckpt(void)
0031 {
0032 loadvsx(fp_load_ckpt, 0);
0033 }
0034
0035 __attribute__((used)) void wait_parent(void)
0036 {
0037 cptr[2] = 1;
0038 while (!cptr[1])
0039 asm volatile("" : : : "memory");
0040 }
0041
0042 void tm_spd_vsx(void)
0043 {
0044 unsigned long result, texasr;
0045 int ret;
0046
0047 cptr = (int *)shmat(shm_id, NULL, 0);
0048
0049 trans:
0050 cptr[2] = 0;
0051 asm __volatile__(
0052 "bl load_vsx_ckpt;"
0053
0054 "1: ;"
0055 "tbegin.;"
0056 "beq 2f;"
0057
0058 "bl load_vsx_new;"
0059 "tsuspend.;"
0060 "bl load_vsx;"
0061 "bl wait_parent;"
0062 "tresume.;"
0063
0064 "tend.;"
0065 "li 0, 0;"
0066 "ori %[res], 0, 0;"
0067 "b 3f;"
0068
0069 "2: ;"
0070 "li 0, 1;"
0071 "ori %[res], 0, 0;"
0072 "mfspr %[texasr], %[sprn_texasr];"
0073
0074 "3: ;"
0075 : [res] "=r" (result), [texasr] "=r" (texasr)
0076 : [sprn_texasr] "i" (SPRN_TEXASR)
0077 : "memory", "r0", "r3", "r4",
0078 "r7", "r8", "r9", "r10", "r11", "lr"
0079 );
0080
0081 if (result) {
0082 if (!cptr[0])
0083 goto trans;
0084 shmdt((void *)cptr);
0085
0086 storevsx(fp_store, 0);
0087 ret = compare_vsx_vmx(fp_store, fp_load_ckpt_new);
0088 if (ret)
0089 exit(1);
0090 exit(0);
0091 }
0092 shmdt((void *)cptr);
0093 exit(1);
0094 }
0095
0096 int trace_tm_spd_vsx(pid_t child)
0097 {
0098 unsigned long vsx[VSX_MAX];
0099 unsigned long vmx[VMX_MAX + 2][2];
0100
0101 FAIL_IF(start_trace(child));
0102 FAIL_IF(show_vsx(child, vsx));
0103 FAIL_IF(validate_vsx(vsx, fp_load));
0104 FAIL_IF(show_vmx(child, vmx));
0105 FAIL_IF(validate_vmx(vmx, fp_load));
0106 FAIL_IF(show_vsx_ckpt(child, vsx));
0107 FAIL_IF(validate_vsx(vsx, fp_load_ckpt));
0108 FAIL_IF(show_vmx_ckpt(child, vmx));
0109 FAIL_IF(validate_vmx(vmx, fp_load_ckpt));
0110
0111 memset(vsx, 0, sizeof(vsx));
0112 memset(vmx, 0, sizeof(vmx));
0113
0114 load_vsx_vmx(fp_load_ckpt_new, vsx, vmx);
0115
0116 FAIL_IF(write_vsx_ckpt(child, vsx));
0117 FAIL_IF(write_vmx_ckpt(child, vmx));
0118
0119 pptr[0] = 1;
0120 pptr[1] = 1;
0121 FAIL_IF(stop_trace(child));
0122
0123 return TEST_PASS;
0124 }
0125
0126 int ptrace_tm_spd_vsx(void)
0127 {
0128 pid_t pid;
0129 int ret, status, i;
0130
0131 SKIP_IF(!have_htm());
0132 SKIP_IF(htm_is_synthetic());
0133 shm_id = shmget(IPC_PRIVATE, sizeof(int) * 3, 0777|IPC_CREAT);
0134
0135 for (i = 0; i < 128; i++) {
0136 fp_load[i] = 1 + rand();
0137 fp_load_new[i] = 1 + 2 * rand();
0138 fp_load_ckpt[i] = 1 + 3 * rand();
0139 fp_load_ckpt_new[i] = 1 + 4 * rand();
0140 }
0141
0142 pid = fork();
0143 if (pid < 0) {
0144 perror("fork() failed");
0145 return TEST_FAIL;
0146 }
0147
0148 if (pid == 0)
0149 tm_spd_vsx();
0150
0151 if (pid) {
0152 pptr = (int *)shmat(shm_id, NULL, 0);
0153 while (!pptr[2])
0154 asm volatile("" : : : "memory");
0155
0156 ret = trace_tm_spd_vsx(pid);
0157 if (ret) {
0158 kill(pid, SIGKILL);
0159 shmdt((void *)pptr);
0160 shmctl(shm_id, IPC_RMID, NULL);
0161 return TEST_FAIL;
0162 }
0163
0164 shmdt((void *)pptr);
0165 ret = wait(&status);
0166 shmctl(shm_id, IPC_RMID, NULL);
0167 if (ret != pid) {
0168 printf("Child's exit status not captured\n");
0169 return TEST_FAIL;
0170 }
0171
0172 return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
0173 TEST_PASS;
0174 }
0175 return TEST_PASS;
0176 }
0177
0178 int main(int argc, char *argv[])
0179 {
0180 return test_harness(ptrace_tm_spd_vsx, "ptrace_tm_spd_vsx");
0181 }