nx-gzip/include/nxu.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Hardware interface of the NX-GZIP compression accelerator
0004  *
0005  * Copyright (C) IBM Corporation, 2020
0006  *
0007  * Author: Bulent Abali <abali@us.ibm.com>
0008  *
0009  */
0010
0011 #ifndef _NXU_H
0012 #define _NXU_H
0013
0014 #include <stdint.h>
0015 #include <endian.h>
0016 #include "nx.h"
0017
0018 /* deflate */
0019 #define LLSZ   286
0020 #define DSZ    30
0021
0022 /* nx */
0023 #define DHTSZ  18
0024 #define DHT_MAXSZ 288
0025 #define MAX_DDE_COUNT 256
0026
0027 /* util */
0028 #ifdef NXDBG
0029 #define NXPRT(X)    X
0030 #else
0031 #define NXPRT(X)
0032 #endif
0033
0034 #ifdef NXTIMER
0035 #include <sys/platform/ppc.h>
0036 #define NX_CLK(X)   X
0037 #define nx_get_time()   __ppc_get_timebase()
0038 #define nx_get_freq()   __ppc_get_timebase_freq()
0039 #else
0040 #define NX_CLK(X)
0041 #define nx_get_time()  (-1)
0042 #define nx_get_freq()  (-1)
0043 #endif
0044
0045 #define NX_MAX_FAULTS  500
0046
0047 /*
0048  * Definitions of acronyms used here. See
0049  * P9 NX Gzip Accelerator User's Manual for details:
0050  * https://github.com/libnxz/power-gzip/blob/develop/doc/power_nx_gzip_um.pdf
0051  *
0052  * adler/crc: 32 bit checksums appended to stream tail
0053  * ce:       completion extension
0054  * cpb:      coprocessor parameter block (metadata)
0055  * crb:      coprocessor request block (command)
0056  * csb:      coprocessor status block (status)
0057  * dht:      dynamic huffman table
0058  * dde:      data descriptor element (address, length)
0059  * ddl:      list of ddes
0060  * dh/fh:    dynamic and fixed huffman types
0061  * fc:       coprocessor function code
0062  * histlen:  history/dictionary length
0063  * history:  sliding window of up to 32KB of data
0064  * lzcount:  Deflate LZ symbol counts
0065  * rembytecnt: remaining byte count
0066  * sfbt:     source final block type; last block's type during decomp
0067  * spbc:     source processed byte count
0068  * subc:     source unprocessed bit count
0069  * tebc:     target ending bit count; valid bits in the last byte
0070  * tpbc:     target processed byte count
0071  * vas:      virtual accelerator switch; the user mode interface
0072  */
0073
0074 union nx_qw_t {
0075     uint32_t word[4];
0076     uint64_t dword[2];
0077 } __aligned(16);
0078
0079 /*
0080  * Note: NX registers with fewer than 32 bits are declared by
0081  * convention as uint32_t variables in unions. If *_offset and *_mask
0082  * are defined for a variable, then use get_ put_ macros to
0083  * conveniently access the register fields for endian conversions.
0084  */
0085
0086 struct nx_dde_t {
0087     /* Data Descriptor Element, Section 6.4 */
0088     union {
0089         uint32_t dde_count;
0090         /* When dde_count == 0 ddead is a pointer to a data buffer;
0091          * ddebc is the buffer length bytes.
0092          * When dde_count > 0 dde is an indirect dde; ddead is a
0093          * pointer to a contiguous list of direct ddes; ddebc is the
0094          * total length of all data pointed to by the list of direct
0095          * ddes. Note that only one level of indirection is permitted.
0096          * See Section 6.4 of the user manual for additional details.
0097          */
0098     };
0099     uint32_t ddebc; /* dde byte count */
0100     uint64_t ddead; /* dde address */
0101 } __aligned(16);
0102
0103 struct nx_csb_t {
0104     /* Coprocessor Status Block, Section 6.6  */
0105     union {
0106         uint32_t csb_v;
0107         /* Valid bit. v must be set to 0 by the program
0108          * before submitting the coprocessor command.
0109          * Software can poll for the v bit
0110          */
0111
0112         uint32_t csb_f;
0113         /* 16B CSB size. Written to 0 by DMA when it writes the CPB */
0114
0115         uint32_t csb_cs;
0116         /* cs completion sequence; unused */
0117
0118         uint32_t csb_cc;
0119         /* cc completion code; cc != 0 exception occurred */
0120
0121         uint32_t csb_ce;
0122         /* ce completion extension */
0123
0124     };
0125     uint32_t tpbc;
0126     /* target processed byte count TPBC */
0127
0128     uint64_t fsaddr;
0129     /* Section 6.12.1 CSB NonZero error summary.  FSA Failing storage
0130      * address.  Address where error occurred. When available, written
0131      * to A field of CSB
0132      */
0133 } __aligned(16);
0134
0135 struct nx_ccb_t {
0136     /* Coprocessor Completion Block, Section 6.7 */
0137
0138     uint32_t reserved[3];
0139     union {
0140         /* When crb.c==0 (no ccb defined) it is reserved;
0141          * When crb.c==1 (ccb defined) it is cm
0142          */
0143
0144         uint32_t ccb_cm;
0145         /* Signal interrupt of crb.c==1 and cm==1 */
0146
0147         uint32_t word;
0148         /* generic access to the 32bit word */
0149     };
0150 } __aligned(16);
0151
0152 struct vas_stamped_crb_t {
0153     /*
0154      * CRB operand of the paste coprocessor instruction is stamped
0155      * in quadword 4 with the information shown here as its written
0156      * in to the receive FIFO of the coprocessor
0157      */
0158
0159     union {
0160         uint32_t vas_buf_num;
0161         /* Verification only vas buffer number which correlates to
0162          * the low order bits of the atag in the paste command
0163          */
0164
0165         uint32_t send_wc_id;
0166         /* Pointer to Send Window Context that provides for NX address
0167          * translation information, such as MSR and LPCR bits, job
0168          * completion interrupt RA, PSWID, and job utilization counter.
0169          */
0170
0171     };
0172     union {
0173         uint32_t recv_wc_id;
0174         /* Pointer to Receive Window Context. NX uses this to return
0175          * credits to a Receive FIFO as entries are dequeued.
0176          */
0177
0178     };
0179     uint32_t reserved2;
0180     union {
0181         uint32_t vas_invalid;
0182         /* Invalid bit. If this bit is 1 the CRB is discarded by
0183          * NX upon fetching from the receive FIFO. If this bit is 0
0184          * the CRB is processed normally. The bit is stamped to 0
0185          * by VAS and may be written to 1 by hypervisor while
0186          * the CRB is in the receive FIFO (in memory).
0187          */
0188
0189     };
0190 };
0191
0192 struct nx_stamped_fault_crb_t {
0193     /*
0194      * A CRB that has a translation fault is stamped by NX in quadword 4
0195      * and pasted to the Fault Send Window in VAS.
0196      */
0197     uint64_t fsa;
0198     union {
0199         uint32_t nxsf_t;
0200         uint32_t nxsf_fs;
0201     };
0202     uint32_t pswid;
0203 };
0204
0205 union stamped_crb_t {
0206     struct vas_stamped_crb_t      vas;
0207     struct nx_stamped_fault_crb_t nx;
0208 };
0209
0210 struct nx_gzip_cpb_t {
0211     /*
0212      * Coprocessor Parameter Block In/Out are used to pass metadata
0213      * to/from accelerator.  Tables 6.5 and 6.6 of the user manual.
0214      */
0215
0216     /* CPBInput */
0217
0218     struct {
0219         union {
0220         union nx_qw_t qw0;
0221             struct {
0222                 uint32_t in_adler;            /* bits 0:31  */
0223                 uint32_t in_crc;              /* bits 32:63 */
0224                 union {
0225                     uint32_t in_histlen;  /* bits 64:75 */
0226                     uint32_t in_subc;     /* bits 93:95 */
0227                 };
0228                 union {
0229                     /* bits 108:111 */
0230                     uint32_t in_sfbt;
0231                     /* bits 112:127 */
0232                     uint32_t in_rembytecnt;
0233                     /* bits 116:127 */
0234                     uint32_t in_dhtlen;
0235                 };
0236             };
0237         };
0238         union {
0239             union nx_qw_t  in_dht[DHTSZ];   /* qw[1:18]     */
0240             char in_dht_char[DHT_MAXSZ];    /* byte access  */
0241         };
0242         union nx_qw_t  reserved[5];     /* qw[19:23]    */
0243     };
0244
0245     /* CPBOutput */
0246
0247     volatile struct {
0248         union {
0249             union nx_qw_t qw24;
0250             struct {
0251                 uint32_t out_adler;    /* bits 0:31  qw[24] */
0252                 uint32_t out_crc;      /* bits 32:63 qw[24] */
0253                 union {
0254                     /* bits 77:79 qw[24] */
0255                     uint32_t out_tebc;
0256                     /* bits 80:95 qw[24] */
0257                     uint32_t out_subc;
0258                 };
0259                 union {
0260                     /* bits 108:111 qw[24] */
0261                     uint32_t out_sfbt;
0262                     /* bits 112:127 qw[24] */
0263                     uint32_t out_rembytecnt;
0264                     /* bits 116:127 qw[24] */
0265                     uint32_t out_dhtlen;
0266                 };
0267             };
0268         };
0269         union {
0270             union nx_qw_t  qw25[79];        /* qw[25:103] */
0271             /* qw[25] compress no lzcounts or wrap */
0272             uint32_t out_spbc_comp_wrap;
0273             uint32_t out_spbc_wrap;         /* qw[25] wrap */
0274             /* qw[25] compress no lzcounts */
0275             uint32_t out_spbc_comp;
0276              /* 286 LL and 30 D symbol counts */
0277             uint32_t out_lzcount[LLSZ+DSZ];
0278             struct {
0279                 union nx_qw_t  out_dht[DHTSZ];  /* qw[25:42] */
0280                 /* qw[43] decompress */
0281                 uint32_t out_spbc_decomp;
0282             };
0283         };
0284         /* qw[104] compress with lzcounts */
0285         uint32_t out_spbc_comp_with_count;
0286     };
0287 } __aligned(128);
0288
0289 struct nx_gzip_crb_t {
0290     union {                   /* byte[0:3]   */
0291         uint32_t gzip_fc;     /* bits[24-31] */
0292     };
0293     uint32_t reserved1;       /* byte[4:7]   */
0294     union {
0295         uint64_t csb_address; /* byte[8:15]  */
0296         struct {
0297             uint32_t reserved2;
0298             union {
0299                 uint32_t crb_c;
0300                 /* c==0 no ccb defined */
0301
0302                 uint32_t crb_at;
0303                 /* at==0 address type is ignored;
0304                  * all addrs effective assumed.
0305                  */
0306
0307             };
0308         };
0309     };
0310     struct nx_dde_t source_dde;           /* byte[16:31] */
0311     struct nx_dde_t target_dde;           /* byte[32:47] */
0312     volatile struct nx_ccb_t ccb;         /* byte[48:63] */
0313     volatile union {
0314         /* byte[64:239] shift csb by 128 bytes out of the crb; csb was
0315          * in crb earlier; JReilly says csb written with partial inject
0316          */
0317         union nx_qw_t reserved64[11];
0318         union stamped_crb_t stamp;       /* byte[64:79] */
0319     };
0320     volatile struct nx_csb_t csb;
0321 } __aligned(128);
0322
0323 struct nx_gzip_crb_cpb_t {
0324     struct nx_gzip_crb_t crb;
0325     struct nx_gzip_cpb_t cpb;
0326 } __aligned(2048);
0327
0328
0329 /*
0330  * NX hardware convention has the msb bit on the left numbered 0.
0331  * The defines below has *_offset defined as the right most bit
0332  * position of a field.  x of size_mask(x) is the field width in bits.
0333  */
0334
0335 #define size_mask(x)          ((1U<<(x))-1)
0336
0337 /*
0338  * Offsets and Widths within the containing 32 bits of the various NX
0339  * gzip hardware registers.  Use the getnn/putnn macros to access
0340  * these regs
0341  */
0342
0343 #define dde_count_mask        size_mask(8)
0344 #define dde_count_offset      23
0345
0346 /* CSB */
0347
0348 #define csb_v_mask            size_mask(1)
0349 #define csb_v_offset          0
0350 #define csb_f_mask            size_mask(1)
0351 #define csb_f_offset          6
0352 #define csb_cs_mask           size_mask(8)
0353 #define csb_cs_offset         15
0354 #define csb_cc_mask           size_mask(8)
0355 #define csb_cc_offset         23
0356 #define csb_ce_mask           size_mask(8)
0357 #define csb_ce_offset         31
0358
0359 /* CCB */
0360
0361 #define ccb_cm_mask           size_mask(3)
0362 #define ccb_cm_offset         31
0363
0364 /* VAS stamped CRB fields */
0365
0366 #define vas_buf_num_mask      size_mask(6)
0367 #define vas_buf_num_offset    5
0368 #define send_wc_id_mask       size_mask(16)
0369 #define send_wc_id_offset     31
0370 #define recv_wc_id_mask       size_mask(16)
0371 #define recv_wc_id_offset     31
0372 #define vas_invalid_mask      size_mask(1)
0373 #define vas_invalid_offset    31
0374
0375 /* NX stamped fault CRB fields */
0376
0377 #define nxsf_t_mask           size_mask(1)
0378 #define nxsf_t_offset         23
0379 #define nxsf_fs_mask          size_mask(8)
0380 #define nxsf_fs_offset        31
0381
0382 /* CPB input */
0383
0384 #define in_histlen_mask       size_mask(12)
0385 #define in_histlen_offset     11
0386 #define in_dhtlen_mask        size_mask(12)
0387 #define in_dhtlen_offset      31
0388 #define in_subc_mask          size_mask(3)
0389 #define in_subc_offset        31
0390 #define in_sfbt_mask          size_mask(4)
0391 #define in_sfbt_offset        15
0392 #define in_rembytecnt_mask    size_mask(16)
0393 #define in_rembytecnt_offset  31
0394
0395 /* CPB output */
0396
0397 #define out_tebc_mask         size_mask(3)
0398 #define out_tebc_offset       15
0399 #define out_subc_mask         size_mask(16)
0400 #define out_subc_offset       31
0401 #define out_sfbt_mask         size_mask(4)
0402 #define out_sfbt_offset       15
0403 #define out_rembytecnt_mask   size_mask(16)
0404 #define out_rembytecnt_offset 31
0405 #define out_dhtlen_mask       size_mask(12)
0406 #define out_dhtlen_offset     31
0407
0408 /* CRB */
0409
0410 #define gzip_fc_mask          size_mask(8)
0411 #define gzip_fc_offset        31
0412 #define crb_c_mask            size_mask(1)
0413 #define crb_c_offset          28
0414 #define crb_at_mask           size_mask(1)
0415 #define crb_at_offset         30
0416 #define csb_address_mask      ~(15UL) /* mask off bottom 4b */
0417
0418 /*
0419  * Access macros for the registers.  Do not access registers directly
0420  * because of the endian conversion.  P9 processor may run either as
0421  * Little or Big endian. However the NX coprocessor regs are always
0422  * big endian.
0423  * Use the 32 and 64b macros to access respective
0424  * register sizes.
0425  * Use nn forms for the register fields shorter than 32 bits.
0426  */
0427
0428 #define getnn(ST, REG)      ((be32toh(ST.REG) >> (31-REG##_offset)) \
0429                  & REG##_mask)
0430 #define getpnn(ST, REG)     ((be32toh((ST)->REG) >> (31-REG##_offset)) \
0431                  & REG##_mask)
0432 #define get32(ST, REG)      (be32toh(ST.REG))
0433 #define getp32(ST, REG)     (be32toh((ST)->REG))
0434 #define get64(ST, REG)      (be64toh(ST.REG))
0435 #define getp64(ST, REG)     (be64toh((ST)->REG))
0436
0437 #define unget32(ST, REG)    (get32(ST, REG) & ~((REG##_mask) \
0438                 << (31-REG##_offset)))
0439 /* get 32bits less the REG field */
0440
0441 #define ungetp32(ST, REG)   (getp32(ST, REG) & ~((REG##_mask) \
0442                 << (31-REG##_offset)))
0443 /* get 32bits less the REG field */
0444
0445 #define clear_regs(ST)      memset((void *)(&(ST)), 0, sizeof(ST))
0446 #define clear_dde(ST)       do { ST.dde_count = ST.ddebc = 0; ST.ddead = 0; \
0447                 } while (0)
0448 #define clearp_dde(ST)      do { (ST)->dde_count = (ST)->ddebc = 0; \
0449                  (ST)->ddead = 0; \
0450                 } while (0)
0451 #define clear_struct(ST)    memset((void *)(&(ST)), 0, sizeof(ST))
0452 #define putnn(ST, REG, X)   (ST.REG = htobe32(unget32(ST, REG) | (((X) \
0453                  & REG##_mask) << (31-REG##_offset))))
0454 #define putpnn(ST, REG, X)  ((ST)->REG = htobe32(ungetp32(ST, REG) \
0455                 | (((X) & REG##_mask) << (31-REG##_offset))))
0456
0457 #define put32(ST, REG, X)   (ST.REG = htobe32(X))
0458 #define putp32(ST, REG, X)  ((ST)->REG = htobe32(X))
0459 #define put64(ST, REG, X)   (ST.REG = htobe64(X))
0460 #define putp64(ST, REG, X)  ((ST)->REG = htobe64(X))
0461
0462 /*
0463  * Completion extension ce(0) ce(1) ce(2).  Bits ce(3-7)
0464  * unused.  Section 6.6 Figure 6.7.
0465  */
0466
0467 #define get_csb_ce(ST) ((uint32_t)getnn(ST, csb_ce))
0468 #define get_csb_ce_ms3b(ST) (get_csb_ce(ST) >> 5)
0469 #define put_csb_ce_ms3b(ST, X) putnn(ST, csb_ce, ((uint32_t)(X) << 5))
0470
0471 #define CSB_CE_PARTIAL         0x4
0472 #define CSB_CE_TERMINATE       0x2
0473 #define CSB_CE_TPBC_VALID      0x1
0474
0475 #define csb_ce_termination(X)         (!!((X) & CSB_CE_TERMINATE))
0476 /* termination, output buffers may be modified, SPBC/TPBC invalid Fig.6-7 */
0477
0478 #define csb_ce_check_completion(X)    (!csb_ce_termination(X))
0479 /* if not terminated then check full or partial completion */
0480
0481 #define csb_ce_partial_completion(X)  (!!((X) & CSB_CE_PARTIAL))
0482 #define csb_ce_full_completion(X)     (!csb_ce_partial_completion(X))
0483 #define csb_ce_tpbc_valid(X)          (!!((X) & CSB_CE_TPBC_VALID))
0484 /* TPBC indicates successfully stored data count */
0485
0486 #define csb_ce_default_err(X)         csb_ce_termination(X)
0487 /* most error CEs have CE(0)=0 and CE(1)=1 */
0488
0489 #define csb_ce_cc3_partial(X)         csb_ce_partial_completion(X)
0490 /* some CC=3 are partially completed, Table 6-8 */
0491
0492 #define csb_ce_cc64(X)                ((X)&(CSB_CE_PARTIAL \
0493                     | CSB_CE_TERMINATE) == 0)
0494 /* Compression: when TPBC>SPBC then CC=64 Table 6-8; target didn't
0495  * compress smaller than source.
0496  */
0497
0498 /* Decompress SFBT combinations Tables 5-3, 6-4, 6-6 */
0499
0500 #define SFBT_BFINAL 0x1
0501 #define SFBT_LIT    0x4
0502 #define SFBT_FHT    0x5
0503 #define SFBT_DHT    0x6
0504 #define SFBT_HDR    0x7
0505
0506 /*
0507  * NX gzip function codes. Table 6.2.
0508  * Bits 0:4 are the FC. Bit 5 is used by the DMA controller to
0509  * select one of the two Byte Count Limits.
0510  */
0511
0512 #define GZIP_FC_LIMIT_MASK                               0x01
0513 #define GZIP_FC_COMPRESS_FHT                             0x00
0514 #define GZIP_FC_COMPRESS_DHT                             0x02
0515 #define GZIP_FC_COMPRESS_FHT_COUNT                       0x04
0516 #define GZIP_FC_COMPRESS_DHT_COUNT                       0x06
0517 #define GZIP_FC_COMPRESS_RESUME_FHT                      0x08
0518 #define GZIP_FC_COMPRESS_RESUME_DHT                      0x0a
0519 #define GZIP_FC_COMPRESS_RESUME_FHT_COUNT                0x0c
0520 #define GZIP_FC_COMPRESS_RESUME_DHT_COUNT                0x0e
0521 #define GZIP_FC_DECOMPRESS                               0x10
0522 #define GZIP_FC_DECOMPRESS_SINGLE_BLK_N_SUSPEND          0x12
0523 #define GZIP_FC_DECOMPRESS_RESUME                        0x14
0524 #define GZIP_FC_DECOMPRESS_RESUME_SINGLE_BLK_N_SUSPEND   0x16
0525 #define GZIP_FC_WRAP                                     0x1e
0526
0527 #define fc_is_compress(fc)  (((fc) & 0x10) == 0)
0528 #define fc_has_count(fc)    (fc_is_compress(fc) && (((fc) & 0x4) != 0))
0529
0530 /* CSB.CC Error codes */
0531
0532 #define ERR_NX_OK             0
0533 #define ERR_NX_ALIGNMENT      1
0534 #define ERR_NX_OPOVERLAP      2
0535 #define ERR_NX_DATA_LENGTH    3
0536 #define ERR_NX_TRANSLATION    5
0537 #define ERR_NX_PROTECTION     6
0538 #define ERR_NX_EXTERNAL_UE7   7
0539 #define ERR_NX_INVALID_OP     8
0540 #define ERR_NX_PRIVILEGE      9
0541 #define ERR_NX_INTERNAL_UE   10
0542 #define ERR_NX_EXTERN_UE_WR  12
0543 #define ERR_NX_TARGET_SPACE  13
0544 #define ERR_NX_EXCESSIVE_DDE 14
0545 #define ERR_NX_TRANSL_WR     15
0546 #define ERR_NX_PROTECT_WR    16
0547 #define ERR_NX_SUBFUNCTION   17
0548 #define ERR_NX_FUNC_ABORT    18
0549 #define ERR_NX_BYTE_MAX      19
0550 #define ERR_NX_CORRUPT_CRB   20
0551 #define ERR_NX_INVALID_CRB   21
0552 #define ERR_NX_INVALID_DDE   30
0553 #define ERR_NX_SEGMENTED_DDL 31
0554 #define ERR_NX_DDE_OVERFLOW  33
0555 #define ERR_NX_TPBC_GT_SPBC  64
0556 #define ERR_NX_MISSING_CODE  66
0557 #define ERR_NX_INVALID_DIST  67
0558 #define ERR_NX_INVALID_DHT   68
0559 #define ERR_NX_EXTERNAL_UE90 90
0560 #define ERR_NX_WDOG_TIMER   224
0561 #define ERR_NX_AT_FAULT     250
0562 #define ERR_NX_INTR_SERVER  252
0563 #define ERR_NX_UE253        253
0564 #define ERR_NX_NO_HW        254
0565 #define ERR_NX_HUNG_OP      255
0566 #define ERR_NX_END          256
0567
0568 /* initial values for non-resume operations */
0569 #define INIT_CRC   0  /* crc32(0L, Z_NULL, 0) */
0570 #define INIT_ADLER 1  /* adler32(0L, Z_NULL, 0)  adler is initialized to 1 */
0571
0572 /* prototypes */
0573 int nxu_submit_job(struct nx_gzip_crb_cpb_t *c, void *handle);
0574
0575 extern void nxu_sigsegv_handler(int sig, siginfo_t *info, void *ctx);
0576 extern int nxu_touch_pages(void *buf, long buf_len, long page_len, int wr);
0577
0578 /* caller supplies a print buffer 4*sizeof(crb) */
0579
0580 char *nx_crb_str(struct nx_gzip_crb_t *crb, char *prbuf);
0581 char *nx_cpb_str(struct nx_gzip_cpb_t *cpb, char *prbuf);
0582 char *nx_prt_hex(void *cp, int sz, char *prbuf);
0583 char *nx_lzcount_str(struct nx_gzip_cpb_t *cpb, char *prbuf);
0584 char *nx_strerror(int e);
0585
0586 #ifdef NX_SIM
0587 #include <stdio.h>
0588 int nx_sim_init(void *ctx);
0589 int nx_sim_end(void *ctx);
0590 int nxu_run_sim_job(struct nx_gzip_crb_cpb_t *c, void *ctx);
0591 #endif /* NX_SIM */
0592
0593 /* Deflate stream manipulation */
0594
0595 #define set_final_bit(x)    (x |= (unsigned char)1)
0596 #define clr_final_bit(x)    (x &= ~(unsigned char)1)
0597
0598 #define append_empty_fh_blk(p, b) do { *(p) = (2 | (1&(b))); *((p)+1) = 0; \
0599                     } while (0)
0600 /* append 10 bits 0000001b 00...... ;
0601  * assumes appending starts on a byte boundary; b is the final bit.
0602  */
0603
0604
0605 #ifdef NX_842
0606
0607 /* 842 Engine */
0608
0609 struct nx_eft_crb_t {
0610     union {                   /* byte[0:3]   */
0611         uint32_t eft_fc;      /* bits[29-31] */
0612     };
0613     uint32_t reserved1;       /* byte[4:7]   */
0614     union {
0615         uint64_t csb_address; /* byte[8:15]  */
0616         struct {
0617             uint32_t reserved2;
0618             union {
0619                 uint32_t crb_c;
0620                 /* c==0 no ccb defined */
0621
0622                 uint32_t crb_at;
0623                 /* at==0 address type is ignored;
0624                  * all addrs effective assumed.
0625                  */
0626
0627             };
0628         };
0629     };
0630     struct nx_dde_t source_dde;           /* byte[16:31] */
0631     struct nx_dde_t target_dde;           /* byte[32:47] */
0632     struct nx_ccb_t ccb;                  /* byte[48:63] */
0633     union {
0634         union nx_qw_t reserved64[3];     /* byte[64:96] */
0635     };
0636     struct nx_csb_t csb;
0637 } __aligned(128);
0638
0639 /* 842 CRB */
0640
0641 #define EFT_FC_MASK                 size_mask(3)
0642 #define EFT_FC_OFFSET               31
0643 #define EFT_FC_COMPRESS             0x0
0644 #define EFT_FC_COMPRESS_WITH_CRC    0x1
0645 #define EFT_FC_DECOMPRESS           0x2
0646 #define EFT_FC_DECOMPRESS_WITH_CRC  0x3
0647 #define EFT_FC_BLK_DATA_MOVE        0x4
0648 #endif /* NX_842 */
0649
0650 #endif /* _NXU_H */