powerpc/include/reg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2014, Michael Ellerman, IBM Corp.
0004  */
0005
0006 #ifndef _SELFTESTS_POWERPC_REG_H
0007 #define _SELFTESTS_POWERPC_REG_H
0008
0009 #define __stringify_1(x)        #x
0010 #define __stringify(x)          __stringify_1(x)
0011
0012 #define mfspr(rn)   ({unsigned long rval; \
0013              asm volatile("mfspr %0," _str(rn) \
0014                     : "=r" (rval)); rval; })
0015 #define mtspr(rn, v)    asm volatile("mtspr " _str(rn) ",%0" : \
0016                     : "r" ((unsigned long)(v)) \
0017                     : "memory")
0018
0019 #define mb()        asm volatile("sync" : : : "memory");
0020 #define barrier()   asm volatile("" : : : "memory");
0021
0022 #define SPRN_MMCR2     769
0023 #define SPRN_MMCRA     770
0024 #define SPRN_MMCR0     779
0025 #define   MMCR0_PMAO   0x00000080
0026 #define   MMCR0_PMAE   0x04000000
0027 #define   MMCR0_FC     0x80000000
0028 #define SPRN_EBBHR     804
0029 #define SPRN_EBBRR     805
0030 #define SPRN_BESCR     806     /* Branch event status & control register */
0031 #define SPRN_BESCRS    800     /* Branch event status & control set (1 bits set to 1) */
0032 #define SPRN_BESCRSU   801     /* Branch event status & control set upper */
0033 #define SPRN_BESCRR    802     /* Branch event status & control REset (1 bits set to 0) */
0034 #define SPRN_BESCRRU   803     /* Branch event status & control REset upper */
0035
0036 #define BESCR_PMEO     0x1     /* PMU Event-based exception Occurred */
0037 #define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
0038
0039 #define SPRN_PMC1      771
0040 #define SPRN_PMC2      772
0041 #define SPRN_PMC3      773
0042 #define SPRN_PMC4      774
0043 #define SPRN_PMC5      775
0044 #define SPRN_PMC6      776
0045
0046 #define SPRN_SIAR      780
0047 #define SPRN_SDAR      781
0048 #define SPRN_SIER      768
0049
0050 #define SPRN_TEXASR     0x82    /* Transaction Exception and Status Register */
0051 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr    */
0052 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
0053 #define SPRN_TAR        0x32f   /* Target Address Register */
0054
0055 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)
0056 #define SPRN_PVR    0x11F
0057
0058 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
0059 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
0060 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
0061
0062 #define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */
0063 #define SPRN_DSCR      0x03 /* Data Stream Control Register */
0064 #define SPRN_PPR       896  /* Program Priority Register */
0065 #define SPRN_AMR       13   /* Authority Mask Register - problem state */
0066
0067 #define set_amr(v)  asm volatile("isync;" \
0068                      "mtspr " __stringify(SPRN_AMR) ",%0;" \
0069                      "isync" : \
0070                     : "r" ((unsigned long)(v)) \
0071                     : "memory")
0072
0073 /* TEXASR register bits */
0074 #define TEXASR_FC   0xFE00000000000000
0075 #define TEXASR_FP   0x0100000000000000
0076 #define TEXASR_DA   0x0080000000000000
0077 #define TEXASR_NO   0x0040000000000000
0078 #define TEXASR_FO   0x0020000000000000
0079 #define TEXASR_SIC  0x0010000000000000
0080 #define TEXASR_NTC  0x0008000000000000
0081 #define TEXASR_TC   0x0004000000000000
0082 #define TEXASR_TIC  0x0002000000000000
0083 #define TEXASR_IC   0x0001000000000000
0084 #define TEXASR_IFC  0x0000800000000000
0085 #define TEXASR_ABT  0x0000000100000000
0086 #define TEXASR_SPD  0x0000000080000000
0087 #define TEXASR_HV   0x0000000020000000
0088 #define TEXASR_PR   0x0000000010000000
0089 #define TEXASR_FS   0x0000000008000000
0090 #define TEXASR_TE   0x0000000004000000
0091 #define TEXASR_ROT  0x0000000002000000
0092
0093 /* MSR register bits */
0094 #define MSR_HV      (1ul << 60) /* Hypervisor state */
0095 #define MSR_TS_S_LG     33              /* Trans Mem state: Suspended */
0096 #define MSR_TS_T_LG 34              /* Trans Mem state: Active */
0097
0098 #define __MASK(X)       (1UL<<(X))
0099
0100 /* macro to check TM MSR bits */
0101 #define MSR_TS_S        __MASK(MSR_TS_S_LG)   /* Transaction Suspended */
0102 #define MSR_TS_T    __MASK(MSR_TS_T_LG)   /* Transaction Transactional */
0103
0104 /* Vector Instructions */
0105 #define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) |  \
0106                  ((rb) << 11) | (((xs) >> 5)))
0107 #define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
0108 #define LXVD2X(xs, ra, rb)  .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
0109
0110 #define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \
0111         "li 14, %[" #_asm_symbol_name_immed "];" \
0112         "li 15, %[" #_asm_symbol_name_immed "];" \
0113         "li 16, %[" #_asm_symbol_name_immed "];" \
0114         "li 17, %[" #_asm_symbol_name_immed "];" \
0115         "li 18, %[" #_asm_symbol_name_immed "];" \
0116         "li 19, %[" #_asm_symbol_name_immed "];" \
0117         "li 20, %[" #_asm_symbol_name_immed "];" \
0118         "li 21, %[" #_asm_symbol_name_immed "];" \
0119         "li 22, %[" #_asm_symbol_name_immed "];" \
0120         "li 23, %[" #_asm_symbol_name_immed "];" \
0121         "li 24, %[" #_asm_symbol_name_immed "];" \
0122         "li 25, %[" #_asm_symbol_name_immed "];" \
0123         "li 26, %[" #_asm_symbol_name_immed "];" \
0124         "li 27, %[" #_asm_symbol_name_immed "];" \
0125         "li 28, %[" #_asm_symbol_name_immed "];" \
0126         "li 29, %[" #_asm_symbol_name_immed "];" \
0127         "li 30, %[" #_asm_symbol_name_immed "];" \
0128         "li 31, %[" #_asm_symbol_name_immed "];"
0129
0130 #define ASM_LOAD_FPR(_asm_symbol_name_addr) \
0131         "lfd 0, 0(%[" #_asm_symbol_name_addr "]);" \
0132         "lfd 1, 0(%[" #_asm_symbol_name_addr "]);" \
0133         "lfd 2, 0(%[" #_asm_symbol_name_addr "]);" \
0134         "lfd 3, 0(%[" #_asm_symbol_name_addr "]);" \
0135         "lfd 4, 0(%[" #_asm_symbol_name_addr "]);" \
0136         "lfd 5, 0(%[" #_asm_symbol_name_addr "]);" \
0137         "lfd 6, 0(%[" #_asm_symbol_name_addr "]);" \
0138         "lfd 7, 0(%[" #_asm_symbol_name_addr "]);" \
0139         "lfd 8, 0(%[" #_asm_symbol_name_addr "]);" \
0140         "lfd 9, 0(%[" #_asm_symbol_name_addr "]);" \
0141         "lfd 10, 0(%[" #_asm_symbol_name_addr "]);" \
0142         "lfd 11, 0(%[" #_asm_symbol_name_addr "]);" \
0143         "lfd 12, 0(%[" #_asm_symbol_name_addr "]);" \
0144         "lfd 13, 0(%[" #_asm_symbol_name_addr "]);" \
0145         "lfd 14, 0(%[" #_asm_symbol_name_addr "]);" \
0146         "lfd 15, 0(%[" #_asm_symbol_name_addr "]);" \
0147         "lfd 16, 0(%[" #_asm_symbol_name_addr "]);" \
0148         "lfd 17, 0(%[" #_asm_symbol_name_addr "]);" \
0149         "lfd 18, 0(%[" #_asm_symbol_name_addr "]);" \
0150         "lfd 19, 0(%[" #_asm_symbol_name_addr "]);" \
0151         "lfd 20, 0(%[" #_asm_symbol_name_addr "]);" \
0152         "lfd 21, 0(%[" #_asm_symbol_name_addr "]);" \
0153         "lfd 22, 0(%[" #_asm_symbol_name_addr "]);" \
0154         "lfd 23, 0(%[" #_asm_symbol_name_addr "]);" \
0155         "lfd 24, 0(%[" #_asm_symbol_name_addr "]);" \
0156         "lfd 25, 0(%[" #_asm_symbol_name_addr "]);" \
0157         "lfd 26, 0(%[" #_asm_symbol_name_addr "]);" \
0158         "lfd 27, 0(%[" #_asm_symbol_name_addr "]);" \
0159         "lfd 28, 0(%[" #_asm_symbol_name_addr "]);" \
0160         "lfd 29, 0(%[" #_asm_symbol_name_addr "]);" \
0161         "lfd 30, 0(%[" #_asm_symbol_name_addr "]);" \
0162         "lfd 31, 0(%[" #_asm_symbol_name_addr "]);"
0163
0164 #ifndef __ASSEMBLER__
0165 void store_gpr(unsigned long *addr);
0166 void load_gpr(unsigned long *addr);
0167 void store_fpr(double *addr);
0168 #endif /* end of __ASSEMBLER__ */
0169
0170 #endif /* _SELFTESTS_POWERPC_REG_H */