lib/x86_64/vmx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * tools/testing/selftests/kvm/lib/x86_64/vmx.c
0004  *
0005  * Copyright (C) 2018, Google LLC.
0006  */
0007
0008 #include <asm/msr-index.h>
0009
0010 #include "test_util.h"
0011 #include "kvm_util.h"
0012 #include "processor.h"
0013 #include "vmx.h"
0014
0015 #define PAGE_SHIFT_4K  12
0016
0017 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000
0018
0019 bool enable_evmcs;
0020
0021 struct hv_enlightened_vmcs *current_evmcs;
0022 struct hv_vp_assist_page *current_vp_assist;
0023
0024 struct eptPageTableEntry {
0025     uint64_t readable:1;
0026     uint64_t writable:1;
0027     uint64_t executable:1;
0028     uint64_t memory_type:3;
0029     uint64_t ignore_pat:1;
0030     uint64_t page_size:1;
0031     uint64_t accessed:1;
0032     uint64_t dirty:1;
0033     uint64_t ignored_11_10:2;
0034     uint64_t address:40;
0035     uint64_t ignored_62_52:11;
0036     uint64_t suppress_ve:1;
0037 };
0038
0039 struct eptPageTablePointer {
0040     uint64_t memory_type:3;
0041     uint64_t page_walk_length:3;
0042     uint64_t ad_enabled:1;
0043     uint64_t reserved_11_07:5;
0044     uint64_t address:40;
0045     uint64_t reserved_63_52:12;
0046 };
0047 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu)
0048 {
0049     uint16_t evmcs_ver;
0050
0051     vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS,
0052             (unsigned long)&evmcs_ver);
0053
0054     /* KVM should return supported EVMCS version range */
0055     TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) &&
0056             (evmcs_ver & 0xff) > 0,
0057             "Incorrect EVMCS version range: %x:%x\n",
0058             evmcs_ver & 0xff, evmcs_ver >> 8);
0059
0060     return evmcs_ver;
0061 }
0062
0063 /* Allocate memory regions for nested VMX tests.
0064  *
0065  * Input Args:
0066  *   vm - The VM to allocate guest-virtual addresses in.
0067  *
0068  * Output Args:
0069  *   p_vmx_gva - The guest virtual address for the struct vmx_pages.
0070  *
0071  * Return:
0072  *   Pointer to structure with the addresses of the VMX areas.
0073  */
0074 struct vmx_pages *
0075 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva)
0076 {
0077     vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm);
0078     struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva);
0079
0080     /* Setup of a region of guest memory for the vmxon region. */
0081     vmx->vmxon = (void *)vm_vaddr_alloc_page(vm);
0082     vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon);
0083     vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon);
0084
0085     /* Setup of a region of guest memory for a vmcs. */
0086     vmx->vmcs = (void *)vm_vaddr_alloc_page(vm);
0087     vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs);
0088     vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs);
0089
0090     /* Setup of a region of guest memory for the MSR bitmap. */
0091     vmx->msr = (void *)vm_vaddr_alloc_page(vm);
0092     vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr);
0093     vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr);
0094     memset(vmx->msr_hva, 0, getpagesize());
0095
0096     /* Setup of a region of guest memory for the shadow VMCS. */
0097     vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm);
0098     vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs);
0099     vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs);
0100
0101     /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */
0102     vmx->vmread = (void *)vm_vaddr_alloc_page(vm);
0103     vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread);
0104     vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread);
0105     memset(vmx->vmread_hva, 0, getpagesize());
0106
0107     vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm);
0108     vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite);
0109     vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite);
0110     memset(vmx->vmwrite_hva, 0, getpagesize());
0111
0112     /* Setup of a region of guest memory for the VP Assist page. */
0113     vmx->vp_assist = (void *)vm_vaddr_alloc_page(vm);
0114     vmx->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)vmx->vp_assist);
0115     vmx->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vp_assist);
0116
0117     /* Setup of a region of guest memory for the enlightened VMCS. */
0118     vmx->enlightened_vmcs = (void *)vm_vaddr_alloc_page(vm);
0119     vmx->enlightened_vmcs_hva =
0120         addr_gva2hva(vm, (uintptr_t)vmx->enlightened_vmcs);
0121     vmx->enlightened_vmcs_gpa =
0122         addr_gva2gpa(vm, (uintptr_t)vmx->enlightened_vmcs);
0123
0124     *p_vmx_gva = vmx_gva;
0125     return vmx;
0126 }
0127
0128 bool prepare_for_vmx_operation(struct vmx_pages *vmx)
0129 {
0130     uint64_t feature_control;
0131     uint64_t required;
0132     unsigned long cr0;
0133     unsigned long cr4;
0134
0135     /*
0136      * Ensure bits in CR0 and CR4 are valid in VMX operation:
0137      * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx.
0138      * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx.
0139      */
0140     __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory");
0141     cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1);
0142     cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0);
0143     __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory");
0144
0145     __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory");
0146     cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1);
0147     cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0);
0148     /* Enable VMX operation */
0149     cr4 |= X86_CR4_VMXE;
0150     __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory");
0151
0152     /*
0153      * Configure IA32_FEATURE_CONTROL MSR to allow VMXON:
0154      *  Bit 0: Lock bit. If clear, VMXON causes a #GP.
0155      *  Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON
0156      *    outside of SMX causes a #GP.
0157      */
0158     required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
0159     required |= FEAT_CTL_LOCKED;
0160     feature_control = rdmsr(MSR_IA32_FEAT_CTL);
0161     if ((feature_control & required) != required)
0162         wrmsr(MSR_IA32_FEAT_CTL, feature_control | required);
0163
0164     /* Enter VMX root operation. */
0165     *(uint32_t *)(vmx->vmxon) = vmcs_revision();
0166     if (vmxon(vmx->vmxon_gpa))
0167         return false;
0168
0169     return true;
0170 }
0171
0172 bool load_vmcs(struct vmx_pages *vmx)
0173 {
0174     if (!enable_evmcs) {
0175         /* Load a VMCS. */
0176         *(uint32_t *)(vmx->vmcs) = vmcs_revision();
0177         if (vmclear(vmx->vmcs_gpa))
0178             return false;
0179
0180         if (vmptrld(vmx->vmcs_gpa))
0181             return false;
0182
0183         /* Setup shadow VMCS, do not load it yet. */
0184         *(uint32_t *)(vmx->shadow_vmcs) =
0185             vmcs_revision() | 0x80000000ul;
0186         if (vmclear(vmx->shadow_vmcs_gpa))
0187             return false;
0188     } else {
0189         if (evmcs_vmptrld(vmx->enlightened_vmcs_gpa,
0190                   vmx->enlightened_vmcs))
0191             return false;
0192         current_evmcs->revision_id = EVMCS_VERSION;
0193     }
0194
0195     return true;
0196 }
0197
0198 static bool ept_vpid_cap_supported(uint64_t mask)
0199 {
0200     return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask;
0201 }
0202
0203 bool ept_1g_pages_supported(void)
0204 {
0205     return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES);
0206 }
0207
0208 /*
0209  * Initialize the control fields to the most basic settings possible.
0210  */
0211 static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
0212 {
0213     uint32_t sec_exec_ctl = 0;
0214
0215     vmwrite(VIRTUAL_PROCESSOR_ID, 0);
0216     vmwrite(POSTED_INTR_NV, 0);
0217
0218     vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS));
0219
0220     if (vmx->eptp_gpa) {
0221         uint64_t ept_paddr;
0222         struct eptPageTablePointer eptp = {
0223             .memory_type = VMX_BASIC_MEM_TYPE_WB,
0224             .page_walk_length = 3, /* + 1 */
0225             .ad_enabled = ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS),
0226             .address = vmx->eptp_gpa >> PAGE_SHIFT_4K,
0227         };
0228
0229         memcpy(&ept_paddr, &eptp, sizeof(ept_paddr));
0230         vmwrite(EPT_POINTER, ept_paddr);
0231         sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT;
0232     }
0233
0234     if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl))
0235         vmwrite(CPU_BASED_VM_EXEC_CONTROL,
0236             rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
0237     else {
0238         vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS));
0239         GUEST_ASSERT(!sec_exec_ctl);
0240     }
0241
0242     vmwrite(EXCEPTION_BITMAP, 0);
0243     vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0);
0244     vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */
0245     vmwrite(CR3_TARGET_COUNT, 0);
0246     vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) |
0247         VM_EXIT_HOST_ADDR_SPACE_SIZE);    /* 64-bit host */
0248     vmwrite(VM_EXIT_MSR_STORE_COUNT, 0);
0249     vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0);
0250     vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) |
0251         VM_ENTRY_IA32E_MODE);         /* 64-bit guest */
0252     vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0);
0253     vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0);
0254     vmwrite(TPR_THRESHOLD, 0);
0255
0256     vmwrite(CR0_GUEST_HOST_MASK, 0);
0257     vmwrite(CR4_GUEST_HOST_MASK, 0);
0258     vmwrite(CR0_READ_SHADOW, get_cr0());
0259     vmwrite(CR4_READ_SHADOW, get_cr4());
0260
0261     vmwrite(MSR_BITMAP, vmx->msr_gpa);
0262     vmwrite(VMREAD_BITMAP, vmx->vmread_gpa);
0263     vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa);
0264 }
0265
0266 /*
0267  * Initialize the host state fields based on the current host state, with
0268  * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch
0269  * or vmresume.
0270  */
0271 static inline void init_vmcs_host_state(void)
0272 {
0273     uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS);
0274
0275     vmwrite(HOST_ES_SELECTOR, get_es());
0276     vmwrite(HOST_CS_SELECTOR, get_cs());
0277     vmwrite(HOST_SS_SELECTOR, get_ss());
0278     vmwrite(HOST_DS_SELECTOR, get_ds());
0279     vmwrite(HOST_FS_SELECTOR, get_fs());
0280     vmwrite(HOST_GS_SELECTOR, get_gs());
0281     vmwrite(HOST_TR_SELECTOR, get_tr());
0282
0283     if (exit_controls & VM_EXIT_LOAD_IA32_PAT)
0284         vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT));
0285     if (exit_controls & VM_EXIT_LOAD_IA32_EFER)
0286         vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER));
0287     if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
0288         vmwrite(HOST_IA32_PERF_GLOBAL_CTRL,
0289             rdmsr(MSR_CORE_PERF_GLOBAL_CTRL));
0290
0291     vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS));
0292
0293     vmwrite(HOST_CR0, get_cr0());
0294     vmwrite(HOST_CR3, get_cr3());
0295     vmwrite(HOST_CR4, get_cr4());
0296     vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE));
0297     vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE));
0298     vmwrite(HOST_TR_BASE,
0299         get_desc64_base((struct desc64 *)(get_gdt().address + get_tr())));
0300     vmwrite(HOST_GDTR_BASE, get_gdt().address);
0301     vmwrite(HOST_IDTR_BASE, get_idt().address);
0302     vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP));
0303     vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP));
0304 }
0305
0306 /*
0307  * Initialize the guest state fields essentially as a clone of
0308  * the host state fields. Some host state fields have fixed
0309  * values, and we set the corresponding guest state fields accordingly.
0310  */
0311 static inline void init_vmcs_guest_state(void *rip, void *rsp)
0312 {
0313     vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR));
0314     vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR));
0315     vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR));
0316     vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR));
0317     vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR));
0318     vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR));
0319     vmwrite(GUEST_LDTR_SELECTOR, 0);
0320     vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR));
0321     vmwrite(GUEST_INTR_STATUS, 0);
0322     vmwrite(GUEST_PML_INDEX, 0);
0323
0324     vmwrite(VMCS_LINK_POINTER, -1ll);
0325     vmwrite(GUEST_IA32_DEBUGCTL, 0);
0326     vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT));
0327     vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER));
0328     vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL,
0329         vmreadz(HOST_IA32_PERF_GLOBAL_CTRL));
0330
0331     vmwrite(GUEST_ES_LIMIT, -1);
0332     vmwrite(GUEST_CS_LIMIT, -1);
0333     vmwrite(GUEST_SS_LIMIT, -1);
0334     vmwrite(GUEST_DS_LIMIT, -1);
0335     vmwrite(GUEST_FS_LIMIT, -1);
0336     vmwrite(GUEST_GS_LIMIT, -1);
0337     vmwrite(GUEST_LDTR_LIMIT, -1);
0338     vmwrite(GUEST_TR_LIMIT, 0x67);
0339     vmwrite(GUEST_GDTR_LIMIT, 0xffff);
0340     vmwrite(GUEST_IDTR_LIMIT, 0xffff);
0341     vmwrite(GUEST_ES_AR_BYTES,
0342         vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093);
0343     vmwrite(GUEST_CS_AR_BYTES, 0xa09b);
0344     vmwrite(GUEST_SS_AR_BYTES, 0xc093);
0345     vmwrite(GUEST_DS_AR_BYTES,
0346         vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093);
0347     vmwrite(GUEST_FS_AR_BYTES,
0348         vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093);
0349     vmwrite(GUEST_GS_AR_BYTES,
0350         vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093);
0351     vmwrite(GUEST_LDTR_AR_BYTES, 0x10000);
0352     vmwrite(GUEST_TR_AR_BYTES, 0x8b);
0353     vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
0354     vmwrite(GUEST_ACTIVITY_STATE, 0);
0355     vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS));
0356     vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0);
0357
0358     vmwrite(GUEST_CR0, vmreadz(HOST_CR0));
0359     vmwrite(GUEST_CR3, vmreadz(HOST_CR3));
0360     vmwrite(GUEST_CR4, vmreadz(HOST_CR4));
0361     vmwrite(GUEST_ES_BASE, 0);
0362     vmwrite(GUEST_CS_BASE, 0);
0363     vmwrite(GUEST_SS_BASE, 0);
0364     vmwrite(GUEST_DS_BASE, 0);
0365     vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE));
0366     vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE));
0367     vmwrite(GUEST_LDTR_BASE, 0);
0368     vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE));
0369     vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE));
0370     vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE));
0371     vmwrite(GUEST_DR7, 0x400);
0372     vmwrite(GUEST_RSP, (uint64_t)rsp);
0373     vmwrite(GUEST_RIP, (uint64_t)rip);
0374     vmwrite(GUEST_RFLAGS, 2);
0375     vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0);
0376     vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP));
0377     vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP));
0378 }
0379
0380 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp)
0381 {
0382     init_vmcs_control_fields(vmx);
0383     init_vmcs_host_state();
0384     init_vmcs_guest_state(guest_rip, guest_rsp);
0385 }
0386
0387 static void nested_create_pte(struct kvm_vm *vm,
0388                   struct eptPageTableEntry *pte,
0389                   uint64_t nested_paddr,
0390                   uint64_t paddr,
0391                   int current_level,
0392                   int target_level)
0393 {
0394     if (!pte->readable) {
0395         pte->writable = true;
0396         pte->readable = true;
0397         pte->executable = true;
0398         pte->page_size = (current_level == target_level);
0399         if (pte->page_size)
0400             pte->address = paddr >> vm->page_shift;
0401         else
0402             pte->address = vm_alloc_page_table(vm) >> vm->page_shift;
0403     } else {
0404         /*
0405          * Entry already present.  Assert that the caller doesn't want
0406          * a hugepage at this level, and that there isn't a hugepage at
0407          * this level.
0408          */
0409         TEST_ASSERT(current_level != target_level,
0410                 "Cannot create hugepage at level: %u, nested_paddr: 0x%lx\n",
0411                 current_level, nested_paddr);
0412         TEST_ASSERT(!pte->page_size,
0413                 "Cannot create page table at level: %u, nested_paddr: 0x%lx\n",
0414                 current_level, nested_paddr);
0415     }
0416 }
0417
0418
0419 void __nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
0420              uint64_t nested_paddr, uint64_t paddr, int target_level)
0421 {
0422     const uint64_t page_size = PG_LEVEL_SIZE(target_level);
0423     struct eptPageTableEntry *pt = vmx->eptp_hva, *pte;
0424     uint16_t index;
0425
0426     TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use "
0427             "unknown or unsupported guest mode, mode: 0x%x", vm->mode);
0428
0429     TEST_ASSERT((nested_paddr >> 48) == 0,
0430             "Nested physical address 0x%lx requires 5-level paging",
0431             nested_paddr);
0432     TEST_ASSERT((nested_paddr % page_size) == 0,
0433             "Nested physical address not on page boundary,\n"
0434             "  nested_paddr: 0x%lx page_size: 0x%lx",
0435             nested_paddr, page_size);
0436     TEST_ASSERT((nested_paddr >> vm->page_shift) <= vm->max_gfn,
0437             "Physical address beyond beyond maximum supported,\n"
0438             "  nested_paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
0439             paddr, vm->max_gfn, vm->page_size);
0440     TEST_ASSERT((paddr % page_size) == 0,
0441             "Physical address not on page boundary,\n"
0442             "  paddr: 0x%lx page_size: 0x%lx",
0443             paddr, page_size);
0444     TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
0445             "Physical address beyond beyond maximum supported,\n"
0446             "  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
0447             paddr, vm->max_gfn, vm->page_size);
0448
0449     for (int level = PG_LEVEL_512G; level >= PG_LEVEL_4K; level--) {
0450         index = (nested_paddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu;
0451         pte = &pt[index];
0452
0453         nested_create_pte(vm, pte, nested_paddr, paddr, level, target_level);
0454
0455         if (pte->page_size)
0456             break;
0457
0458         pt = addr_gpa2hva(vm, pte->address * vm->page_size);
0459     }
0460
0461     /*
0462      * For now mark these as accessed and dirty because the only
0463      * testcase we have needs that.  Can be reconsidered later.
0464      */
0465     pte->accessed = true;
0466     pte->dirty = true;
0467
0468 }
0469
0470 void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm,
0471            uint64_t nested_paddr, uint64_t paddr)
0472 {
0473     __nested_pg_map(vmx, vm, nested_paddr, paddr, PG_LEVEL_4K);
0474 }
0475
0476 /*
0477  * Map a range of EPT guest physical addresses to the VM's physical address
0478  *
0479  * Input Args:
0480  *   vm - Virtual Machine
0481  *   nested_paddr - Nested guest physical address to map
0482  *   paddr - VM Physical Address
0483  *   size - The size of the range to map
0484  *   level - The level at which to map the range
0485  *
0486  * Output Args: None
0487  *
0488  * Return: None
0489  *
0490  * Within the VM given by vm, creates a nested guest translation for the
0491  * page range starting at nested_paddr to the page range starting at paddr.
0492  */
0493 void __nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
0494           uint64_t nested_paddr, uint64_t paddr, uint64_t size,
0495           int level)
0496 {
0497     size_t page_size = PG_LEVEL_SIZE(level);
0498     size_t npages = size / page_size;
0499
0500     TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow");
0501     TEST_ASSERT(paddr + size > paddr, "Paddr overflow");
0502
0503     while (npages--) {
0504         __nested_pg_map(vmx, vm, nested_paddr, paddr, level);
0505         nested_paddr += page_size;
0506         paddr += page_size;
0507     }
0508 }
0509
0510 void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm,
0511         uint64_t nested_paddr, uint64_t paddr, uint64_t size)
0512 {
0513     __nested_map(vmx, vm, nested_paddr, paddr, size, PG_LEVEL_4K);
0514 }
0515
0516 /* Prepare an identity extended page table that maps all the
0517  * physical pages in VM.
0518  */
0519 void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm,
0520             uint32_t memslot)
0521 {
0522     sparsebit_idx_t i, last;
0523     struct userspace_mem_region *region =
0524         memslot2region(vm, memslot);
0525
0526     i = (region->region.guest_phys_addr >> vm->page_shift) - 1;
0527     last = i + (region->region.memory_size >> vm->page_shift);
0528     for (;;) {
0529         i = sparsebit_next_clear(region->unused_phy_pages, i);
0530         if (i > last)
0531             break;
0532
0533         nested_map(vmx, vm,
0534                (uint64_t)i << vm->page_shift,
0535                (uint64_t)i << vm->page_shift,
0536                1 << vm->page_shift);
0537     }
0538 }
0539
0540 /* Identity map a region with 1GiB Pages. */
0541 void nested_identity_map_1g(struct vmx_pages *vmx, struct kvm_vm *vm,
0542                 uint64_t addr, uint64_t size)
0543 {
0544     __nested_map(vmx, vm, addr, addr, size, PG_LEVEL_1G);
0545 }
0546
0547 bool kvm_vm_has_ept(struct kvm_vm *vm)
0548 {
0549     struct kvm_vcpu *vcpu;
0550     uint64_t ctrl;
0551
0552     vcpu = list_first_entry(&vm->vcpus, struct kvm_vcpu, list);
0553     TEST_ASSERT(vcpu, "Cannot determine EPT support without vCPUs.\n");
0554
0555     ctrl = vcpu_get_msr(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32;
0556     if (!(ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
0557         return false;
0558
0559     ctrl = vcpu_get_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS2) >> 32;
0560     return ctrl & SECONDARY_EXEC_ENABLE_EPT;
0561 }
0562
0563 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm,
0564           uint32_t eptp_memslot)
0565 {
0566     TEST_REQUIRE(kvm_vm_has_ept(vm));
0567
0568     vmx->eptp = (void *)vm_vaddr_alloc_page(vm);
0569     vmx->eptp_hva = addr_gva2hva(vm, (uintptr_t)vmx->eptp);
0570     vmx->eptp_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->eptp);
0571 }
0572
0573 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm)
0574 {
0575     vmx->apic_access = (void *)vm_vaddr_alloc_page(vm);
0576     vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access);
0577     vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access);
0578 }