lib/aarch64/processor.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AArch64 code
0004  *
0005  * Copyright (C) 2018, Red Hat, Inc.
0006  */
0007
0008 #include <linux/compiler.h>
0009 #include <assert.h>
0010
0011 #include "guest_modes.h"
0012 #include "kvm_util.h"
0013 #include "processor.h"
0014
0015 #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000
0016
0017 static vm_vaddr_t exception_handlers;
0018
0019 static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
0020 {
0021     return (v + vm->page_size) & ~(vm->page_size - 1);
0022 }
0023
0024 static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva)
0025 {
0026     unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
0027     uint64_t mask = (1UL << (vm->va_bits - shift)) - 1;
0028
0029     return (gva >> shift) & mask;
0030 }
0031
0032 static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva)
0033 {
0034     unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift;
0035     uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
0036
0037     TEST_ASSERT(vm->pgtable_levels == 4,
0038         "Mode %d does not have 4 page table levels", vm->mode);
0039
0040     return (gva >> shift) & mask;
0041 }
0042
0043 static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva)
0044 {
0045     unsigned int shift = (vm->page_shift - 3) + vm->page_shift;
0046     uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
0047
0048     TEST_ASSERT(vm->pgtable_levels >= 3,
0049         "Mode %d does not have >= 3 page table levels", vm->mode);
0050
0051     return (gva >> shift) & mask;
0052 }
0053
0054 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva)
0055 {
0056     uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
0057     return (gva >> vm->page_shift) & mask;
0058 }
0059
0060 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
0061 {
0062     uint64_t mask = ((1UL << (vm->va_bits - vm->page_shift)) - 1) << vm->page_shift;
0063     return entry & mask;
0064 }
0065
0066 static uint64_t ptrs_per_pgd(struct kvm_vm *vm)
0067 {
0068     unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
0069     return 1 << (vm->va_bits - shift);
0070 }
0071
0072 static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm)
0073 {
0074     return 1 << (vm->page_shift - 3);
0075 }
0076
0077 void virt_arch_pgd_alloc(struct kvm_vm *vm)
0078 {
0079     if (!vm->pgd_created) {
0080         vm_paddr_t paddr = vm_phy_pages_alloc(vm,
0081             page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size,
0082             KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
0083         vm->pgd = paddr;
0084         vm->pgd_created = true;
0085     }
0086 }
0087
0088 static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
0089              uint64_t flags)
0090 {
0091     uint8_t attr_idx = flags & 7;
0092     uint64_t *ptep;
0093
0094     TEST_ASSERT((vaddr % vm->page_size) == 0,
0095         "Virtual address not on page boundary,\n"
0096         "  vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
0097     TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
0098         (vaddr >> vm->page_shift)),
0099         "Invalid virtual address, vaddr: 0x%lx", vaddr);
0100     TEST_ASSERT((paddr % vm->page_size) == 0,
0101         "Physical address not on page boundary,\n"
0102         "  paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
0103     TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
0104         "Physical address beyond beyond maximum supported,\n"
0105         "  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
0106         paddr, vm->max_gfn, vm->page_size);
0107
0108     ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, vaddr) * 8;
0109     if (!*ptep)
0110         *ptep = vm_alloc_page_table(vm) | 3;
0111
0112     switch (vm->pgtable_levels) {
0113     case 4:
0114         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8;
0115         if (!*ptep)
0116             *ptep = vm_alloc_page_table(vm) | 3;
0117         /* fall through */
0118     case 3:
0119         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8;
0120         if (!*ptep)
0121             *ptep = vm_alloc_page_table(vm) | 3;
0122         /* fall through */
0123     case 2:
0124         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8;
0125         break;
0126     default:
0127         TEST_FAIL("Page table levels must be 2, 3, or 4");
0128     }
0129
0130     *ptep = paddr | 3;
0131     *ptep |= (attr_idx << 2) | (1 << 10) /* Access Flag */;
0132 }
0133
0134 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
0135 {
0136     uint64_t attr_idx = 4; /* NORMAL (See DEFAULT_MAIR_EL1) */
0137
0138     _virt_pg_map(vm, vaddr, paddr, attr_idx);
0139 }
0140
0141 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
0142 {
0143     uint64_t *ptep;
0144
0145     if (!vm->pgd_created)
0146         goto unmapped_gva;
0147
0148     ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, gva) * 8;
0149     if (!ptep)
0150         goto unmapped_gva;
0151
0152     switch (vm->pgtable_levels) {
0153     case 4:
0154         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8;
0155         if (!ptep)
0156             goto unmapped_gva;
0157         /* fall through */
0158     case 3:
0159         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8;
0160         if (!ptep)
0161             goto unmapped_gva;
0162         /* fall through */
0163     case 2:
0164         ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8;
0165         if (!ptep)
0166             goto unmapped_gva;
0167         break;
0168     default:
0169         TEST_FAIL("Page table levels must be 2, 3, or 4");
0170     }
0171
0172     return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
0173
0174 unmapped_gva:
0175     TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva);
0176     exit(1);
0177 }
0178
0179 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)
0180 {
0181 #ifdef DEBUG
0182     static const char * const type[] = { "", "pud", "pmd", "pte" };
0183     uint64_t pte, *ptep;
0184
0185     if (level == 4)
0186         return;
0187
0188     for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
0189         ptep = addr_gpa2hva(vm, pte);
0190         if (!*ptep)
0191             continue;
0192         fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep);
0193         pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1);
0194     }
0195 #endif
0196 }
0197
0198 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
0199 {
0200     int level = 4 - (vm->pgtable_levels - 1);
0201     uint64_t pgd, *ptep;
0202
0203     if (!vm->pgd_created)
0204         return;
0205
0206     for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pgd(vm) * 8; pgd += 8) {
0207         ptep = addr_gpa2hva(vm, pgd);
0208         if (!*ptep)
0209             continue;
0210         fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep);
0211         pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level);
0212     }
0213 }
0214
0215 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
0216 {
0217     struct kvm_vcpu_init default_init = { .target = -1, };
0218     struct kvm_vm *vm = vcpu->vm;
0219     uint64_t sctlr_el1, tcr_el1;
0220
0221     if (!init)
0222         init = &default_init;
0223
0224     if (init->target == -1) {
0225         struct kvm_vcpu_init preferred;
0226         vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred);
0227         init->target = preferred.target;
0228     }
0229
0230     vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init);
0231
0232     /*
0233      * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15
0234      * registers, which the variable argument list macros do.
0235      */
0236     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CPACR_EL1), 3 << 20);
0237
0238     vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1), &sctlr_el1);
0239     vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1), &tcr_el1);
0240
0241     /* Configure base granule size */
0242     switch (vm->mode) {
0243     case VM_MODE_P52V48_4K:
0244         TEST_FAIL("AArch64 does not support 4K sized pages "
0245               "with 52-bit physical address ranges");
0246     case VM_MODE_PXXV48_4K:
0247         TEST_FAIL("AArch64 does not support 4K sized pages "
0248               "with ANY-bit physical address ranges");
0249     case VM_MODE_P52V48_64K:
0250     case VM_MODE_P48V48_64K:
0251     case VM_MODE_P40V48_64K:
0252     case VM_MODE_P36V48_64K:
0253         tcr_el1 |= 1ul << 14; /* TG0 = 64KB */
0254         break;
0255     case VM_MODE_P48V48_16K:
0256     case VM_MODE_P40V48_16K:
0257     case VM_MODE_P36V48_16K:
0258     case VM_MODE_P36V47_16K:
0259         tcr_el1 |= 2ul << 14; /* TG0 = 16KB */
0260         break;
0261     case VM_MODE_P48V48_4K:
0262     case VM_MODE_P40V48_4K:
0263     case VM_MODE_P36V48_4K:
0264         tcr_el1 |= 0ul << 14; /* TG0 = 4KB */
0265         break;
0266     default:
0267         TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
0268     }
0269
0270     /* Configure output size */
0271     switch (vm->mode) {
0272     case VM_MODE_P52V48_64K:
0273         tcr_el1 |= 6ul << 32; /* IPS = 52 bits */
0274         break;
0275     case VM_MODE_P48V48_4K:
0276     case VM_MODE_P48V48_16K:
0277     case VM_MODE_P48V48_64K:
0278         tcr_el1 |= 5ul << 32; /* IPS = 48 bits */
0279         break;
0280     case VM_MODE_P40V48_4K:
0281     case VM_MODE_P40V48_16K:
0282     case VM_MODE_P40V48_64K:
0283         tcr_el1 |= 2ul << 32; /* IPS = 40 bits */
0284         break;
0285     case VM_MODE_P36V48_4K:
0286     case VM_MODE_P36V48_16K:
0287     case VM_MODE_P36V48_64K:
0288     case VM_MODE_P36V47_16K:
0289         tcr_el1 |= 1ul << 32; /* IPS = 36 bits */
0290         break;
0291     default:
0292         TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
0293     }
0294
0295     sctlr_el1 |= (1 << 0) | (1 << 2) | (1 << 12) /* M | C | I */;
0296     /* TCR_EL1 |= IRGN0:WBWA | ORGN0:WBWA | SH0:Inner-Shareable */;
0297     tcr_el1 |= (1 << 8) | (1 << 10) | (3 << 12);
0298     tcr_el1 |= (64 - vm->va_bits) /* T0SZ */;
0299
0300     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1), sctlr_el1);
0301     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1), tcr_el1);
0302     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MAIR_EL1), DEFAULT_MAIR_EL1);
0303     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TTBR0_EL1), vm->pgd);
0304     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id);
0305 }
0306
0307 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
0308 {
0309     uint64_t pstate, pc;
0310
0311     vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate), &pstate);
0312     vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc);
0313
0314     fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n",
0315         indent, "", pstate, pc);
0316 }
0317
0318 struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
0319                   struct kvm_vcpu_init *init, void *guest_code)
0320 {
0321     size_t stack_size = vm->page_size == 4096 ?
0322                     DEFAULT_STACK_PGS * vm->page_size :
0323                     vm->page_size;
0324     uint64_t stack_vaddr = vm_vaddr_alloc(vm, stack_size,
0325                           DEFAULT_ARM64_GUEST_STACK_VADDR_MIN);
0326     struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id);
0327
0328     aarch64_vcpu_setup(vcpu, init);
0329
0330     vcpu_set_reg(vcpu, ARM64_CORE_REG(sp_el1), stack_vaddr + stack_size);
0331     vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code);
0332
0333     return vcpu;
0334 }
0335
0336 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
0337                   void *guest_code)
0338 {
0339     return aarch64_vcpu_add(vm, vcpu_id, NULL, guest_code);
0340 }
0341
0342 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
0343 {
0344     va_list ap;
0345     int i;
0346
0347     TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
0348             "  num: %u\n", num);
0349
0350     va_start(ap, num);
0351
0352     for (i = 0; i < num; i++) {
0353         vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]),
0354                  va_arg(ap, uint64_t));
0355     }
0356
0357     va_end(ap);
0358 }
0359
0360 void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec)
0361 {
0362     ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec);
0363     while (1)
0364         ;
0365 }
0366
0367 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
0368 {
0369     struct ucall uc;
0370
0371     if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED)
0372         return;
0373
0374     if (uc.args[2]) /* valid_ec */ {
0375         assert(VECTOR_IS_SYNC(uc.args[0]));
0376         TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)",
0377               uc.args[0], uc.args[1]);
0378     } else {
0379         assert(!VECTOR_IS_SYNC(uc.args[0]));
0380         TEST_FAIL("Unexpected exception (vector:0x%lx)",
0381               uc.args[0]);
0382     }
0383 }
0384
0385 struct handlers {
0386     handler_fn exception_handlers[VECTOR_NUM][ESR_EC_NUM];
0387 };
0388
0389 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu)
0390 {
0391     extern char vectors;
0392
0393     vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_VBAR_EL1), (uint64_t)&vectors);
0394 }
0395
0396 void route_exception(struct ex_regs *regs, int vector)
0397 {
0398     struct handlers *handlers = (struct handlers *)exception_handlers;
0399     bool valid_ec;
0400     int ec = 0;
0401
0402     switch (vector) {
0403     case VECTOR_SYNC_CURRENT:
0404     case VECTOR_SYNC_LOWER_64:
0405         ec = (read_sysreg(esr_el1) >> ESR_EC_SHIFT) & ESR_EC_MASK;
0406         valid_ec = true;
0407         break;
0408     case VECTOR_IRQ_CURRENT:
0409     case VECTOR_IRQ_LOWER_64:
0410     case VECTOR_FIQ_CURRENT:
0411     case VECTOR_FIQ_LOWER_64:
0412     case VECTOR_ERROR_CURRENT:
0413     case VECTOR_ERROR_LOWER_64:
0414         ec = 0;
0415         valid_ec = false;
0416         break;
0417     default:
0418         valid_ec = false;
0419         goto unexpected_exception;
0420     }
0421
0422     if (handlers && handlers->exception_handlers[vector][ec])
0423         return handlers->exception_handlers[vector][ec](regs);
0424
0425 unexpected_exception:
0426     kvm_exit_unexpected_exception(vector, ec, valid_ec);
0427 }
0428
0429 void vm_init_descriptor_tables(struct kvm_vm *vm)
0430 {
0431     vm->handlers = vm_vaddr_alloc(vm, sizeof(struct handlers),
0432             vm->page_size);
0433
0434     *(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
0435 }
0436
0437 void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec,
0438              void (*handler)(struct ex_regs *))
0439 {
0440     struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
0441
0442     assert(VECTOR_IS_SYNC(vector));
0443     assert(vector < VECTOR_NUM);
0444     assert(ec < ESR_EC_NUM);
0445     handlers->exception_handlers[vector][ec] = handler;
0446 }
0447
0448 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
0449              void (*handler)(struct ex_regs *))
0450 {
0451     struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
0452
0453     assert(!VECTOR_IS_SYNC(vector));
0454     assert(vector < VECTOR_NUM);
0455     handlers->exception_handlers[vector][0] = handler;
0456 }
0457
0458 uint32_t guest_get_vcpuid(void)
0459 {
0460     return read_sysreg(tpidr_el1);
0461 }
0462
0463 void aarch64_get_supported_page_sizes(uint32_t ipa,
0464                       bool *ps4k, bool *ps16k, bool *ps64k)
0465 {
0466     struct kvm_vcpu_init preferred_init;
0467     int kvm_fd, vm_fd, vcpu_fd, err;
0468     uint64_t val;
0469     struct kvm_one_reg reg = {
0470         .id = KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1),
0471         .addr   = (uint64_t)&val,
0472     };
0473
0474     kvm_fd = open_kvm_dev_path_or_exit();
0475     vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, (void *)(unsigned long)ipa);
0476     TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd));
0477
0478     vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0);
0479     TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd));
0480
0481     err = ioctl(vm_fd, KVM_ARM_PREFERRED_TARGET, &preferred_init);
0482     TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_PREFERRED_TARGET, err));
0483     err = ioctl(vcpu_fd, KVM_ARM_VCPU_INIT, &preferred_init);
0484     TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_VCPU_INIT, err));
0485
0486     err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg);
0487     TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
0488
0489     *ps4k = ((val >> 28) & 0xf) != 0xf;
0490     *ps64k = ((val >> 24) & 0xf) == 0;
0491     *ps16k = ((val >> 20) & 0xf) != 0;
0492
0493     close(vcpu_fd);
0494     close(vm_fd);
0495     close(kvm_fd);
0496 }
0497
0498 /*
0499  * arm64 doesn't have a true default mode, so start by computing the
0500  * available IPA space and page sizes early.
0501  */
0502 void __attribute__((constructor)) init_guest_modes(void)
0503 {
0504        guest_modes_append_default();
0505 }
0506
0507 void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
0508            uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
0509            uint64_t arg6, struct arm_smccc_res *res)
0510 {
0511     asm volatile("mov   w0, %w[function_id]\n"
0512              "mov   x1, %[arg0]\n"
0513              "mov   x2, %[arg1]\n"
0514              "mov   x3, %[arg2]\n"
0515              "mov   x4, %[arg3]\n"
0516              "mov   x5, %[arg4]\n"
0517              "mov   x6, %[arg5]\n"
0518              "mov   x7, %[arg6]\n"
0519              "hvc   #0\n"
0520              "mov   %[res0], x0\n"
0521              "mov   %[res1], x1\n"
0522              "mov   %[res2], x2\n"
0523              "mov   %[res3], x3\n"
0524              : [res0] "=r"(res->a0), [res1] "=r"(res->a1),
0525                [res2] "=r"(res->a2), [res3] "=r"(res->a3)
0526              : [function_id] "r"(function_id), [arg0] "r"(arg0),
0527                [arg1] "r"(arg1), [arg2] "r"(arg2), [arg3] "r"(arg3),
0528                [arg4] "r"(arg4), [arg5] "r"(arg5), [arg6] "r"(arg6)
0529              : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7");
0530 }