include/riscv/processor.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * RISC-V processor specific defines
0004  *
0005  * Copyright (C) 2021 Western Digital Corporation or its affiliates.
0006  */
0007 #ifndef SELFTEST_KVM_PROCESSOR_H
0008 #define SELFTEST_KVM_PROCESSOR_H
0009
0010 #include "kvm_util.h"
0011 #include <linux/stringify.h>
0012
0013 static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
0014                     uint64_t  size)
0015 {
0016     return KVM_REG_RISCV | type | idx | size;
0017 }
0018
0019 #if __riscv_xlen == 64
0020 #define KVM_REG_SIZE_ULONG  KVM_REG_SIZE_U64
0021 #else
0022 #define KVM_REG_SIZE_ULONG  KVM_REG_SIZE_U32
0023 #endif
0024
0025 #define RISCV_CONFIG_REG(name)  __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
0026                          KVM_REG_RISCV_CONFIG_REG(name), \
0027                          KVM_REG_SIZE_ULONG)
0028
0029 #define RISCV_CORE_REG(name)    __kvm_reg_id(KVM_REG_RISCV_CORE, \
0030                          KVM_REG_RISCV_CORE_REG(name), \
0031                          KVM_REG_SIZE_ULONG)
0032
0033 #define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
0034                          KVM_REG_RISCV_CSR_REG(name), \
0035                          KVM_REG_SIZE_ULONG)
0036
0037 #define RISCV_TIMER_REG(name)   __kvm_reg_id(KVM_REG_RISCV_TIMER, \
0038                          KVM_REG_RISCV_TIMER_REG(name), \
0039                          KVM_REG_SIZE_U64)
0040
0041 /* L3 index Bit[47:39] */
0042 #define PGTBL_L3_INDEX_MASK         0x0000FF8000000000ULL
0043 #define PGTBL_L3_INDEX_SHIFT            39
0044 #define PGTBL_L3_BLOCK_SHIFT            39
0045 #define PGTBL_L3_BLOCK_SIZE         0x0000008000000000ULL
0046 #define PGTBL_L3_MAP_MASK           (~(PGTBL_L3_BLOCK_SIZE - 1))
0047 /* L2 index Bit[38:30] */
0048 #define PGTBL_L2_INDEX_MASK         0x0000007FC0000000ULL
0049 #define PGTBL_L2_INDEX_SHIFT            30
0050 #define PGTBL_L2_BLOCK_SHIFT            30
0051 #define PGTBL_L2_BLOCK_SIZE         0x0000000040000000ULL
0052 #define PGTBL_L2_MAP_MASK           (~(PGTBL_L2_BLOCK_SIZE - 1))
0053 /* L1 index Bit[29:21] */
0054 #define PGTBL_L1_INDEX_MASK         0x000000003FE00000ULL
0055 #define PGTBL_L1_INDEX_SHIFT            21
0056 #define PGTBL_L1_BLOCK_SHIFT            21
0057 #define PGTBL_L1_BLOCK_SIZE         0x0000000000200000ULL
0058 #define PGTBL_L1_MAP_MASK           (~(PGTBL_L1_BLOCK_SIZE - 1))
0059 /* L0 index Bit[20:12] */
0060 #define PGTBL_L0_INDEX_MASK         0x00000000001FF000ULL
0061 #define PGTBL_L0_INDEX_SHIFT            12
0062 #define PGTBL_L0_BLOCK_SHIFT            12
0063 #define PGTBL_L0_BLOCK_SIZE         0x0000000000001000ULL
0064 #define PGTBL_L0_MAP_MASK           (~(PGTBL_L0_BLOCK_SIZE - 1))
0065
0066 #define PGTBL_PTE_ADDR_MASK         0x003FFFFFFFFFFC00ULL
0067 #define PGTBL_PTE_ADDR_SHIFT            10
0068 #define PGTBL_PTE_RSW_MASK          0x0000000000000300ULL
0069 #define PGTBL_PTE_RSW_SHIFT         8
0070 #define PGTBL_PTE_DIRTY_MASK            0x0000000000000080ULL
0071 #define PGTBL_PTE_DIRTY_SHIFT           7
0072 #define PGTBL_PTE_ACCESSED_MASK         0x0000000000000040ULL
0073 #define PGTBL_PTE_ACCESSED_SHIFT        6
0074 #define PGTBL_PTE_GLOBAL_MASK           0x0000000000000020ULL
0075 #define PGTBL_PTE_GLOBAL_SHIFT          5
0076 #define PGTBL_PTE_USER_MASK         0x0000000000000010ULL
0077 #define PGTBL_PTE_USER_SHIFT            4
0078 #define PGTBL_PTE_EXECUTE_MASK          0x0000000000000008ULL
0079 #define PGTBL_PTE_EXECUTE_SHIFT         3
0080 #define PGTBL_PTE_WRITE_MASK            0x0000000000000004ULL
0081 #define PGTBL_PTE_WRITE_SHIFT           2
0082 #define PGTBL_PTE_READ_MASK         0x0000000000000002ULL
0083 #define PGTBL_PTE_READ_SHIFT            1
0084 #define PGTBL_PTE_PERM_MASK         (PGTBL_PTE_ACCESSED_MASK | \
0085                          PGTBL_PTE_DIRTY_MASK | \
0086                          PGTBL_PTE_EXECUTE_MASK | \
0087                          PGTBL_PTE_WRITE_MASK | \
0088                          PGTBL_PTE_READ_MASK)
0089 #define PGTBL_PTE_VALID_MASK            0x0000000000000001ULL
0090 #define PGTBL_PTE_VALID_SHIFT           0
0091
0092 #define PGTBL_PAGE_SIZE             PGTBL_L0_BLOCK_SIZE
0093 #define PGTBL_PAGE_SIZE_SHIFT           PGTBL_L0_BLOCK_SHIFT
0094
0095 #define SATP_PPN                _AC(0x00000FFFFFFFFFFF, UL)
0096 #define SATP_MODE_39                _AC(0x8000000000000000, UL)
0097 #define SATP_MODE_48                _AC(0x9000000000000000, UL)
0098 #define SATP_ASID_BITS              16
0099 #define SATP_ASID_SHIFT             44
0100 #define SATP_ASID_MASK              _AC(0xFFFF, UL)
0101
0102 #define SBI_EXT_EXPERIMENTAL_START      0x08000000
0103 #define SBI_EXT_EXPERIMENTAL_END        0x08FFFFFF
0104
0105 #define KVM_RISCV_SELFTESTS_SBI_EXT     SBI_EXT_EXPERIMENTAL_END
0106 #define KVM_RISCV_SELFTESTS_SBI_UCALL       0
0107 #define KVM_RISCV_SELFTESTS_SBI_UNEXP       1
0108
0109 struct sbiret {
0110     long error;
0111     long value;
0112 };
0113
0114 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
0115             unsigned long arg1, unsigned long arg2,
0116             unsigned long arg3, unsigned long arg4,
0117             unsigned long arg5);
0118
0119 #endif /* SELFTEST_KVM_PROCESSOR_H */