include/aarch64/gic.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ARM Generic Interrupt Controller (GIC) specific defines
0004  */
0005
0006 #ifndef SELFTEST_KVM_GIC_H
0007 #define SELFTEST_KVM_GIC_H
0008
0009 enum gic_type {
0010     GIC_V3,
0011     GIC_TYPE_MAX,
0012 };
0013
0014 #define MIN_SGI         0
0015 #define MIN_PPI         16
0016 #define MIN_SPI         32
0017 #define MAX_SPI         1019
0018 #define IAR_SPURIOUS        1023
0019
0020 #define INTID_IS_SGI(intid) (0       <= (intid) && (intid) < MIN_PPI)
0021 #define INTID_IS_PPI(intid) (MIN_PPI <= (intid) && (intid) < MIN_SPI)
0022 #define INTID_IS_SPI(intid) (MIN_SPI <= (intid) && (intid) <= MAX_SPI)
0023
0024 void gic_init(enum gic_type type, unsigned int nr_cpus,
0025         void *dist_base, void *redist_base);
0026 void gic_irq_enable(unsigned int intid);
0027 void gic_irq_disable(unsigned int intid);
0028 unsigned int gic_get_and_ack_irq(void);
0029 void gic_set_eoi(unsigned int intid);
0030 void gic_set_dir(unsigned int intid);
0031
0032 /*
0033  * Sets the EOI mode. When split is false, EOI just drops the priority. When
0034  * split is true, EOI drops the priority and deactivates the interrupt.
0035  */
0036 void gic_set_eoi_split(bool split);
0037 void gic_set_priority_mask(uint64_t mask);
0038 void gic_set_priority(uint32_t intid, uint32_t prio);
0039 void gic_irq_set_active(unsigned int intid);
0040 void gic_irq_clear_active(unsigned int intid);
0041 bool gic_irq_get_active(unsigned int intid);
0042 void gic_irq_set_pending(unsigned int intid);
0043 void gic_irq_clear_pending(unsigned int intid);
0044 bool gic_irq_get_pending(unsigned int intid);
0045 void gic_irq_set_config(unsigned int intid, bool is_edge);
0046
0047 #endif /* SELFTEST_KVM_GIC_H */