kvm/aarch64/debug-exceptions.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <test_util.h>
0003 #include <kvm_util.h>
0004 #include <processor.h>
0005
0006 #define MDSCR_KDE   (1 << 13)
0007 #define MDSCR_MDE   (1 << 15)
0008 #define MDSCR_SS    (1 << 0)
0009
0010 #define DBGBCR_LEN8 (0xff << 5)
0011 #define DBGBCR_EXEC (0x0 << 3)
0012 #define DBGBCR_EL1  (0x1 << 1)
0013 #define DBGBCR_E    (0x1 << 0)
0014
0015 #define DBGWCR_LEN8 (0xff << 5)
0016 #define DBGWCR_RD   (0x1 << 3)
0017 #define DBGWCR_WR   (0x2 << 3)
0018 #define DBGWCR_EL1  (0x1 << 1)
0019 #define DBGWCR_E    (0x1 << 0)
0020
0021 #define SPSR_D      (1 << 9)
0022 #define SPSR_SS     (1 << 21)
0023
0024 extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start;
0025 static volatile uint64_t sw_bp_addr, hw_bp_addr;
0026 static volatile uint64_t wp_addr, wp_data_addr;
0027 static volatile uint64_t svc_addr;
0028 static volatile uint64_t ss_addr[4], ss_idx;
0029 #define  PC(v)  ((uint64_t)&(v))
0030
0031 static void reset_debug_state(void)
0032 {
0033     asm volatile("msr daifset, #8");
0034
0035     write_sysreg(0, osdlr_el1);
0036     write_sysreg(0, oslar_el1);
0037     isb();
0038
0039     write_sysreg(0, mdscr_el1);
0040     /* This test only uses the first bp and wp slot. */
0041     write_sysreg(0, dbgbvr0_el1);
0042     write_sysreg(0, dbgbcr0_el1);
0043     write_sysreg(0, dbgwcr0_el1);
0044     write_sysreg(0, dbgwvr0_el1);
0045     isb();
0046 }
0047
0048 static void enable_os_lock(void)
0049 {
0050     write_sysreg(1, oslar_el1);
0051     isb();
0052
0053     GUEST_ASSERT(read_sysreg(oslsr_el1) & 2);
0054 }
0055
0056 static void install_wp(uint64_t addr)
0057 {
0058     uint32_t wcr;
0059     uint32_t mdscr;
0060
0061     wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;
0062     write_sysreg(wcr, dbgwcr0_el1);
0063     write_sysreg(addr, dbgwvr0_el1);
0064     isb();
0065
0066     asm volatile("msr daifclr, #8");
0067
0068     mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;
0069     write_sysreg(mdscr, mdscr_el1);
0070     isb();
0071 }
0072
0073 static void install_hw_bp(uint64_t addr)
0074 {
0075     uint32_t bcr;
0076     uint32_t mdscr;
0077
0078     bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E;
0079     write_sysreg(bcr, dbgbcr0_el1);
0080     write_sysreg(addr, dbgbvr0_el1);
0081     isb();
0082
0083     asm volatile("msr daifclr, #8");
0084
0085     mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;
0086     write_sysreg(mdscr, mdscr_el1);
0087     isb();
0088 }
0089
0090 static void install_ss(void)
0091 {
0092     uint32_t mdscr;
0093
0094     asm volatile("msr daifclr, #8");
0095
0096     mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_SS;
0097     write_sysreg(mdscr, mdscr_el1);
0098     isb();
0099 }
0100
0101 static volatile char write_data;
0102
0103 static void guest_code(void)
0104 {
0105     GUEST_SYNC(0);
0106
0107     /* Software-breakpoint */
0108     reset_debug_state();
0109     asm volatile("sw_bp: brk #0");
0110     GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp));
0111
0112     GUEST_SYNC(1);
0113
0114     /* Hardware-breakpoint */
0115     reset_debug_state();
0116     install_hw_bp(PC(hw_bp));
0117     asm volatile("hw_bp: nop");
0118     GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp));
0119
0120     GUEST_SYNC(2);
0121
0122     /* Hardware-breakpoint + svc */
0123     reset_debug_state();
0124     install_hw_bp(PC(bp_svc));
0125     asm volatile("bp_svc: svc #0");
0126     GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc));
0127     GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4);
0128
0129     GUEST_SYNC(3);
0130
0131     /* Hardware-breakpoint + software-breakpoint */
0132     reset_debug_state();
0133     install_hw_bp(PC(bp_brk));
0134     asm volatile("bp_brk: brk #0");
0135     GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk));
0136     GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk));
0137
0138     GUEST_SYNC(4);
0139
0140     /* Watchpoint */
0141     reset_debug_state();
0142     install_wp(PC(write_data));
0143     write_data = 'x';
0144     GUEST_ASSERT_EQ(write_data, 'x');
0145     GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));
0146
0147     GUEST_SYNC(5);
0148
0149     /* Single-step */
0150     reset_debug_state();
0151     install_ss();
0152     ss_idx = 0;
0153     asm volatile("ss_start:\n"
0154              "mrs x0, esr_el1\n"
0155              "add x0, x0, #1\n"
0156              "msr daifset, #8\n"
0157              : : : "x0");
0158     GUEST_ASSERT_EQ(ss_addr[0], PC(ss_start));
0159     GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4);
0160     GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8);
0161
0162     GUEST_SYNC(6);
0163
0164     /* OS Lock does not block software-breakpoint */
0165     reset_debug_state();
0166     enable_os_lock();
0167     sw_bp_addr = 0;
0168     asm volatile("sw_bp2: brk #0");
0169     GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2));
0170
0171     GUEST_SYNC(7);
0172
0173     /* OS Lock blocking hardware-breakpoint */
0174     reset_debug_state();
0175     enable_os_lock();
0176     install_hw_bp(PC(hw_bp2));
0177     hw_bp_addr = 0;
0178     asm volatile("hw_bp2: nop");
0179     GUEST_ASSERT_EQ(hw_bp_addr, 0);
0180
0181     GUEST_SYNC(8);
0182
0183     /* OS Lock blocking watchpoint */
0184     reset_debug_state();
0185     enable_os_lock();
0186     write_data = '\0';
0187     wp_data_addr = 0;
0188     install_wp(PC(write_data));
0189     write_data = 'x';
0190     GUEST_ASSERT_EQ(write_data, 'x');
0191     GUEST_ASSERT_EQ(wp_data_addr, 0);
0192
0193     GUEST_SYNC(9);
0194
0195     /* OS Lock blocking single-step */
0196     reset_debug_state();
0197     enable_os_lock();
0198     ss_addr[0] = 0;
0199     install_ss();
0200     ss_idx = 0;
0201     asm volatile("mrs x0, esr_el1\n\t"
0202              "add x0, x0, #1\n\t"
0203              "msr daifset, #8\n\t"
0204              : : : "x0");
0205     GUEST_ASSERT_EQ(ss_addr[0], 0);
0206
0207     GUEST_DONE();
0208 }
0209
0210 static void guest_sw_bp_handler(struct ex_regs *regs)
0211 {
0212     sw_bp_addr = regs->pc;
0213     regs->pc += 4;
0214 }
0215
0216 static void guest_hw_bp_handler(struct ex_regs *regs)
0217 {
0218     hw_bp_addr = regs->pc;
0219     regs->pstate |= SPSR_D;
0220 }
0221
0222 static void guest_wp_handler(struct ex_regs *regs)
0223 {
0224     wp_data_addr = read_sysreg(far_el1);
0225     wp_addr = regs->pc;
0226     regs->pstate |= SPSR_D;
0227 }
0228
0229 static void guest_ss_handler(struct ex_regs *regs)
0230 {
0231     GUEST_ASSERT_1(ss_idx < 4, ss_idx);
0232     ss_addr[ss_idx++] = regs->pc;
0233     regs->pstate |= SPSR_SS;
0234 }
0235
0236 static void guest_svc_handler(struct ex_regs *regs)
0237 {
0238     svc_addr = regs->pc;
0239 }
0240
0241 static int debug_version(struct kvm_vcpu *vcpu)
0242 {
0243     uint64_t id_aa64dfr0;
0244
0245     vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &id_aa64dfr0);
0246     return id_aa64dfr0 & 0xf;
0247 }
0248
0249 int main(int argc, char *argv[])
0250 {
0251     struct kvm_vcpu *vcpu;
0252     struct kvm_vm *vm;
0253     struct ucall uc;
0254     int stage;
0255
0256     vm = vm_create_with_one_vcpu(&vcpu, guest_code);
0257     ucall_init(vm, NULL);
0258
0259     vm_init_descriptor_tables(vm);
0260     vcpu_init_descriptor_tables(vcpu);
0261
0262     __TEST_REQUIRE(debug_version(vcpu) >= 6,
0263                "Armv8 debug architecture not supported.");
0264
0265     vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
0266                 ESR_EC_BRK_INS, guest_sw_bp_handler);
0267     vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
0268                 ESR_EC_HW_BP_CURRENT, guest_hw_bp_handler);
0269     vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
0270                 ESR_EC_WP_CURRENT, guest_wp_handler);
0271     vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
0272                 ESR_EC_SSTEP_CURRENT, guest_ss_handler);
0273     vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
0274                 ESR_EC_SVC64, guest_svc_handler);
0275
0276     for (stage = 0; stage < 11; stage++) {
0277         vcpu_run(vcpu);
0278
0279         switch (get_ucall(vcpu, &uc)) {
0280         case UCALL_SYNC:
0281             TEST_ASSERT(uc.args[1] == stage,
0282                 "Stage %d: Unexpected sync ucall, got %lx",
0283                 stage, (ulong)uc.args[1]);
0284             break;
0285         case UCALL_ABORT:
0286             REPORT_GUEST_ASSERT_2(uc, "values: %#lx, %#lx");
0287             break;
0288         case UCALL_DONE:
0289             goto done;
0290         default:
0291             TEST_FAIL("Unknown ucall %lu", uc.cmd);
0292         }
0293     }
0294
0295 done:
0296     kvm_vm_free(vm);
0297     return 0;
0298 }