0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2021 ARM Limited.
0003 //
0004 // Assembly portion of the syscall ABI test
0005
0006 //
0007 // Load values from memory into registers, invoke a syscall and save the
0008 // register values back to memory for later checking. The syscall to be
0009 // invoked is configured in x8 of the input GPR data.
0010 //
0011 // x0: SVE VL, 0 for FP only
0012 // x1: SME VL
0013 //
0014 // GPRs: gpr_in, gpr_out
0015 // FPRs: fpr_in, fpr_out
0016 // Zn: z_in, z_out
0017 // Pn: p_in, p_out
0018 // FFR: ffr_in, ffr_out
0019 // ZA: za_in, za_out
0020 // SVCR: svcr_in, svcr_out
0021
0022 #include "syscall-abi.h"
0023
0024 .arch_extension sve
0025
0026
0027
0028
0029
0030 .macro _ldr_za nw, nxbase, offset=0
0031 .inst 0xe1000000 \
0032 | (((\nw) & 3) << 13) \
0033 | ((\nxbase) << 5) \
0034 | ((\offset) & 7)
0035 .endm
0036
0037
0038
0039
0040
0041 .macro _str_za nw, nxbase, offset=0
0042 .inst 0xe1200000 \
0043 | (((\nw) & 3) << 13) \
0044 | ((\nxbase) << 5) \
0045 | ((\offset) & 7)
0046 .endm
0047
0048 .globl do_syscall
0049 do_syscall:
0050 // Store callee saved registers x19-x29 (80 bytes) plus x0 and x1
0051 stp x29, x30, [sp, #-112]!
0052 mov x29, sp
0053 stp x0, x1, [sp, #16]
0054 stp x19, x20, [sp, #32]
0055 stp x21, x22, [sp, #48]
0056 stp x23, x24, [sp, #64]
0057 stp x25, x26, [sp, #80]
0058 stp x27, x28, [sp, #96]
0059
0060 // Set SVCR if we're doing SME
0061 cbz x1, 1f
0062 adrp x2, svcr_in
0063 ldr x2, [x2, :lo12:svcr_in]
0064 msr S3_3_C4_C2_2, x2
0065 1:
0066
0067 // Load ZA if it's enabled - uses x12 as scratch due to SME LDR
0068 tbz x2, #SVCR_ZA_SHIFT, 1f
0069 mov w12, #0
0070 ldr x2, =za_in
0071 2: _ldr_za 12, 2
0072 add x2, x2, x1
0073 add x12, x12, #1
0074 cmp x1, x12
0075 bne 2b
0076 1:
0077
0078 // Load GPRs x8-x28, and save our SP/FP for later comparison
0079 ldr x2, =gpr_in
0080 add x2, x2, #64
0081 ldp x8, x9, [x2], #16
0082 ldp x10, x11, [x2], #16
0083 ldp x12, x13, [x2], #16
0084 ldp x14, x15, [x2], #16
0085 ldp x16, x17, [x2], #16
0086 ldp x18, x19, [x2], #16
0087 ldp x20, x21, [x2], #16
0088 ldp x22, x23, [x2], #16
0089 ldp x24, x25, [x2], #16
0090 ldp x26, x27, [x2], #16
0091 ldr x28, [x2], #8
0092 str x29, [x2], #8 // FP
0093 str x30, [x2], #8 // LR
0094
0095 // Load FPRs if we're not doing SVE
0096 cbnz x0, 1f
0097 ldr x2, =fpr_in
0098 ldp q0, q1, [x2]
0099 ldp q2, q3, [x2, #16 * 2]
0100 ldp q4, q5, [x2, #16 * 4]
0101 ldp q6, q7, [x2, #16 * 6]
0102 ldp q8, q9, [x2, #16 * 8]
0103 ldp q10, q11, [x2, #16 * 10]
0104 ldp q12, q13, [x2, #16 * 12]
0105 ldp q14, q15, [x2, #16 * 14]
0106 ldp q16, q17, [x2, #16 * 16]
0107 ldp q18, q19, [x2, #16 * 18]
0108 ldp q20, q21, [x2, #16 * 20]
0109 ldp q22, q23, [x2, #16 * 22]
0110 ldp q24, q25, [x2, #16 * 24]
0111 ldp q26, q27, [x2, #16 * 26]
0112 ldp q28, q29, [x2, #16 * 28]
0113 ldp q30, q31, [x2, #16 * 30]
0114 1:
0115
0116 // Load the SVE registers if we're doing SVE/SME
0117 cbz x0, 1f
0118
0119 ldr x2, =z_in
0120 ldr z0, [x2, #0, MUL VL]
0121 ldr z1, [x2, #1, MUL VL]
0122 ldr z2, [x2, #2, MUL VL]
0123 ldr z3, [x2, #3, MUL VL]
0124 ldr z4, [x2, #4, MUL VL]
0125 ldr z5, [x2, #5, MUL VL]
0126 ldr z6, [x2, #6, MUL VL]
0127 ldr z7, [x2, #7, MUL VL]
0128 ldr z8, [x2, #8, MUL VL]
0129 ldr z9, [x2, #9, MUL VL]
0130 ldr z10, [x2, #10, MUL VL]
0131 ldr z11, [x2, #11, MUL VL]
0132 ldr z12, [x2, #12, MUL VL]
0133 ldr z13, [x2, #13, MUL VL]
0134 ldr z14, [x2, #14, MUL VL]
0135 ldr z15, [x2, #15, MUL VL]
0136 ldr z16, [x2, #16, MUL VL]
0137 ldr z17, [x2, #17, MUL VL]
0138 ldr z18, [x2, #18, MUL VL]
0139 ldr z19, [x2, #19, MUL VL]
0140 ldr z20, [x2, #20, MUL VL]
0141 ldr z21, [x2, #21, MUL VL]
0142 ldr z22, [x2, #22, MUL VL]
0143 ldr z23, [x2, #23, MUL VL]
0144 ldr z24, [x2, #24, MUL VL]
0145 ldr z25, [x2, #25, MUL VL]
0146 ldr z26, [x2, #26, MUL VL]
0147 ldr z27, [x2, #27, MUL VL]
0148 ldr z28, [x2, #28, MUL VL]
0149 ldr z29, [x2, #29, MUL VL]
0150 ldr z30, [x2, #30, MUL VL]
0151 ldr z31, [x2, #31, MUL VL]
0152
0153 // Only set a non-zero FFR, test patterns must be zero since the
0154 // syscall should clear it - this lets us handle FA64.
0155 ldr x2, =ffr_in
0156 ldr p0, [x2, #0]
0157 ldr x2, [x2, #0]
0158 cbz x2, 2f
0159 wrffr p0.b
0160 2:
0161
0162 ldr x2, =p_in
0163 ldr p0, [x2, #0, MUL VL]
0164 ldr p1, [x2, #1, MUL VL]
0165 ldr p2, [x2, #2, MUL VL]
0166 ldr p3, [x2, #3, MUL VL]
0167 ldr p4, [x2, #4, MUL VL]
0168 ldr p5, [x2, #5, MUL VL]
0169 ldr p6, [x2, #6, MUL VL]
0170 ldr p7, [x2, #7, MUL VL]
0171 ldr p8, [x2, #8, MUL VL]
0172 ldr p9, [x2, #9, MUL VL]
0173 ldr p10, [x2, #10, MUL VL]
0174 ldr p11, [x2, #11, MUL VL]
0175 ldr p12, [x2, #12, MUL VL]
0176 ldr p13, [x2, #13, MUL VL]
0177 ldr p14, [x2, #14, MUL VL]
0178 ldr p15, [x2, #15, MUL VL]
0179 1:
0180
0181 // Do the syscall
0182 svc #0
0183
0184 // Save GPRs x8-x30
0185 ldr x2, =gpr_out
0186 add x2, x2, #64
0187 stp x8, x9, [x2], #16
0188 stp x10, x11, [x2], #16
0189 stp x12, x13, [x2], #16
0190 stp x14, x15, [x2], #16
0191 stp x16, x17, [x2], #16
0192 stp x18, x19, [x2], #16
0193 stp x20, x21, [x2], #16
0194 stp x22, x23, [x2], #16
0195 stp x24, x25, [x2], #16
0196 stp x26, x27, [x2], #16
0197 stp x28, x29, [x2], #16
0198 str x30, [x2]
0199
0200 // Restore x0 and x1 for feature checks
0201 ldp x0, x1, [sp, #16]
0202
0203 // Save FPSIMD state
0204 ldr x2, =fpr_out
0205 stp q0, q1, [x2]
0206 stp q2, q3, [x2, #16 * 2]
0207 stp q4, q5, [x2, #16 * 4]
0208 stp q6, q7, [x2, #16 * 6]
0209 stp q8, q9, [x2, #16 * 8]
0210 stp q10, q11, [x2, #16 * 10]
0211 stp q12, q13, [x2, #16 * 12]
0212 stp q14, q15, [x2, #16 * 14]
0213 stp q16, q17, [x2, #16 * 16]
0214 stp q18, q19, [x2, #16 * 18]
0215 stp q20, q21, [x2, #16 * 20]
0216 stp q22, q23, [x2, #16 * 22]
0217 stp q24, q25, [x2, #16 * 24]
0218 stp q26, q27, [x2, #16 * 26]
0219 stp q28, q29, [x2, #16 * 28]
0220 stp q30, q31, [x2, #16 * 30]
0221
0222 // Save SVCR if we're doing SME
0223 cbz x1, 1f
0224 mrs x2, S3_3_C4_C2_2
0225 adrp x3, svcr_out
0226 str x2, [x3, :lo12:svcr_out]
0227 1:
0228
0229 // Save ZA if it's enabled - uses x12 as scratch due to SME STR
0230 tbz x2, #SVCR_ZA_SHIFT, 1f
0231 mov w12, #0
0232 ldr x2, =za_out
0233 2: _str_za 12, 2
0234 add x2, x2, x1
0235 add x12, x12, #1
0236 cmp x1, x12
0237 bne 2b
0238 1:
0239
0240 // Save the SVE state if we have some
0241 cbz x0, 1f
0242
0243 ldr x2, =z_out
0244 str z0, [x2, #0, MUL VL]
0245 str z1, [x2, #1, MUL VL]
0246 str z2, [x2, #2, MUL VL]
0247 str z3, [x2, #3, MUL VL]
0248 str z4, [x2, #4, MUL VL]
0249 str z5, [x2, #5, MUL VL]
0250 str z6, [x2, #6, MUL VL]
0251 str z7, [x2, #7, MUL VL]
0252 str z8, [x2, #8, MUL VL]
0253 str z9, [x2, #9, MUL VL]
0254 str z10, [x2, #10, MUL VL]
0255 str z11, [x2, #11, MUL VL]
0256 str z12, [x2, #12, MUL VL]
0257 str z13, [x2, #13, MUL VL]
0258 str z14, [x2, #14, MUL VL]
0259 str z15, [x2, #15, MUL VL]
0260 str z16, [x2, #16, MUL VL]
0261 str z17, [x2, #17, MUL VL]
0262 str z18, [x2, #18, MUL VL]
0263 str z19, [x2, #19, MUL VL]
0264 str z20, [x2, #20, MUL VL]
0265 str z21, [x2, #21, MUL VL]
0266 str z22, [x2, #22, MUL VL]
0267 str z23, [x2, #23, MUL VL]
0268 str z24, [x2, #24, MUL VL]
0269 str z25, [x2, #25, MUL VL]
0270 str z26, [x2, #26, MUL VL]
0271 str z27, [x2, #27, MUL VL]
0272 str z28, [x2, #28, MUL VL]
0273 str z29, [x2, #29, MUL VL]
0274 str z30, [x2, #30, MUL VL]
0275 str z31, [x2, #31, MUL VL]
0276
0277 ldr x2, =p_out
0278 str p0, [x2, #0, MUL VL]
0279 str p1, [x2, #1, MUL VL]
0280 str p2, [x2, #2, MUL VL]
0281 str p3, [x2, #3, MUL VL]
0282 str p4, [x2, #4, MUL VL]
0283 str p5, [x2, #5, MUL VL]
0284 str p6, [x2, #6, MUL VL]
0285 str p7, [x2, #7, MUL VL]
0286 str p8, [x2, #8, MUL VL]
0287 str p9, [x2, #9, MUL VL]
0288 str p10, [x2, #10, MUL VL]
0289 str p11, [x2, #11, MUL VL]
0290 str p12, [x2, #12, MUL VL]
0291 str p13, [x2, #13, MUL VL]
0292 str p14, [x2, #14, MUL VL]
0293 str p15, [x2, #15, MUL VL]
0294
0295 // Only save FFR if we wrote a value for SME
0296 ldr x2, =ffr_in
0297 ldr x2, [x2, #0]
0298 cbz x2, 1f
0299 ldr x2, =ffr_out
0300 rdffr p0.b
0301 str p0, [x2, #0]
0302 1:
0303
0304 // Restore callee saved registers x19-x30
0305 ldp x19, x20, [sp, #32]
0306 ldp x21, x22, [sp, #48]
0307 ldp x23, x24, [sp, #64]
0308 ldp x25, x26, [sp, #80]
0309 ldp x27, x28, [sp, #96]
0310 ldp x29, x30, [sp], #112
0311
0312 // Clear SVCR if we were doing SME so future tests don't have ZA
0313 cbz x1, 1f
0314 msr S3_3_C4_C2_2, xzr
0315 1:
0316
0317 ret
