util/arm-spe-decoder/arm-spe-pkt-decoder.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Arm Statistical Profiling Extensions (SPE) support
0004  * Copyright (c) 2017-2018, Arm Ltd.
0005  */
0006
0007 #ifndef INCLUDE__ARM_SPE_PKT_DECODER_H__
0008 #define INCLUDE__ARM_SPE_PKT_DECODER_H__
0009
0010 #include <stddef.h>
0011 #include <stdint.h>
0012
0013 #define ARM_SPE_PKT_DESC_MAX        256
0014
0015 #define ARM_SPE_NEED_MORE_BYTES     -1
0016 #define ARM_SPE_BAD_PACKET      -2
0017
0018 #define ARM_SPE_PKT_MAX_SZ      16
0019
0020 enum arm_spe_pkt_type {
0021     ARM_SPE_BAD,
0022     ARM_SPE_PAD,
0023     ARM_SPE_END,
0024     ARM_SPE_TIMESTAMP,
0025     ARM_SPE_ADDRESS,
0026     ARM_SPE_COUNTER,
0027     ARM_SPE_CONTEXT,
0028     ARM_SPE_OP_TYPE,
0029     ARM_SPE_EVENTS,
0030     ARM_SPE_DATA_SOURCE,
0031 };
0032
0033 struct arm_spe_pkt {
0034     enum arm_spe_pkt_type   type;
0035     unsigned char       index;
0036     uint64_t        payload;
0037 };
0038
0039 /* Short header (HEADER0) and extended header (HEADER1) */
0040 #define SPE_HEADER0_PAD             0x0
0041 #define SPE_HEADER0_END             0x1
0042 #define SPE_HEADER0_TIMESTAMP           0x71
0043 /* Mask for event & data source */
0044 #define SPE_HEADER0_MASK1           (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
0045 #define SPE_HEADER0_EVENTS          0x42
0046 #define SPE_HEADER0_SOURCE          0x43
0047 /* Mask for context & operation */
0048 #define SPE_HEADER0_MASK2           GENMASK_ULL(7, 2)
0049 #define SPE_HEADER0_CONTEXT         0x64
0050 #define SPE_HEADER0_OP_TYPE         0x48
0051 /* Mask for extended format */
0052 #define SPE_HEADER0_EXTENDED            0x20
0053 /* Mask for address & counter */
0054 #define SPE_HEADER0_MASK3           GENMASK_ULL(7, 3)
0055 #define SPE_HEADER0_ADDRESS         0xb0
0056 #define SPE_HEADER0_COUNTER         0x98
0057 #define SPE_HEADER1_ALIGNMENT           0x0
0058
0059 #define SPE_HDR_SHORT_INDEX(h)          ((h) & GENMASK_ULL(2, 0))
0060 #define SPE_HDR_EXTENDED_INDEX(h0, h1)      (((h0) & GENMASK_ULL(1, 0)) << 3 | \
0061                          SPE_HDR_SHORT_INDEX(h1))
0062
0063 /* Address packet header */
0064 #define SPE_ADDR_PKT_HDR_INDEX_INS      0x0
0065 #define SPE_ADDR_PKT_HDR_INDEX_BRANCH       0x1
0066 #define SPE_ADDR_PKT_HDR_INDEX_DATA_VIRT    0x2
0067 #define SPE_ADDR_PKT_HDR_INDEX_DATA_PHYS    0x3
0068
0069 /* Address packet payload */
0070 #define SPE_ADDR_PKT_ADDR_BYTE7_SHIFT       56
0071 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v)  ((v) & GENMASK_ULL(55, 0))
0072 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v)     (((v) & GENMASK_ULL(55, 48)) >> 48)
0073
0074 #define SPE_ADDR_PKT_GET_NS(v)          (((v) & BIT_ULL(63)) >> 63)
0075 #define SPE_ADDR_PKT_GET_EL(v)          (((v) & GENMASK_ULL(62, 61)) >> 61)
0076 #define SPE_ADDR_PKT_GET_CH(v)          (((v) & BIT_ULL(62)) >> 62)
0077 #define SPE_ADDR_PKT_GET_PAT(v)         (((v) & GENMASK_ULL(59, 56)) >> 56)
0078
0079 #define SPE_ADDR_PKT_EL0            0
0080 #define SPE_ADDR_PKT_EL1            1
0081 #define SPE_ADDR_PKT_EL2            2
0082 #define SPE_ADDR_PKT_EL3            3
0083
0084 /* Context packet header */
0085 #define SPE_CTX_PKT_HDR_INDEX(h)        ((h) & GENMASK_ULL(1, 0))
0086
0087 /* Counter packet header */
0088 #define SPE_CNT_PKT_HDR_INDEX_TOTAL_LAT     0x0
0089 #define SPE_CNT_PKT_HDR_INDEX_ISSUE_LAT     0x1
0090 #define SPE_CNT_PKT_HDR_INDEX_TRANS_LAT     0x2
0091
0092 /* Event packet payload */
0093 enum arm_spe_events {
0094     EV_EXCEPTION_GEN    = 0,
0095     EV_RETIRED      = 1,
0096     EV_L1D_ACCESS       = 2,
0097     EV_L1D_REFILL       = 3,
0098     EV_TLB_ACCESS       = 4,
0099     EV_TLB_WALK     = 5,
0100     EV_NOT_TAKEN        = 6,
0101     EV_MISPRED      = 7,
0102     EV_LLC_ACCESS       = 8,
0103     EV_LLC_MISS     = 9,
0104     EV_REMOTE_ACCESS    = 10,
0105     EV_ALIGNMENT        = 11,
0106     EV_PARTIAL_PREDICATE    = 17,
0107     EV_EMPTY_PREDICATE  = 18,
0108 };
0109
0110 /* Operation packet header */
0111 #define SPE_OP_PKT_HDR_CLASS(h)         ((h) & GENMASK_ULL(1, 0))
0112 #define SPE_OP_PKT_HDR_CLASS_OTHER      0x0
0113 #define SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC   0x1
0114 #define SPE_OP_PKT_HDR_CLASS_BR_ERET        0x2
0115
0116 #define SPE_OP_PKT_IS_OTHER_SVE_OP(v)       (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
0117
0118 #define SPE_OP_PKT_COND             BIT(0)
0119
0120 #define SPE_OP_PKT_LDST_SUBCLASS_GET(v)     ((v) & GENMASK_ULL(7, 1))
0121 #define SPE_OP_PKT_LDST_SUBCLASS_GP_REG     0x0
0122 #define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP    0x4
0123 #define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG 0x10
0124 #define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG  0x30
0125
0126 #define SPE_OP_PKT_IS_LDST_ATOMIC(v)        (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)
0127
0128 #define SPE_OP_PKT_AR               BIT(4)
0129 #define SPE_OP_PKT_EXCL             BIT(3)
0130 #define SPE_OP_PKT_AT               BIT(2)
0131 #define SPE_OP_PKT_ST               BIT(0)
0132
0133 #define SPE_OP_PKT_IS_LDST_SVE(v)       (((v) & (BIT(3) | BIT(1))) == 0x8)
0134
0135 #define SPE_OP_PKT_SVE_SG           BIT(7)
0136 /*
0137  * SVE effective vector length (EVL) is stored in byte 0 bits [6:4];
0138  * the length is rounded up to a power of two and use 32 as one step,
0139  * so EVL calculation is:
0140  *
0141  *   32 * (2 ^ bits [6:4]) = 32 << (bits [6:4])
0142  */
0143 #define SPE_OP_PKG_SVE_EVL(v)           (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))
0144 #define SPE_OP_PKT_SVE_PRED         BIT(2)
0145 #define SPE_OP_PKT_SVE_FP           BIT(1)
0146
0147 #define SPE_OP_PKT_IS_INDIRECT_BRANCH(v)    (((v) & GENMASK_ULL(7, 1)) == 0x2)
0148
0149 const char *arm_spe_pkt_name(enum arm_spe_pkt_type);
0150
0151 int arm_spe_get_packet(const unsigned char *buf, size_t len,
0152                struct arm_spe_pkt *packet);
0153
0154 int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, size_t len);
0155 #endif