0001 [
0002 {
0003 "BriefDescription": "DTLB load misses",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0x8",
0006 "EventName": "DTLB_LOAD_MISSES.ANY",
0007 "SampleAfterValue": "200000",
0008 "UMask": "0x1"
0009 },
0010 {
0011 "BriefDescription": "DTLB load miss large page walks",
0012 "Counter": "0,1,2,3",
0013 "EventCode": "0x8",
0014 "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
0015 "SampleAfterValue": "200000",
0016 "UMask": "0x80"
0017 },
0018 {
0019 "BriefDescription": "DTLB load miss caused by low part of address",
0020 "Counter": "0,1,2,3",
0021 "EventCode": "0x8",
0022 "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
0023 "SampleAfterValue": "200000",
0024 "UMask": "0x20"
0025 },
0026 {
0027 "BriefDescription": "DTLB second level hit",
0028 "Counter": "0,1,2,3",
0029 "EventCode": "0x8",
0030 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
0031 "SampleAfterValue": "2000000",
0032 "UMask": "0x10"
0033 },
0034 {
0035 "BriefDescription": "DTLB load miss page walks complete",
0036 "Counter": "0,1,2,3",
0037 "EventCode": "0x8",
0038 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0039 "SampleAfterValue": "200000",
0040 "UMask": "0x2"
0041 },
0042 {
0043 "BriefDescription": "DTLB load miss page walk cycles",
0044 "Counter": "0,1,2,3",
0045 "EventCode": "0x8",
0046 "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
0047 "SampleAfterValue": "200000",
0048 "UMask": "0x4"
0049 },
0050 {
0051 "BriefDescription": "DTLB misses",
0052 "Counter": "0,1,2,3",
0053 "EventCode": "0x49",
0054 "EventName": "DTLB_MISSES.ANY",
0055 "SampleAfterValue": "200000",
0056 "UMask": "0x1"
0057 },
0058 {
0059 "BriefDescription": "DTLB miss large page walks",
0060 "Counter": "0,1,2,3",
0061 "EventCode": "0x49",
0062 "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
0063 "SampleAfterValue": "200000",
0064 "UMask": "0x80"
0065 },
0066 {
0067 "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
0068 "Counter": "0,1,2,3",
0069 "EventCode": "0x49",
0070 "EventName": "DTLB_MISSES.PDE_MISS",
0071 "SampleAfterValue": "200000",
0072 "UMask": "0x20"
0073 },
0074 {
0075 "BriefDescription": "DTLB first level misses but second level hit",
0076 "Counter": "0,1,2,3",
0077 "EventCode": "0x49",
0078 "EventName": "DTLB_MISSES.STLB_HIT",
0079 "SampleAfterValue": "200000",
0080 "UMask": "0x10"
0081 },
0082 {
0083 "BriefDescription": "DTLB miss page walks",
0084 "Counter": "0,1,2,3",
0085 "EventCode": "0x49",
0086 "EventName": "DTLB_MISSES.WALK_COMPLETED",
0087 "SampleAfterValue": "200000",
0088 "UMask": "0x2"
0089 },
0090 {
0091 "BriefDescription": "DTLB miss page walk cycles",
0092 "Counter": "0,1,2,3",
0093 "EventCode": "0x49",
0094 "EventName": "DTLB_MISSES.WALK_CYCLES",
0095 "SampleAfterValue": "2000000",
0096 "UMask": "0x4"
0097 },
0098 {
0099 "BriefDescription": "Extended Page Table walk cycles",
0100 "Counter": "0,1,2,3",
0101 "EventCode": "0x4F",
0102 "EventName": "EPT.WALK_CYCLES",
0103 "SampleAfterValue": "2000000",
0104 "UMask": "0x10"
0105 },
0106 {
0107 "BriefDescription": "ITLB flushes",
0108 "Counter": "0,1,2,3",
0109 "EventCode": "0xAE",
0110 "EventName": "ITLB_FLUSH",
0111 "SampleAfterValue": "2000000",
0112 "UMask": "0x1"
0113 },
0114 {
0115 "BriefDescription": "ITLB miss",
0116 "Counter": "0,1,2,3",
0117 "EventCode": "0x85",
0118 "EventName": "ITLB_MISSES.ANY",
0119 "SampleAfterValue": "200000",
0120 "UMask": "0x1"
0121 },
0122 {
0123 "BriefDescription": "ITLB miss large page walks",
0124 "Counter": "0,1,2,3",
0125 "EventCode": "0x85",
0126 "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
0127 "SampleAfterValue": "200000",
0128 "UMask": "0x80"
0129 },
0130 {
0131 "BriefDescription": "ITLB miss page walks",
0132 "Counter": "0,1,2,3",
0133 "EventCode": "0x85",
0134 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0135 "SampleAfterValue": "200000",
0136 "UMask": "0x2"
0137 },
0138 {
0139 "BriefDescription": "ITLB miss page walk cycles",
0140 "Counter": "0,1,2,3",
0141 "EventCode": "0x85",
0142 "EventName": "ITLB_MISSES.WALK_CYCLES",
0143 "SampleAfterValue": "2000000",
0144 "UMask": "0x4"
0145 },
0146 {
0147 "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
0148 "Counter": "0,1,2,3",
0149 "EventCode": "0xC8",
0150 "EventName": "ITLB_MISS_RETIRED",
0151 "PEBS": "1",
0152 "SampleAfterValue": "200000",
0153 "UMask": "0x20"
0154 },
0155 {
0156 "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
0157 "Counter": "0,1,2,3",
0158 "EventCode": "0xCB",
0159 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
0160 "PEBS": "1",
0161 "SampleAfterValue": "200000",
0162 "UMask": "0x80"
0163 },
0164 {
0165 "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
0166 "Counter": "0,1,2,3",
0167 "EventCode": "0xC",
0168 "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
0169 "PEBS": "1",
0170 "SampleAfterValue": "200000",
0171 "UMask": "0x1"
0172 }
0173 ]
