0001 [
0002 {
0003 "BriefDescription": "Cycles the divider is busy",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0x14",
0006 "EventName": "ARITH.CYCLES_DIV_BUSY",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0x1"
0009 },
0010 {
0011 "BriefDescription": "Divide Operations executed",
0012 "Counter": "0,1,2,3",
0013 "CounterMask": "1",
0014 "EdgeDetect": "1",
0015 "EventCode": "0x14",
0016 "EventName": "ARITH.DIV",
0017 "Invert": "1",
0018 "SampleAfterValue": "2000000",
0019 "UMask": "0x1"
0020 },
0021 {
0022 "BriefDescription": "Multiply operations executed",
0023 "Counter": "0,1,2,3",
0024 "EventCode": "0x14",
0025 "EventName": "ARITH.MUL",
0026 "SampleAfterValue": "2000000",
0027 "UMask": "0x2"
0028 },
0029 {
0030 "BriefDescription": "BACLEAR asserted with bad target address",
0031 "Counter": "0,1,2,3",
0032 "EventCode": "0xE6",
0033 "EventName": "BACLEAR.BAD_TARGET",
0034 "SampleAfterValue": "2000000",
0035 "UMask": "0x2"
0036 },
0037 {
0038 "BriefDescription": "BACLEAR asserted, regardless of cause",
0039 "Counter": "0,1,2,3",
0040 "EventCode": "0xE6",
0041 "EventName": "BACLEAR.CLEAR",
0042 "SampleAfterValue": "2000000",
0043 "UMask": "0x1"
0044 },
0045 {
0046 "BriefDescription": "Instruction queue forced BACLEAR",
0047 "Counter": "0,1,2,3",
0048 "EventCode": "0xA7",
0049 "EventName": "BACLEAR_FORCE_IQ",
0050 "SampleAfterValue": "2000000",
0051 "UMask": "0x1"
0052 },
0053 {
0054 "BriefDescription": "Early Branch Prediciton Unit clears",
0055 "Counter": "0,1,2,3",
0056 "EventCode": "0xE8",
0057 "EventName": "BPU_CLEARS.EARLY",
0058 "SampleAfterValue": "2000000",
0059 "UMask": "0x1"
0060 },
0061 {
0062 "BriefDescription": "Late Branch Prediction Unit clears",
0063 "Counter": "0,1,2,3",
0064 "EventCode": "0xE8",
0065 "EventName": "BPU_CLEARS.LATE",
0066 "SampleAfterValue": "2000000",
0067 "UMask": "0x2"
0068 },
0069 {
0070 "BriefDescription": "Branch prediction unit missed call or return",
0071 "Counter": "0,1,2,3",
0072 "EventCode": "0xE5",
0073 "EventName": "BPU_MISSED_CALL_RET",
0074 "SampleAfterValue": "2000000",
0075 "UMask": "0x1"
0076 },
0077 {
0078 "BriefDescription": "Branch instructions decoded",
0079 "Counter": "0,1,2,3",
0080 "EventCode": "0xE0",
0081 "EventName": "BR_INST_DECODED",
0082 "SampleAfterValue": "2000000",
0083 "UMask": "0x1"
0084 },
0085 {
0086 "BriefDescription": "Branch instructions executed",
0087 "Counter": "0,1,2,3",
0088 "EventCode": "0x88",
0089 "EventName": "BR_INST_EXEC.ANY",
0090 "SampleAfterValue": "200000",
0091 "UMask": "0x7f"
0092 },
0093 {
0094 "BriefDescription": "Conditional branch instructions executed",
0095 "Counter": "0,1,2,3",
0096 "EventCode": "0x88",
0097 "EventName": "BR_INST_EXEC.COND",
0098 "SampleAfterValue": "200000",
0099 "UMask": "0x1"
0100 },
0101 {
0102 "BriefDescription": "Unconditional branches executed",
0103 "Counter": "0,1,2,3",
0104 "EventCode": "0x88",
0105 "EventName": "BR_INST_EXEC.DIRECT",
0106 "SampleAfterValue": "200000",
0107 "UMask": "0x2"
0108 },
0109 {
0110 "BriefDescription": "Unconditional call branches executed",
0111 "Counter": "0,1,2,3",
0112 "EventCode": "0x88",
0113 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
0114 "SampleAfterValue": "20000",
0115 "UMask": "0x10"
0116 },
0117 {
0118 "BriefDescription": "Indirect call branches executed",
0119 "Counter": "0,1,2,3",
0120 "EventCode": "0x88",
0121 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
0122 "SampleAfterValue": "20000",
0123 "UMask": "0x20"
0124 },
0125 {
0126 "BriefDescription": "Indirect non call branches executed",
0127 "Counter": "0,1,2,3",
0128 "EventCode": "0x88",
0129 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
0130 "SampleAfterValue": "20000",
0131 "UMask": "0x4"
0132 },
0133 {
0134 "BriefDescription": "Call branches executed",
0135 "Counter": "0,1,2,3",
0136 "EventCode": "0x88",
0137 "EventName": "BR_INST_EXEC.NEAR_CALLS",
0138 "SampleAfterValue": "20000",
0139 "UMask": "0x30"
0140 },
0141 {
0142 "BriefDescription": "All non call branches executed",
0143 "Counter": "0,1,2,3",
0144 "EventCode": "0x88",
0145 "EventName": "BR_INST_EXEC.NON_CALLS",
0146 "SampleAfterValue": "200000",
0147 "UMask": "0x7"
0148 },
0149 {
0150 "BriefDescription": "Indirect return branches executed",
0151 "Counter": "0,1,2,3",
0152 "EventCode": "0x88",
0153 "EventName": "BR_INST_EXEC.RETURN_NEAR",
0154 "SampleAfterValue": "20000",
0155 "UMask": "0x8"
0156 },
0157 {
0158 "BriefDescription": "Taken branches executed",
0159 "Counter": "0,1,2,3",
0160 "EventCode": "0x88",
0161 "EventName": "BR_INST_EXEC.TAKEN",
0162 "SampleAfterValue": "200000",
0163 "UMask": "0x40"
0164 },
0165 {
0166 "BriefDescription": "Retired branch instructions (Precise Event)",
0167 "Counter": "0,1,2,3",
0168 "EventCode": "0xC4",
0169 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
0170 "PEBS": "1",
0171 "SampleAfterValue": "200000",
0172 "UMask": "0x4"
0173 },
0174 {
0175 "BriefDescription": "Retired conditional branch instructions (Precise Event)",
0176 "Counter": "0,1,2,3",
0177 "EventCode": "0xC4",
0178 "EventName": "BR_INST_RETIRED.CONDITIONAL",
0179 "PEBS": "1",
0180 "SampleAfterValue": "200000",
0181 "UMask": "0x1"
0182 },
0183 {
0184 "BriefDescription": "Retired near call instructions (Precise Event)",
0185 "Counter": "0,1,2,3",
0186 "EventCode": "0xC4",
0187 "EventName": "BR_INST_RETIRED.NEAR_CALL",
0188 "PEBS": "1",
0189 "SampleAfterValue": "20000",
0190 "UMask": "0x2"
0191 },
0192 {
0193 "BriefDescription": "Mispredicted branches executed",
0194 "Counter": "0,1,2,3",
0195 "EventCode": "0x89",
0196 "EventName": "BR_MISP_EXEC.ANY",
0197 "SampleAfterValue": "20000",
0198 "UMask": "0x7f"
0199 },
0200 {
0201 "BriefDescription": "Mispredicted conditional branches executed",
0202 "Counter": "0,1,2,3",
0203 "EventCode": "0x89",
0204 "EventName": "BR_MISP_EXEC.COND",
0205 "SampleAfterValue": "20000",
0206 "UMask": "0x1"
0207 },
0208 {
0209 "BriefDescription": "Mispredicted unconditional branches executed",
0210 "Counter": "0,1,2,3",
0211 "EventCode": "0x89",
0212 "EventName": "BR_MISP_EXEC.DIRECT",
0213 "SampleAfterValue": "20000",
0214 "UMask": "0x2"
0215 },
0216 {
0217 "BriefDescription": "Mispredicted non call branches executed",
0218 "Counter": "0,1,2,3",
0219 "EventCode": "0x89",
0220 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
0221 "SampleAfterValue": "2000",
0222 "UMask": "0x10"
0223 },
0224 {
0225 "BriefDescription": "Mispredicted indirect call branches executed",
0226 "Counter": "0,1,2,3",
0227 "EventCode": "0x89",
0228 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
0229 "SampleAfterValue": "2000",
0230 "UMask": "0x20"
0231 },
0232 {
0233 "BriefDescription": "Mispredicted indirect non call branches executed",
0234 "Counter": "0,1,2,3",
0235 "EventCode": "0x89",
0236 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
0237 "SampleAfterValue": "2000",
0238 "UMask": "0x4"
0239 },
0240 {
0241 "BriefDescription": "Mispredicted call branches executed",
0242 "Counter": "0,1,2,3",
0243 "EventCode": "0x89",
0244 "EventName": "BR_MISP_EXEC.NEAR_CALLS",
0245 "SampleAfterValue": "2000",
0246 "UMask": "0x30"
0247 },
0248 {
0249 "BriefDescription": "Mispredicted non call branches executed",
0250 "Counter": "0,1,2,3",
0251 "EventCode": "0x89",
0252 "EventName": "BR_MISP_EXEC.NON_CALLS",
0253 "SampleAfterValue": "20000",
0254 "UMask": "0x7"
0255 },
0256 {
0257 "BriefDescription": "Mispredicted return branches executed",
0258 "Counter": "0,1,2,3",
0259 "EventCode": "0x89",
0260 "EventName": "BR_MISP_EXEC.RETURN_NEAR",
0261 "SampleAfterValue": "2000",
0262 "UMask": "0x8"
0263 },
0264 {
0265 "BriefDescription": "Mispredicted taken branches executed",
0266 "Counter": "0,1,2,3",
0267 "EventCode": "0x89",
0268 "EventName": "BR_MISP_EXEC.TAKEN",
0269 "SampleAfterValue": "20000",
0270 "UMask": "0x40"
0271 },
0272 {
0273 "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
0274 "Counter": "0,1,2,3",
0275 "EventCode": "0xC5",
0276 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
0277 "PEBS": "1",
0278 "SampleAfterValue": "20000",
0279 "UMask": "0x4"
0280 },
0281 {
0282 "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
0283 "Counter": "0,1,2,3",
0284 "EventCode": "0xC5",
0285 "EventName": "BR_MISP_RETIRED.CONDITIONAL",
0286 "PEBS": "1",
0287 "SampleAfterValue": "20000",
0288 "UMask": "0x1"
0289 },
0290 {
0291 "BriefDescription": "Mispredicted near retired calls (Precise Event)",
0292 "Counter": "0,1,2,3",
0293 "EventCode": "0xC5",
0294 "EventName": "BR_MISP_RETIRED.NEAR_CALL",
0295 "PEBS": "1",
0296 "SampleAfterValue": "2000",
0297 "UMask": "0x2"
0298 },
0299 {
0300 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
0301 "Counter": "Fixed counter 3",
0302 "EventCode": "0x0",
0303 "EventName": "CPU_CLK_UNHALTED.REF",
0304 "SampleAfterValue": "2000000",
0305 "UMask": "0x0"
0306 },
0307 {
0308 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
0309 "Counter": "0,1,2,3",
0310 "EventCode": "0x3C",
0311 "EventName": "CPU_CLK_UNHALTED.REF_P",
0312 "SampleAfterValue": "100000",
0313 "UMask": "0x1"
0314 },
0315 {
0316 "BriefDescription": "Cycles when thread is not halted (fixed counter)",
0317 "Counter": "Fixed counter 2",
0318 "EventCode": "0x0",
0319 "EventName": "CPU_CLK_UNHALTED.THREAD",
0320 "SampleAfterValue": "2000000",
0321 "UMask": "0x0"
0322 },
0323 {
0324 "BriefDescription": "Cycles when thread is not halted (programmable counter)",
0325 "Counter": "0,1,2,3",
0326 "EventCode": "0x3C",
0327 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
0328 "SampleAfterValue": "2000000",
0329 "UMask": "0x0"
0330 },
0331 {
0332 "BriefDescription": "Total CPU cycles",
0333 "Counter": "0,1,2,3",
0334 "CounterMask": "2",
0335 "EventCode": "0x3C",
0336 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
0337 "Invert": "1",
0338 "SampleAfterValue": "2000000",
0339 "UMask": "0x0"
0340 },
0341 {
0342 "BriefDescription": "Any Instruction Length Decoder stall cycles",
0343 "Counter": "0,1,2,3",
0344 "EventCode": "0x87",
0345 "EventName": "ILD_STALL.ANY",
0346 "SampleAfterValue": "2000000",
0347 "UMask": "0xf"
0348 },
0349 {
0350 "BriefDescription": "Instruction Queue full stall cycles",
0351 "Counter": "0,1,2,3",
0352 "EventCode": "0x87",
0353 "EventName": "ILD_STALL.IQ_FULL",
0354 "SampleAfterValue": "2000000",
0355 "UMask": "0x4"
0356 },
0357 {
0358 "BriefDescription": "Length Change Prefix stall cycles",
0359 "Counter": "0,1,2,3",
0360 "EventCode": "0x87",
0361 "EventName": "ILD_STALL.LCP",
0362 "SampleAfterValue": "2000000",
0363 "UMask": "0x1"
0364 },
0365 {
0366 "BriefDescription": "Stall cycles due to BPU MRU bypass",
0367 "Counter": "0,1,2,3",
0368 "EventCode": "0x87",
0369 "EventName": "ILD_STALL.MRU",
0370 "SampleAfterValue": "2000000",
0371 "UMask": "0x2"
0372 },
0373 {
0374 "BriefDescription": "Regen stall cycles",
0375 "Counter": "0,1,2,3",
0376 "EventCode": "0x87",
0377 "EventName": "ILD_STALL.REGEN",
0378 "SampleAfterValue": "2000000",
0379 "UMask": "0x8"
0380 },
0381 {
0382 "BriefDescription": "Instructions that must be decoded by decoder 0",
0383 "Counter": "0,1,2,3",
0384 "EventCode": "0x18",
0385 "EventName": "INST_DECODED.DEC0",
0386 "SampleAfterValue": "2000000",
0387 "UMask": "0x1"
0388 },
0389 {
0390 "BriefDescription": "Instructions written to instruction queue.",
0391 "Counter": "0,1,2,3",
0392 "EventCode": "0x17",
0393 "EventName": "INST_QUEUE_WRITES",
0394 "SampleAfterValue": "2000000",
0395 "UMask": "0x1"
0396 },
0397 {
0398 "BriefDescription": "Cycles instructions are written to the instruction queue",
0399 "Counter": "0,1,2,3",
0400 "EventCode": "0x1E",
0401 "EventName": "INST_QUEUE_WRITE_CYCLES",
0402 "SampleAfterValue": "2000000",
0403 "UMask": "0x1"
0404 },
0405 {
0406 "BriefDescription": "Instructions retired (fixed counter)",
0407 "Counter": "Fixed counter 1",
0408 "EventCode": "0x0",
0409 "EventName": "INST_RETIRED.ANY",
0410 "SampleAfterValue": "2000000",
0411 "UMask": "0x0"
0412 },
0413 {
0414 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
0415 "Counter": "0,1,2,3",
0416 "EventCode": "0xC0",
0417 "EventName": "INST_RETIRED.ANY_P",
0418 "PEBS": "1",
0419 "SampleAfterValue": "2000000",
0420 "UMask": "0x1"
0421 },
0422 {
0423 "BriefDescription": "Retired MMX instructions (Precise Event)",
0424 "Counter": "0,1,2,3",
0425 "EventCode": "0xC0",
0426 "EventName": "INST_RETIRED.MMX",
0427 "PEBS": "1",
0428 "SampleAfterValue": "2000000",
0429 "UMask": "0x4"
0430 },
0431 {
0432 "BriefDescription": "Total cycles (Precise Event)",
0433 "Counter": "0,1,2,3",
0434 "CounterMask": "16",
0435 "EventCode": "0xC0",
0436 "EventName": "INST_RETIRED.TOTAL_CYCLES",
0437 "Invert": "1",
0438 "PEBS": "1",
0439 "SampleAfterValue": "2000000",
0440 "UMask": "0x1"
0441 },
0442 {
0443 "BriefDescription": "Total cycles (Precise Event)",
0444 "Counter": "0,1,2,3",
0445 "CounterMask": "16",
0446 "EventCode": "0xC0",
0447 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
0448 "Invert": "1",
0449 "PEBS": "2",
0450 "SampleAfterValue": "2000000",
0451 "UMask": "0x1"
0452 },
0453 {
0454 "BriefDescription": "Retired floating-point operations (Precise Event)",
0455 "Counter": "0,1,2,3",
0456 "EventCode": "0xC0",
0457 "EventName": "INST_RETIRED.X87",
0458 "PEBS": "1",
0459 "SampleAfterValue": "2000000",
0460 "UMask": "0x2"
0461 },
0462 {
0463 "BriefDescription": "Load operations conflicting with software prefetches",
0464 "Counter": "0,1",
0465 "EventCode": "0x4C",
0466 "EventName": "LOAD_HIT_PRE",
0467 "SampleAfterValue": "200000",
0468 "UMask": "0x1"
0469 },
0470 {
0471 "BriefDescription": "Cycles when uops were delivered by the LSD",
0472 "Counter": "0,1,2,3",
0473 "CounterMask": "1",
0474 "EventCode": "0xA8",
0475 "EventName": "LSD.ACTIVE",
0476 "SampleAfterValue": "2000000",
0477 "UMask": "0x1"
0478 },
0479 {
0480 "BriefDescription": "Cycles no uops were delivered by the LSD",
0481 "Counter": "0,1,2,3",
0482 "CounterMask": "1",
0483 "EventCode": "0xA8",
0484 "EventName": "LSD.INACTIVE",
0485 "Invert": "1",
0486 "SampleAfterValue": "2000000",
0487 "UMask": "0x1"
0488 },
0489 {
0490 "BriefDescription": "Loops that can't stream from the instruction queue",
0491 "Counter": "0,1,2,3",
0492 "EventCode": "0x20",
0493 "EventName": "LSD_OVERFLOW",
0494 "SampleAfterValue": "2000000",
0495 "UMask": "0x1"
0496 },
0497 {
0498 "BriefDescription": "Cycles machine clear asserted",
0499 "Counter": "0,1,2,3",
0500 "EventCode": "0xC3",
0501 "EventName": "MACHINE_CLEARS.CYCLES",
0502 "SampleAfterValue": "20000",
0503 "UMask": "0x1"
0504 },
0505 {
0506 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
0507 "Counter": "0,1,2,3",
0508 "EventCode": "0xC3",
0509 "EventName": "MACHINE_CLEARS.MEM_ORDER",
0510 "SampleAfterValue": "20000",
0511 "UMask": "0x2"
0512 },
0513 {
0514 "BriefDescription": "Self-Modifying Code detected",
0515 "Counter": "0,1,2,3",
0516 "EventCode": "0xC3",
0517 "EventName": "MACHINE_CLEARS.SMC",
0518 "SampleAfterValue": "20000",
0519 "UMask": "0x4"
0520 },
0521 {
0522 "BriefDescription": "All RAT stall cycles",
0523 "Counter": "0,1,2,3",
0524 "EventCode": "0xD2",
0525 "EventName": "RAT_STALLS.ANY",
0526 "SampleAfterValue": "2000000",
0527 "UMask": "0xf"
0528 },
0529 {
0530 "BriefDescription": "Flag stall cycles",
0531 "Counter": "0,1,2,3",
0532 "EventCode": "0xD2",
0533 "EventName": "RAT_STALLS.FLAGS",
0534 "SampleAfterValue": "2000000",
0535 "UMask": "0x1"
0536 },
0537 {
0538 "BriefDescription": "Partial register stall cycles",
0539 "Counter": "0,1,2,3",
0540 "EventCode": "0xD2",
0541 "EventName": "RAT_STALLS.REGISTERS",
0542 "SampleAfterValue": "2000000",
0543 "UMask": "0x2"
0544 },
0545 {
0546 "BriefDescription": "ROB read port stalls cycles",
0547 "Counter": "0,1,2,3",
0548 "EventCode": "0xD2",
0549 "EventName": "RAT_STALLS.ROB_READ_PORT",
0550 "SampleAfterValue": "2000000",
0551 "UMask": "0x4"
0552 },
0553 {
0554 "BriefDescription": "Scoreboard stall cycles",
0555 "Counter": "0,1,2,3",
0556 "EventCode": "0xD2",
0557 "EventName": "RAT_STALLS.SCOREBOARD",
0558 "SampleAfterValue": "2000000",
0559 "UMask": "0x8"
0560 },
0561 {
0562 "BriefDescription": "Resource related stall cycles",
0563 "Counter": "0,1,2,3",
0564 "EventCode": "0xA2",
0565 "EventName": "RESOURCE_STALLS.ANY",
0566 "SampleAfterValue": "2000000",
0567 "UMask": "0x1"
0568 },
0569 {
0570 "BriefDescription": "FPU control word write stall cycles",
0571 "Counter": "0,1,2,3",
0572 "EventCode": "0xA2",
0573 "EventName": "RESOURCE_STALLS.FPCW",
0574 "SampleAfterValue": "2000000",
0575 "UMask": "0x20"
0576 },
0577 {
0578 "BriefDescription": "Load buffer stall cycles",
0579 "Counter": "0,1,2,3",
0580 "EventCode": "0xA2",
0581 "EventName": "RESOURCE_STALLS.LOAD",
0582 "SampleAfterValue": "2000000",
0583 "UMask": "0x2"
0584 },
0585 {
0586 "BriefDescription": "MXCSR rename stall cycles",
0587 "Counter": "0,1,2,3",
0588 "EventCode": "0xA2",
0589 "EventName": "RESOURCE_STALLS.MXCSR",
0590 "SampleAfterValue": "2000000",
0591 "UMask": "0x40"
0592 },
0593 {
0594 "BriefDescription": "Other Resource related stall cycles",
0595 "Counter": "0,1,2,3",
0596 "EventCode": "0xA2",
0597 "EventName": "RESOURCE_STALLS.OTHER",
0598 "SampleAfterValue": "2000000",
0599 "UMask": "0x80"
0600 },
0601 {
0602 "BriefDescription": "ROB full stall cycles",
0603 "Counter": "0,1,2,3",
0604 "EventCode": "0xA2",
0605 "EventName": "RESOURCE_STALLS.ROB_FULL",
0606 "SampleAfterValue": "2000000",
0607 "UMask": "0x10"
0608 },
0609 {
0610 "BriefDescription": "Reservation Station full stall cycles",
0611 "Counter": "0,1,2,3",
0612 "EventCode": "0xA2",
0613 "EventName": "RESOURCE_STALLS.RS_FULL",
0614 "SampleAfterValue": "2000000",
0615 "UMask": "0x4"
0616 },
0617 {
0618 "BriefDescription": "Store buffer stall cycles",
0619 "Counter": "0,1,2,3",
0620 "EventCode": "0xA2",
0621 "EventName": "RESOURCE_STALLS.STORE",
0622 "SampleAfterValue": "2000000",
0623 "UMask": "0x8"
0624 },
0625 {
0626 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
0627 "Counter": "0,1,2,3",
0628 "EventCode": "0xC7",
0629 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
0630 "PEBS": "1",
0631 "SampleAfterValue": "200000",
0632 "UMask": "0x4"
0633 },
0634 {
0635 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
0636 "Counter": "0,1,2,3",
0637 "EventCode": "0xC7",
0638 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
0639 "PEBS": "1",
0640 "SampleAfterValue": "200000",
0641 "UMask": "0x1"
0642 },
0643 {
0644 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
0645 "Counter": "0,1,2,3",
0646 "EventCode": "0xC7",
0647 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
0648 "PEBS": "1",
0649 "SampleAfterValue": "200000",
0650 "UMask": "0x8"
0651 },
0652 {
0653 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
0654 "Counter": "0,1,2,3",
0655 "EventCode": "0xC7",
0656 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
0657 "PEBS": "1",
0658 "SampleAfterValue": "200000",
0659 "UMask": "0x2"
0660 },
0661 {
0662 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
0663 "Counter": "0,1,2,3",
0664 "EventCode": "0xC7",
0665 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
0666 "PEBS": "1",
0667 "SampleAfterValue": "200000",
0668 "UMask": "0x10"
0669 },
0670 {
0671 "BriefDescription": "Stack pointer instructions decoded",
0672 "Counter": "0,1,2,3",
0673 "EventCode": "0xD1",
0674 "EventName": "UOPS_DECODED.ESP_FOLDING",
0675 "SampleAfterValue": "2000000",
0676 "UMask": "0x4"
0677 },
0678 {
0679 "BriefDescription": "Stack pointer sync operations",
0680 "Counter": "0,1,2,3",
0681 "EventCode": "0xD1",
0682 "EventName": "UOPS_DECODED.ESP_SYNC",
0683 "SampleAfterValue": "2000000",
0684 "UMask": "0x8"
0685 },
0686 {
0687 "BriefDescription": "Uops decoded by Microcode Sequencer",
0688 "Counter": "0,1,2,3",
0689 "CounterMask": "1",
0690 "EventCode": "0xD1",
0691 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
0692 "SampleAfterValue": "2000000",
0693 "UMask": "0x2"
0694 },
0695 {
0696 "BriefDescription": "Cycles no Uops are decoded",
0697 "Counter": "0,1,2,3",
0698 "CounterMask": "1",
0699 "EventCode": "0xD1",
0700 "EventName": "UOPS_DECODED.STALL_CYCLES",
0701 "Invert": "1",
0702 "SampleAfterValue": "2000000",
0703 "UMask": "0x1"
0704 },
0705 {
0706 "AnyThread": "1",
0707 "BriefDescription": "Cycles Uops executed on any port (core count)",
0708 "Counter": "0,1,2,3",
0709 "CounterMask": "1",
0710 "EventCode": "0xB1",
0711 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
0712 "SampleAfterValue": "2000000",
0713 "UMask": "0x3f"
0714 },
0715 {
0716 "AnyThread": "1",
0717 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
0718 "Counter": "0,1,2,3",
0719 "CounterMask": "1",
0720 "EventCode": "0xB1",
0721 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
0722 "SampleAfterValue": "2000000",
0723 "UMask": "0x1f"
0724 },
0725 {
0726 "AnyThread": "1",
0727 "BriefDescription": "Uops executed on any port (core count)",
0728 "Counter": "0,1,2,3",
0729 "CounterMask": "1",
0730 "EdgeDetect": "1",
0731 "EventCode": "0xB1",
0732 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
0733 "Invert": "1",
0734 "SampleAfterValue": "2000000",
0735 "UMask": "0x3f"
0736 },
0737 {
0738 "AnyThread": "1",
0739 "BriefDescription": "Uops executed on ports 0-4 (core count)",
0740 "Counter": "0,1,2,3",
0741 "CounterMask": "1",
0742 "EdgeDetect": "1",
0743 "EventCode": "0xB1",
0744 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
0745 "Invert": "1",
0746 "SampleAfterValue": "2000000",
0747 "UMask": "0x1f"
0748 },
0749 {
0750 "AnyThread": "1",
0751 "BriefDescription": "Cycles no Uops issued on any port (core count)",
0752 "Counter": "0,1,2,3",
0753 "CounterMask": "1",
0754 "EventCode": "0xB1",
0755 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
0756 "Invert": "1",
0757 "SampleAfterValue": "2000000",
0758 "UMask": "0x3f"
0759 },
0760 {
0761 "AnyThread": "1",
0762 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
0763 "Counter": "0,1,2,3",
0764 "CounterMask": "1",
0765 "EventCode": "0xB1",
0766 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
0767 "Invert": "1",
0768 "SampleAfterValue": "2000000",
0769 "UMask": "0x1f"
0770 },
0771 {
0772 "BriefDescription": "Uops executed on port 0",
0773 "Counter": "0,1,2,3",
0774 "EventCode": "0xB1",
0775 "EventName": "UOPS_EXECUTED.PORT0",
0776 "SampleAfterValue": "2000000",
0777 "UMask": "0x1"
0778 },
0779 {
0780 "BriefDescription": "Uops issued on ports 0, 1 or 5",
0781 "Counter": "0,1,2,3",
0782 "EventCode": "0xB1",
0783 "EventName": "UOPS_EXECUTED.PORT015",
0784 "SampleAfterValue": "2000000",
0785 "UMask": "0x40"
0786 },
0787 {
0788 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
0789 "Counter": "0,1,2,3",
0790 "CounterMask": "1",
0791 "EventCode": "0xB1",
0792 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
0793 "Invert": "1",
0794 "SampleAfterValue": "2000000",
0795 "UMask": "0x40"
0796 },
0797 {
0798 "BriefDescription": "Uops executed on port 1",
0799 "Counter": "0,1,2,3",
0800 "EventCode": "0xB1",
0801 "EventName": "UOPS_EXECUTED.PORT1",
0802 "SampleAfterValue": "2000000",
0803 "UMask": "0x2"
0804 },
0805 {
0806 "AnyThread": "1",
0807 "BriefDescription": "Uops issued on ports 2, 3 or 4",
0808 "Counter": "0,1,2,3",
0809 "EventCode": "0xB1",
0810 "EventName": "UOPS_EXECUTED.PORT234_CORE",
0811 "SampleAfterValue": "2000000",
0812 "UMask": "0x80"
0813 },
0814 {
0815 "AnyThread": "1",
0816 "BriefDescription": "Uops executed on port 2 (core count)",
0817 "Counter": "0,1,2,3",
0818 "EventCode": "0xB1",
0819 "EventName": "UOPS_EXECUTED.PORT2_CORE",
0820 "SampleAfterValue": "2000000",
0821 "UMask": "0x4"
0822 },
0823 {
0824 "AnyThread": "1",
0825 "BriefDescription": "Uops executed on port 3 (core count)",
0826 "Counter": "0,1,2,3",
0827 "EventCode": "0xB1",
0828 "EventName": "UOPS_EXECUTED.PORT3_CORE",
0829 "SampleAfterValue": "2000000",
0830 "UMask": "0x8"
0831 },
0832 {
0833 "AnyThread": "1",
0834 "BriefDescription": "Uops executed on port 4 (core count)",
0835 "Counter": "0,1,2,3",
0836 "EventCode": "0xB1",
0837 "EventName": "UOPS_EXECUTED.PORT4_CORE",
0838 "SampleAfterValue": "2000000",
0839 "UMask": "0x10"
0840 },
0841 {
0842 "BriefDescription": "Uops executed on port 5",
0843 "Counter": "0,1,2,3",
0844 "EventCode": "0xB1",
0845 "EventName": "UOPS_EXECUTED.PORT5",
0846 "SampleAfterValue": "2000000",
0847 "UMask": "0x20"
0848 },
0849 {
0850 "BriefDescription": "Uops issued",
0851 "Counter": "0,1,2,3",
0852 "EventCode": "0xE",
0853 "EventName": "UOPS_ISSUED.ANY",
0854 "SampleAfterValue": "2000000",
0855 "UMask": "0x1"
0856 },
0857 {
0858 "AnyThread": "1",
0859 "BriefDescription": "Cycles no Uops were issued on any thread",
0860 "Counter": "0,1,2,3",
0861 "CounterMask": "1",
0862 "EventCode": "0xE",
0863 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
0864 "Invert": "1",
0865 "SampleAfterValue": "2000000",
0866 "UMask": "0x1"
0867 },
0868 {
0869 "AnyThread": "1",
0870 "BriefDescription": "Cycles Uops were issued on either thread",
0871 "Counter": "0,1,2,3",
0872 "CounterMask": "1",
0873 "EventCode": "0xE",
0874 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
0875 "SampleAfterValue": "2000000",
0876 "UMask": "0x1"
0877 },
0878 {
0879 "BriefDescription": "Fused Uops issued",
0880 "Counter": "0,1,2,3",
0881 "EventCode": "0xE",
0882 "EventName": "UOPS_ISSUED.FUSED",
0883 "SampleAfterValue": "2000000",
0884 "UMask": "0x2"
0885 },
0886 {
0887 "BriefDescription": "Cycles no Uops were issued",
0888 "Counter": "0,1,2,3",
0889 "CounterMask": "1",
0890 "EventCode": "0xE",
0891 "EventName": "UOPS_ISSUED.STALL_CYCLES",
0892 "Invert": "1",
0893 "SampleAfterValue": "2000000",
0894 "UMask": "0x1"
0895 },
0896 {
0897 "BriefDescription": "Cycles Uops are being retired",
0898 "Counter": "0,1,2,3",
0899 "CounterMask": "1",
0900 "EventCode": "0xC2",
0901 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
0902 "PEBS": "1",
0903 "SampleAfterValue": "2000000",
0904 "UMask": "0x1"
0905 },
0906 {
0907 "BriefDescription": "Uops retired (Precise Event)",
0908 "Counter": "0,1,2,3",
0909 "EventCode": "0xC2",
0910 "EventName": "UOPS_RETIRED.ANY",
0911 "PEBS": "1",
0912 "SampleAfterValue": "2000000",
0913 "UMask": "0x1"
0914 },
0915 {
0916 "BriefDescription": "Macro-fused Uops retired (Precise Event)",
0917 "Counter": "0,1,2,3",
0918 "EventCode": "0xC2",
0919 "EventName": "UOPS_RETIRED.MACRO_FUSED",
0920 "PEBS": "1",
0921 "SampleAfterValue": "2000000",
0922 "UMask": "0x4"
0923 },
0924 {
0925 "BriefDescription": "Retirement slots used (Precise Event)",
0926 "Counter": "0,1,2,3",
0927 "EventCode": "0xC2",
0928 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
0929 "PEBS": "1",
0930 "SampleAfterValue": "2000000",
0931 "UMask": "0x2"
0932 },
0933 {
0934 "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
0935 "Counter": "0,1,2,3",
0936 "CounterMask": "1",
0937 "EventCode": "0xC2",
0938 "EventName": "UOPS_RETIRED.STALL_CYCLES",
0939 "Invert": "1",
0940 "PEBS": "1",
0941 "SampleAfterValue": "2000000",
0942 "UMask": "0x1"
0943 },
0944 {
0945 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
0946 "Counter": "0,1,2,3",
0947 "CounterMask": "16",
0948 "EventCode": "0xC2",
0949 "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
0950 "Invert": "1",
0951 "PEBS": "1",
0952 "SampleAfterValue": "2000000",
0953 "UMask": "0x1"
0954 },
0955 {
0956 "BriefDescription": "Uop unfusions due to FP exceptions",
0957 "Counter": "0,1,2,3",
0958 "EventCode": "0xDB",
0959 "EventName": "UOP_UNFUSION",
0960 "SampleAfterValue": "2000000",
0961 "UMask": "0x1"
0962 }
0963 ]
