0001 [
0002 {
0003 "BriefDescription": "Cycles L1D locked",
0004 "Counter": "0,1",
0005 "EventCode": "0x63",
0006 "EventName": "CACHE_LOCK_CYCLES.L1D",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0x2"
0009 },
0010 {
0011 "BriefDescription": "Cycles L1D and L2 locked",
0012 "Counter": "0,1",
0013 "EventCode": "0x63",
0014 "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
0015 "SampleAfterValue": "2000000",
0016 "UMask": "0x1"
0017 },
0018 {
0019 "BriefDescription": "L1D cache lines replaced in M state",
0020 "Counter": "0,1",
0021 "EventCode": "0x51",
0022 "EventName": "L1D.M_EVICT",
0023 "SampleAfterValue": "2000000",
0024 "UMask": "0x4"
0025 },
0026 {
0027 "BriefDescription": "L1D cache lines allocated in the M state",
0028 "Counter": "0,1",
0029 "EventCode": "0x51",
0030 "EventName": "L1D.M_REPL",
0031 "SampleAfterValue": "2000000",
0032 "UMask": "0x2"
0033 },
0034 {
0035 "BriefDescription": "L1D snoop eviction of cache lines in M state",
0036 "Counter": "0,1",
0037 "EventCode": "0x51",
0038 "EventName": "L1D.M_SNOOP_EVICT",
0039 "SampleAfterValue": "2000000",
0040 "UMask": "0x8"
0041 },
0042 {
0043 "BriefDescription": "L1 data cache lines allocated",
0044 "Counter": "0,1",
0045 "EventCode": "0x51",
0046 "EventName": "L1D.REPL",
0047 "SampleAfterValue": "2000000",
0048 "UMask": "0x1"
0049 },
0050 {
0051 "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
0052 "Counter": "0,1",
0053 "EventCode": "0x52",
0054 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
0055 "SampleAfterValue": "2000000",
0056 "UMask": "0x1"
0057 },
0058 {
0059 "BriefDescription": "L1D hardware prefetch misses",
0060 "Counter": "0,1",
0061 "EventCode": "0x4E",
0062 "EventName": "L1D_PREFETCH.MISS",
0063 "SampleAfterValue": "200000",
0064 "UMask": "0x2"
0065 },
0066 {
0067 "BriefDescription": "L1D hardware prefetch requests",
0068 "Counter": "0,1",
0069 "EventCode": "0x4E",
0070 "EventName": "L1D_PREFETCH.REQUESTS",
0071 "SampleAfterValue": "200000",
0072 "UMask": "0x1"
0073 },
0074 {
0075 "BriefDescription": "L1D hardware prefetch requests triggered",
0076 "Counter": "0,1",
0077 "EventCode": "0x4E",
0078 "EventName": "L1D_PREFETCH.TRIGGERS",
0079 "SampleAfterValue": "200000",
0080 "UMask": "0x4"
0081 },
0082 {
0083 "BriefDescription": "L1 writebacks to L2 in E state",
0084 "Counter": "0,1,2,3",
0085 "EventCode": "0x28",
0086 "EventName": "L1D_WB_L2.E_STATE",
0087 "SampleAfterValue": "100000",
0088 "UMask": "0x4"
0089 },
0090 {
0091 "BriefDescription": "L1 writebacks to L2 in I state (misses)",
0092 "Counter": "0,1,2,3",
0093 "EventCode": "0x28",
0094 "EventName": "L1D_WB_L2.I_STATE",
0095 "SampleAfterValue": "100000",
0096 "UMask": "0x1"
0097 },
0098 {
0099 "BriefDescription": "All L1 writebacks to L2",
0100 "Counter": "0,1,2,3",
0101 "EventCode": "0x28",
0102 "EventName": "L1D_WB_L2.MESI",
0103 "SampleAfterValue": "100000",
0104 "UMask": "0xf"
0105 },
0106 {
0107 "BriefDescription": "L1 writebacks to L2 in M state",
0108 "Counter": "0,1,2,3",
0109 "EventCode": "0x28",
0110 "EventName": "L1D_WB_L2.M_STATE",
0111 "SampleAfterValue": "100000",
0112 "UMask": "0x8"
0113 },
0114 {
0115 "BriefDescription": "L1 writebacks to L2 in S state",
0116 "Counter": "0,1,2,3",
0117 "EventCode": "0x28",
0118 "EventName": "L1D_WB_L2.S_STATE",
0119 "SampleAfterValue": "100000",
0120 "UMask": "0x2"
0121 },
0122 {
0123 "BriefDescription": "All L2 data requests",
0124 "Counter": "0,1,2,3",
0125 "EventCode": "0x26",
0126 "EventName": "L2_DATA_RQSTS.ANY",
0127 "SampleAfterValue": "200000",
0128 "UMask": "0xff"
0129 },
0130 {
0131 "BriefDescription": "L2 data demand loads in E state",
0132 "Counter": "0,1,2,3",
0133 "EventCode": "0x26",
0134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
0135 "SampleAfterValue": "200000",
0136 "UMask": "0x4"
0137 },
0138 {
0139 "BriefDescription": "L2 data demand loads in I state (misses)",
0140 "Counter": "0,1,2,3",
0141 "EventCode": "0x26",
0142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
0143 "SampleAfterValue": "200000",
0144 "UMask": "0x1"
0145 },
0146 {
0147 "BriefDescription": "L2 data demand requests",
0148 "Counter": "0,1,2,3",
0149 "EventCode": "0x26",
0150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
0151 "SampleAfterValue": "200000",
0152 "UMask": "0xf"
0153 },
0154 {
0155 "BriefDescription": "L2 data demand loads in M state",
0156 "Counter": "0,1,2,3",
0157 "EventCode": "0x26",
0158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
0159 "SampleAfterValue": "200000",
0160 "UMask": "0x8"
0161 },
0162 {
0163 "BriefDescription": "L2 data demand loads in S state",
0164 "Counter": "0,1,2,3",
0165 "EventCode": "0x26",
0166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
0167 "SampleAfterValue": "200000",
0168 "UMask": "0x2"
0169 },
0170 {
0171 "BriefDescription": "L2 data prefetches in E state",
0172 "Counter": "0,1,2,3",
0173 "EventCode": "0x26",
0174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
0175 "SampleAfterValue": "200000",
0176 "UMask": "0x40"
0177 },
0178 {
0179 "BriefDescription": "L2 data prefetches in the I state (misses)",
0180 "Counter": "0,1,2,3",
0181 "EventCode": "0x26",
0182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
0183 "SampleAfterValue": "200000",
0184 "UMask": "0x10"
0185 },
0186 {
0187 "BriefDescription": "All L2 data prefetches",
0188 "Counter": "0,1,2,3",
0189 "EventCode": "0x26",
0190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
0191 "SampleAfterValue": "200000",
0192 "UMask": "0xf0"
0193 },
0194 {
0195 "BriefDescription": "L2 data prefetches in M state",
0196 "Counter": "0,1,2,3",
0197 "EventCode": "0x26",
0198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
0199 "SampleAfterValue": "200000",
0200 "UMask": "0x80"
0201 },
0202 {
0203 "BriefDescription": "L2 data prefetches in the S state",
0204 "Counter": "0,1,2,3",
0205 "EventCode": "0x26",
0206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
0207 "SampleAfterValue": "200000",
0208 "UMask": "0x20"
0209 },
0210 {
0211 "BriefDescription": "L2 lines alloacated",
0212 "Counter": "0,1,2,3",
0213 "EventCode": "0xF1",
0214 "EventName": "L2_LINES_IN.ANY",
0215 "SampleAfterValue": "100000",
0216 "UMask": "0x7"
0217 },
0218 {
0219 "BriefDescription": "L2 lines allocated in the E state",
0220 "Counter": "0,1,2,3",
0221 "EventCode": "0xF1",
0222 "EventName": "L2_LINES_IN.E_STATE",
0223 "SampleAfterValue": "100000",
0224 "UMask": "0x4"
0225 },
0226 {
0227 "BriefDescription": "L2 lines allocated in the S state",
0228 "Counter": "0,1,2,3",
0229 "EventCode": "0xF1",
0230 "EventName": "L2_LINES_IN.S_STATE",
0231 "SampleAfterValue": "100000",
0232 "UMask": "0x2"
0233 },
0234 {
0235 "BriefDescription": "L2 lines evicted",
0236 "Counter": "0,1,2,3",
0237 "EventCode": "0xF2",
0238 "EventName": "L2_LINES_OUT.ANY",
0239 "SampleAfterValue": "100000",
0240 "UMask": "0xf"
0241 },
0242 {
0243 "BriefDescription": "L2 lines evicted by a demand request",
0244 "Counter": "0,1,2,3",
0245 "EventCode": "0xF2",
0246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
0247 "SampleAfterValue": "100000",
0248 "UMask": "0x1"
0249 },
0250 {
0251 "BriefDescription": "L2 modified lines evicted by a demand request",
0252 "Counter": "0,1,2,3",
0253 "EventCode": "0xF2",
0254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
0255 "SampleAfterValue": "100000",
0256 "UMask": "0x2"
0257 },
0258 {
0259 "BriefDescription": "L2 lines evicted by a prefetch request",
0260 "Counter": "0,1,2,3",
0261 "EventCode": "0xF2",
0262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
0263 "SampleAfterValue": "100000",
0264 "UMask": "0x4"
0265 },
0266 {
0267 "BriefDescription": "L2 modified lines evicted by a prefetch request",
0268 "Counter": "0,1,2,3",
0269 "EventCode": "0xF2",
0270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
0271 "SampleAfterValue": "100000",
0272 "UMask": "0x8"
0273 },
0274 {
0275 "BriefDescription": "L2 instruction fetches",
0276 "Counter": "0,1,2,3",
0277 "EventCode": "0x24",
0278 "EventName": "L2_RQSTS.IFETCHES",
0279 "SampleAfterValue": "200000",
0280 "UMask": "0x30"
0281 },
0282 {
0283 "BriefDescription": "L2 instruction fetch hits",
0284 "Counter": "0,1,2,3",
0285 "EventCode": "0x24",
0286 "EventName": "L2_RQSTS.IFETCH_HIT",
0287 "SampleAfterValue": "200000",
0288 "UMask": "0x10"
0289 },
0290 {
0291 "BriefDescription": "L2 instruction fetch misses",
0292 "Counter": "0,1,2,3",
0293 "EventCode": "0x24",
0294 "EventName": "L2_RQSTS.IFETCH_MISS",
0295 "SampleAfterValue": "200000",
0296 "UMask": "0x20"
0297 },
0298 {
0299 "BriefDescription": "L2 load hits",
0300 "Counter": "0,1,2,3",
0301 "EventCode": "0x24",
0302 "EventName": "L2_RQSTS.LD_HIT",
0303 "SampleAfterValue": "200000",
0304 "UMask": "0x1"
0305 },
0306 {
0307 "BriefDescription": "L2 load misses",
0308 "Counter": "0,1,2,3",
0309 "EventCode": "0x24",
0310 "EventName": "L2_RQSTS.LD_MISS",
0311 "SampleAfterValue": "200000",
0312 "UMask": "0x2"
0313 },
0314 {
0315 "BriefDescription": "L2 requests",
0316 "Counter": "0,1,2,3",
0317 "EventCode": "0x24",
0318 "EventName": "L2_RQSTS.LOADS",
0319 "SampleAfterValue": "200000",
0320 "UMask": "0x3"
0321 },
0322 {
0323 "BriefDescription": "All L2 misses",
0324 "Counter": "0,1,2,3",
0325 "EventCode": "0x24",
0326 "EventName": "L2_RQSTS.MISS",
0327 "SampleAfterValue": "200000",
0328 "UMask": "0xaa"
0329 },
0330 {
0331 "BriefDescription": "All L2 prefetches",
0332 "Counter": "0,1,2,3",
0333 "EventCode": "0x24",
0334 "EventName": "L2_RQSTS.PREFETCHES",
0335 "SampleAfterValue": "200000",
0336 "UMask": "0xc0"
0337 },
0338 {
0339 "BriefDescription": "L2 prefetch hits",
0340 "Counter": "0,1,2,3",
0341 "EventCode": "0x24",
0342 "EventName": "L2_RQSTS.PREFETCH_HIT",
0343 "SampleAfterValue": "200000",
0344 "UMask": "0x40"
0345 },
0346 {
0347 "BriefDescription": "L2 prefetch misses",
0348 "Counter": "0,1,2,3",
0349 "EventCode": "0x24",
0350 "EventName": "L2_RQSTS.PREFETCH_MISS",
0351 "SampleAfterValue": "200000",
0352 "UMask": "0x80"
0353 },
0354 {
0355 "BriefDescription": "All L2 requests",
0356 "Counter": "0,1,2,3",
0357 "EventCode": "0x24",
0358 "EventName": "L2_RQSTS.REFERENCES",
0359 "SampleAfterValue": "200000",
0360 "UMask": "0xff"
0361 },
0362 {
0363 "BriefDescription": "L2 RFO requests",
0364 "Counter": "0,1,2,3",
0365 "EventCode": "0x24",
0366 "EventName": "L2_RQSTS.RFOS",
0367 "SampleAfterValue": "200000",
0368 "UMask": "0xc"
0369 },
0370 {
0371 "BriefDescription": "L2 RFO hits",
0372 "Counter": "0,1,2,3",
0373 "EventCode": "0x24",
0374 "EventName": "L2_RQSTS.RFO_HIT",
0375 "SampleAfterValue": "200000",
0376 "UMask": "0x4"
0377 },
0378 {
0379 "BriefDescription": "L2 RFO misses",
0380 "Counter": "0,1,2,3",
0381 "EventCode": "0x24",
0382 "EventName": "L2_RQSTS.RFO_MISS",
0383 "SampleAfterValue": "200000",
0384 "UMask": "0x8"
0385 },
0386 {
0387 "BriefDescription": "All L2 transactions",
0388 "Counter": "0,1,2,3",
0389 "EventCode": "0xF0",
0390 "EventName": "L2_TRANSACTIONS.ANY",
0391 "SampleAfterValue": "200000",
0392 "UMask": "0x80"
0393 },
0394 {
0395 "BriefDescription": "L2 fill transactions",
0396 "Counter": "0,1,2,3",
0397 "EventCode": "0xF0",
0398 "EventName": "L2_TRANSACTIONS.FILL",
0399 "SampleAfterValue": "200000",
0400 "UMask": "0x20"
0401 },
0402 {
0403 "BriefDescription": "L2 instruction fetch transactions",
0404 "Counter": "0,1,2,3",
0405 "EventCode": "0xF0",
0406 "EventName": "L2_TRANSACTIONS.IFETCH",
0407 "SampleAfterValue": "200000",
0408 "UMask": "0x4"
0409 },
0410 {
0411 "BriefDescription": "L1D writeback to L2 transactions",
0412 "Counter": "0,1,2,3",
0413 "EventCode": "0xF0",
0414 "EventName": "L2_TRANSACTIONS.L1D_WB",
0415 "SampleAfterValue": "200000",
0416 "UMask": "0x10"
0417 },
0418 {
0419 "BriefDescription": "L2 Load transactions",
0420 "Counter": "0,1,2,3",
0421 "EventCode": "0xF0",
0422 "EventName": "L2_TRANSACTIONS.LOAD",
0423 "SampleAfterValue": "200000",
0424 "UMask": "0x1"
0425 },
0426 {
0427 "BriefDescription": "L2 prefetch transactions",
0428 "Counter": "0,1,2,3",
0429 "EventCode": "0xF0",
0430 "EventName": "L2_TRANSACTIONS.PREFETCH",
0431 "SampleAfterValue": "200000",
0432 "UMask": "0x8"
0433 },
0434 {
0435 "BriefDescription": "L2 RFO transactions",
0436 "Counter": "0,1,2,3",
0437 "EventCode": "0xF0",
0438 "EventName": "L2_TRANSACTIONS.RFO",
0439 "SampleAfterValue": "200000",
0440 "UMask": "0x2"
0441 },
0442 {
0443 "BriefDescription": "L2 writeback to LLC transactions",
0444 "Counter": "0,1,2,3",
0445 "EventCode": "0xF0",
0446 "EventName": "L2_TRANSACTIONS.WB",
0447 "SampleAfterValue": "200000",
0448 "UMask": "0x40"
0449 },
0450 {
0451 "BriefDescription": "L2 demand lock RFOs in E state",
0452 "Counter": "0,1,2,3",
0453 "EventCode": "0x27",
0454 "EventName": "L2_WRITE.LOCK.E_STATE",
0455 "SampleAfterValue": "100000",
0456 "UMask": "0x40"
0457 },
0458 {
0459 "BriefDescription": "All demand L2 lock RFOs that hit the cache",
0460 "Counter": "0,1,2,3",
0461 "EventCode": "0x27",
0462 "EventName": "L2_WRITE.LOCK.HIT",
0463 "SampleAfterValue": "100000",
0464 "UMask": "0xe0"
0465 },
0466 {
0467 "BriefDescription": "L2 demand lock RFOs in I state (misses)",
0468 "Counter": "0,1,2,3",
0469 "EventCode": "0x27",
0470 "EventName": "L2_WRITE.LOCK.I_STATE",
0471 "SampleAfterValue": "100000",
0472 "UMask": "0x10"
0473 },
0474 {
0475 "BriefDescription": "All demand L2 lock RFOs",
0476 "Counter": "0,1,2,3",
0477 "EventCode": "0x27",
0478 "EventName": "L2_WRITE.LOCK.MESI",
0479 "SampleAfterValue": "100000",
0480 "UMask": "0xf0"
0481 },
0482 {
0483 "BriefDescription": "L2 demand lock RFOs in M state",
0484 "Counter": "0,1,2,3",
0485 "EventCode": "0x27",
0486 "EventName": "L2_WRITE.LOCK.M_STATE",
0487 "SampleAfterValue": "100000",
0488 "UMask": "0x80"
0489 },
0490 {
0491 "BriefDescription": "L2 demand lock RFOs in S state",
0492 "Counter": "0,1,2,3",
0493 "EventCode": "0x27",
0494 "EventName": "L2_WRITE.LOCK.S_STATE",
0495 "SampleAfterValue": "100000",
0496 "UMask": "0x20"
0497 },
0498 {
0499 "BriefDescription": "All L2 demand store RFOs that hit the cache",
0500 "Counter": "0,1,2,3",
0501 "EventCode": "0x27",
0502 "EventName": "L2_WRITE.RFO.HIT",
0503 "SampleAfterValue": "100000",
0504 "UMask": "0xe"
0505 },
0506 {
0507 "BriefDescription": "L2 demand store RFOs in I state (misses)",
0508 "Counter": "0,1,2,3",
0509 "EventCode": "0x27",
0510 "EventName": "L2_WRITE.RFO.I_STATE",
0511 "SampleAfterValue": "100000",
0512 "UMask": "0x1"
0513 },
0514 {
0515 "BriefDescription": "All L2 demand store RFOs",
0516 "Counter": "0,1,2,3",
0517 "EventCode": "0x27",
0518 "EventName": "L2_WRITE.RFO.MESI",
0519 "SampleAfterValue": "100000",
0520 "UMask": "0xf"
0521 },
0522 {
0523 "BriefDescription": "L2 demand store RFOs in M state",
0524 "Counter": "0,1,2,3",
0525 "EventCode": "0x27",
0526 "EventName": "L2_WRITE.RFO.M_STATE",
0527 "SampleAfterValue": "100000",
0528 "UMask": "0x8"
0529 },
0530 {
0531 "BriefDescription": "L2 demand store RFOs in S state",
0532 "Counter": "0,1,2,3",
0533 "EventCode": "0x27",
0534 "EventName": "L2_WRITE.RFO.S_STATE",
0535 "SampleAfterValue": "100000",
0536 "UMask": "0x2"
0537 },
0538 {
0539 "BriefDescription": "Longest latency cache miss",
0540 "Counter": "0,1,2,3",
0541 "EventCode": "0x2E",
0542 "EventName": "LONGEST_LAT_CACHE.MISS",
0543 "SampleAfterValue": "100000",
0544 "UMask": "0x41"
0545 },
0546 {
0547 "BriefDescription": "Longest latency cache reference",
0548 "Counter": "0,1,2,3",
0549 "EventCode": "0x2E",
0550 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0551 "SampleAfterValue": "200000",
0552 "UMask": "0x4f"
0553 },
0554 {
0555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
0556 "Counter": "3",
0557 "EventCode": "0xB",
0558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
0559 "MSRIndex": "0x3F6",
0560 "MSRValue": "0x0",
0561 "PEBS": "2",
0562 "SampleAfterValue": "2000000",
0563 "UMask": "0x10"
0564 },
0565 {
0566 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
0567 "Counter": "3",
0568 "EventCode": "0xB",
0569 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
0570 "MSRIndex": "0x3F6",
0571 "MSRValue": "0x400",
0572 "PEBS": "2",
0573 "SampleAfterValue": "100",
0574 "UMask": "0x10"
0575 },
0576 {
0577 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
0578 "Counter": "3",
0579 "EventCode": "0xB",
0580 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
0581 "MSRIndex": "0x3F6",
0582 "MSRValue": "0x80",
0583 "PEBS": "2",
0584 "SampleAfterValue": "1000",
0585 "UMask": "0x10"
0586 },
0587 {
0588 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
0589 "Counter": "3",
0590 "EventCode": "0xB",
0591 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
0592 "MSRIndex": "0x3F6",
0593 "MSRValue": "0x10",
0594 "PEBS": "2",
0595 "SampleAfterValue": "10000",
0596 "UMask": "0x10"
0597 },
0598 {
0599 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
0600 "Counter": "3",
0601 "EventCode": "0xB",
0602 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
0603 "MSRIndex": "0x3F6",
0604 "MSRValue": "0x4000",
0605 "PEBS": "2",
0606 "SampleAfterValue": "5",
0607 "UMask": "0x10"
0608 },
0609 {
0610 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
0611 "Counter": "3",
0612 "EventCode": "0xB",
0613 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
0614 "MSRIndex": "0x3F6",
0615 "MSRValue": "0x800",
0616 "PEBS": "2",
0617 "SampleAfterValue": "50",
0618 "UMask": "0x10"
0619 },
0620 {
0621 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
0622 "Counter": "3",
0623 "EventCode": "0xB",
0624 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
0625 "MSRIndex": "0x3F6",
0626 "MSRValue": "0x100",
0627 "PEBS": "2",
0628 "SampleAfterValue": "500",
0629 "UMask": "0x10"
0630 },
0631 {
0632 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
0633 "Counter": "3",
0634 "EventCode": "0xB",
0635 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
0636 "MSRIndex": "0x3F6",
0637 "MSRValue": "0x20",
0638 "PEBS": "2",
0639 "SampleAfterValue": "5000",
0640 "UMask": "0x10"
0641 },
0642 {
0643 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
0644 "Counter": "3",
0645 "EventCode": "0xB",
0646 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
0647 "MSRIndex": "0x3F6",
0648 "MSRValue": "0x8000",
0649 "PEBS": "2",
0650 "SampleAfterValue": "3",
0651 "UMask": "0x10"
0652 },
0653 {
0654 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
0655 "Counter": "3",
0656 "EventCode": "0xB",
0657 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
0658 "MSRIndex": "0x3F6",
0659 "MSRValue": "0x4",
0660 "PEBS": "2",
0661 "SampleAfterValue": "50000",
0662 "UMask": "0x10"
0663 },
0664 {
0665 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
0666 "Counter": "3",
0667 "EventCode": "0xB",
0668 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
0669 "MSRIndex": "0x3F6",
0670 "MSRValue": "0x1000",
0671 "PEBS": "2",
0672 "SampleAfterValue": "20",
0673 "UMask": "0x10"
0674 },
0675 {
0676 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
0677 "Counter": "3",
0678 "EventCode": "0xB",
0679 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
0680 "MSRIndex": "0x3F6",
0681 "MSRValue": "0x200",
0682 "PEBS": "2",
0683 "SampleAfterValue": "200",
0684 "UMask": "0x10"
0685 },
0686 {
0687 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
0688 "Counter": "3",
0689 "EventCode": "0xB",
0690 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
0691 "MSRIndex": "0x3F6",
0692 "MSRValue": "0x40",
0693 "PEBS": "2",
0694 "SampleAfterValue": "2000",
0695 "UMask": "0x10"
0696 },
0697 {
0698 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
0699 "Counter": "3",
0700 "EventCode": "0xB",
0701 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
0702 "MSRIndex": "0x3F6",
0703 "MSRValue": "0x8",
0704 "PEBS": "2",
0705 "SampleAfterValue": "20000",
0706 "UMask": "0x10"
0707 },
0708 {
0709 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
0710 "Counter": "3",
0711 "EventCode": "0xB",
0712 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
0713 "MSRIndex": "0x3F6",
0714 "MSRValue": "0x2000",
0715 "PEBS": "2",
0716 "SampleAfterValue": "10",
0717 "UMask": "0x10"
0718 },
0719 {
0720 "BriefDescription": "Instructions retired which contains a load (Precise Event)",
0721 "Counter": "0,1,2,3",
0722 "EventCode": "0xB",
0723 "EventName": "MEM_INST_RETIRED.LOADS",
0724 "PEBS": "1",
0725 "SampleAfterValue": "2000000",
0726 "UMask": "0x1"
0727 },
0728 {
0729 "BriefDescription": "Instructions retired which contains a store (Precise Event)",
0730 "Counter": "0,1,2,3",
0731 "EventCode": "0xB",
0732 "EventName": "MEM_INST_RETIRED.STORES",
0733 "PEBS": "1",
0734 "SampleAfterValue": "2000000",
0735 "UMask": "0x2"
0736 },
0737 {
0738 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
0739 "Counter": "0,1,2,3",
0740 "EventCode": "0xCB",
0741 "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
0742 "PEBS": "1",
0743 "SampleAfterValue": "200000",
0744 "UMask": "0x40"
0745 },
0746 {
0747 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
0748 "Counter": "0,1,2,3",
0749 "EventCode": "0xCB",
0750 "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
0751 "PEBS": "1",
0752 "SampleAfterValue": "2000000",
0753 "UMask": "0x1"
0754 },
0755 {
0756 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
0757 "Counter": "0,1,2,3",
0758 "EventCode": "0xCB",
0759 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
0760 "PEBS": "1",
0761 "SampleAfterValue": "200000",
0762 "UMask": "0x2"
0763 },
0764 {
0765 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
0766 "Counter": "0,1,2,3",
0767 "EventCode": "0xCB",
0768 "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
0769 "PEBS": "1",
0770 "SampleAfterValue": "10000",
0771 "UMask": "0x10"
0772 },
0773 {
0774 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
0775 "Counter": "0,1,2,3",
0776 "EventCode": "0xCB",
0777 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
0778 "PEBS": "1",
0779 "SampleAfterValue": "40000",
0780 "UMask": "0x4"
0781 },
0782 {
0783 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
0784 "Counter": "0,1,2,3",
0785 "EventCode": "0xCB",
0786 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
0787 "PEBS": "1",
0788 "SampleAfterValue": "40000",
0789 "UMask": "0x8"
0790 },
0791 {
0792 "BriefDescription": "All offcore requests",
0793 "Counter": "0,1,2,3",
0794 "EventCode": "0xB0",
0795 "EventName": "OFFCORE_REQUESTS.ANY",
0796 "SampleAfterValue": "100000",
0797 "UMask": "0x80"
0798 },
0799 {
0800 "BriefDescription": "Offcore read requests",
0801 "Counter": "0,1,2,3",
0802 "EventCode": "0xB0",
0803 "EventName": "OFFCORE_REQUESTS.ANY.READ",
0804 "SampleAfterValue": "100000",
0805 "UMask": "0x8"
0806 },
0807 {
0808 "BriefDescription": "Offcore RFO requests",
0809 "Counter": "0,1,2,3",
0810 "EventCode": "0xB0",
0811 "EventName": "OFFCORE_REQUESTS.ANY.RFO",
0812 "SampleAfterValue": "100000",
0813 "UMask": "0x10"
0814 },
0815 {
0816 "BriefDescription": "Offcore demand code read requests",
0817 "Counter": "0,1,2,3",
0818 "EventCode": "0xB0",
0819 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
0820 "SampleAfterValue": "100000",
0821 "UMask": "0x2"
0822 },
0823 {
0824 "BriefDescription": "Offcore demand data read requests",
0825 "Counter": "0,1,2,3",
0826 "EventCode": "0xB0",
0827 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
0828 "SampleAfterValue": "100000",
0829 "UMask": "0x1"
0830 },
0831 {
0832 "BriefDescription": "Offcore demand RFO requests",
0833 "Counter": "0,1,2,3",
0834 "EventCode": "0xB0",
0835 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
0836 "SampleAfterValue": "100000",
0837 "UMask": "0x4"
0838 },
0839 {
0840 "BriefDescription": "Offcore L1 data cache writebacks",
0841 "Counter": "0,1,2,3",
0842 "EventCode": "0xB0",
0843 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
0844 "SampleAfterValue": "100000",
0845 "UMask": "0x40"
0846 },
0847 {
0848 "BriefDescription": "Outstanding offcore reads",
0849 "EventCode": "0x60",
0850 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
0851 "SampleAfterValue": "2000000",
0852 "UMask": "0x8"
0853 },
0854 {
0855 "BriefDescription": "Cycles offcore reads busy",
0856 "CounterMask": "1",
0857 "EventCode": "0x60",
0858 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
0859 "SampleAfterValue": "2000000",
0860 "UMask": "0x8"
0861 },
0862 {
0863 "BriefDescription": "Outstanding offcore demand code reads",
0864 "EventCode": "0x60",
0865 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
0866 "SampleAfterValue": "2000000",
0867 "UMask": "0x2"
0868 },
0869 {
0870 "BriefDescription": "Cycles offcore demand code read busy",
0871 "CounterMask": "1",
0872 "EventCode": "0x60",
0873 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
0874 "SampleAfterValue": "2000000",
0875 "UMask": "0x2"
0876 },
0877 {
0878 "BriefDescription": "Outstanding offcore demand data reads",
0879 "EventCode": "0x60",
0880 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
0881 "SampleAfterValue": "2000000",
0882 "UMask": "0x1"
0883 },
0884 {
0885 "BriefDescription": "Cycles offcore demand data read busy",
0886 "CounterMask": "1",
0887 "EventCode": "0x60",
0888 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
0889 "SampleAfterValue": "2000000",
0890 "UMask": "0x1"
0891 },
0892 {
0893 "BriefDescription": "Outstanding offcore demand RFOs",
0894 "EventCode": "0x60",
0895 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
0896 "SampleAfterValue": "2000000",
0897 "UMask": "0x4"
0898 },
0899 {
0900 "BriefDescription": "Cycles offcore demand RFOs busy",
0901 "CounterMask": "1",
0902 "EventCode": "0x60",
0903 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
0904 "SampleAfterValue": "2000000",
0905 "UMask": "0x4"
0906 },
0907 {
0908 "BriefDescription": "Offcore requests blocked due to Super Queue full",
0909 "Counter": "0,1,2,3",
0910 "EventCode": "0xB2",
0911 "EventName": "OFFCORE_REQUESTS_SQ_FULL",
0912 "SampleAfterValue": "100000",
0913 "UMask": "0x1"
0914 },
0915 {
0916 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
0917 "Counter": "0,1,2,3",
0918 "EventCode": "0xB7, 0xBB",
0919 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
0920 "MSRIndex": "0x1a6,0x1a7",
0921 "MSRValue": "0x5011",
0922 "Offcore": "1",
0923 "SampleAfterValue": "100000",
0924 "UMask": "0x1"
0925 },
0926 {
0927 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
0928 "Counter": "0,1,2,3",
0929 "EventCode": "0xB7, 0xBB",
0930 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
0931 "MSRIndex": "0x1a6,0x1a7",
0932 "MSRValue": "0x7f11",
0933 "Offcore": "1",
0934 "SampleAfterValue": "100000",
0935 "UMask": "0x1"
0936 },
0937 {
0938 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
0939 "Counter": "0,1,2,3",
0940 "EventCode": "0xB7, 0xBB",
0941 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
0942 "MSRIndex": "0x1a6,0x1a7",
0943 "MSRValue": "0xff11",
0944 "Offcore": "1",
0945 "SampleAfterValue": "100000",
0946 "UMask": "0x1"
0947 },
0948 {
0949 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
0950 "Counter": "0,1,2,3",
0951 "EventCode": "0xB7, 0xBB",
0952 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
0953 "MSRIndex": "0x1a6,0x1a7",
0954 "MSRValue": "0x8011",
0955 "Offcore": "1",
0956 "SampleAfterValue": "100000",
0957 "UMask": "0x1"
0958 },
0959 {
0960 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
0961 "Counter": "0,1,2,3",
0962 "EventCode": "0xB7, 0xBB",
0963 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
0964 "MSRIndex": "0x1a6,0x1a7",
0965 "MSRValue": "0x111",
0966 "Offcore": "1",
0967 "SampleAfterValue": "100000",
0968 "UMask": "0x1"
0969 },
0970 {
0971 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
0972 "Counter": "0,1,2,3",
0973 "EventCode": "0xB7, 0xBB",
0974 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
0975 "MSRIndex": "0x1a6,0x1a7",
0976 "MSRValue": "0x211",
0977 "Offcore": "1",
0978 "SampleAfterValue": "100000",
0979 "UMask": "0x1"
0980 },
0981 {
0982 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
0983 "Counter": "0,1,2,3",
0984 "EventCode": "0xB7, 0xBB",
0985 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
0986 "MSRIndex": "0x1a6,0x1a7",
0987 "MSRValue": "0x411",
0988 "Offcore": "1",
0989 "SampleAfterValue": "100000",
0990 "UMask": "0x1"
0991 },
0992 {
0993 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
0994 "Counter": "0,1,2,3",
0995 "EventCode": "0xB7, 0xBB",
0996 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
0997 "MSRIndex": "0x1a6,0x1a7",
0998 "MSRValue": "0x711",
0999 "Offcore": "1",
1000 "SampleAfterValue": "100000",
1001 "UMask": "0x1"
1002 },
1003 {
1004 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1005 "Counter": "0,1,2,3",
1006 "EventCode": "0xB7, 0xBB",
1007 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1008 "MSRIndex": "0x1a6,0x1a7",
1009 "MSRValue": "0x1011",
1010 "Offcore": "1",
1011 "SampleAfterValue": "100000",
1012 "UMask": "0x1"
1013 },
1014 {
1015 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
1016 "Counter": "0,1,2,3",
1017 "EventCode": "0xB7, 0xBB",
1018 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1019 "MSRIndex": "0x1a6,0x1a7",
1020 "MSRValue": "0x811",
1021 "Offcore": "1",
1022 "SampleAfterValue": "100000",
1023 "UMask": "0x1"
1024 },
1025 {
1026 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1027 "Counter": "0,1,2,3",
1028 "EventCode": "0xB7, 0xBB",
1029 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1030 "MSRIndex": "0x1a6,0x1a7",
1031 "MSRValue": "0x5044",
1032 "Offcore": "1",
1033 "SampleAfterValue": "100000",
1034 "UMask": "0x1"
1035 },
1036 {
1037 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
1038 "Counter": "0,1,2,3",
1039 "EventCode": "0xB7, 0xBB",
1040 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1041 "MSRIndex": "0x1a6,0x1a7",
1042 "MSRValue": "0x7f44",
1043 "Offcore": "1",
1044 "SampleAfterValue": "100000",
1045 "UMask": "0x1"
1046 },
1047 {
1048 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
1049 "Counter": "0,1,2,3",
1050 "EventCode": "0xB7, 0xBB",
1051 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1052 "MSRIndex": "0x1a6,0x1a7",
1053 "MSRValue": "0xff44",
1054 "Offcore": "1",
1055 "SampleAfterValue": "100000",
1056 "UMask": "0x1"
1057 },
1058 {
1059 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
1060 "Counter": "0,1,2,3",
1061 "EventCode": "0xB7, 0xBB",
1062 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1063 "MSRIndex": "0x1a6,0x1a7",
1064 "MSRValue": "0x8044",
1065 "Offcore": "1",
1066 "SampleAfterValue": "100000",
1067 "UMask": "0x1"
1068 },
1069 {
1070 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1071 "Counter": "0,1,2,3",
1072 "EventCode": "0xB7, 0xBB",
1073 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1074 "MSRIndex": "0x1a6,0x1a7",
1075 "MSRValue": "0x144",
1076 "Offcore": "1",
1077 "SampleAfterValue": "100000",
1078 "UMask": "0x1"
1079 },
1080 {
1081 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1082 "Counter": "0,1,2,3",
1083 "EventCode": "0xB7, 0xBB",
1084 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1085 "MSRIndex": "0x1a6,0x1a7",
1086 "MSRValue": "0x244",
1087 "Offcore": "1",
1088 "SampleAfterValue": "100000",
1089 "UMask": "0x1"
1090 },
1091 {
1092 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1093 "Counter": "0,1,2,3",
1094 "EventCode": "0xB7, 0xBB",
1095 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1096 "MSRIndex": "0x1a6,0x1a7",
1097 "MSRValue": "0x444",
1098 "Offcore": "1",
1099 "SampleAfterValue": "100000",
1100 "UMask": "0x1"
1101 },
1102 {
1103 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
1104 "Counter": "0,1,2,3",
1105 "EventCode": "0xB7, 0xBB",
1106 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1107 "MSRIndex": "0x1a6,0x1a7",
1108 "MSRValue": "0x744",
1109 "Offcore": "1",
1110 "SampleAfterValue": "100000",
1111 "UMask": "0x1"
1112 },
1113 {
1114 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1115 "Counter": "0,1,2,3",
1116 "EventCode": "0xB7, 0xBB",
1117 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1118 "MSRIndex": "0x1a6,0x1a7",
1119 "MSRValue": "0x1044",
1120 "Offcore": "1",
1121 "SampleAfterValue": "100000",
1122 "UMask": "0x1"
1123 },
1124 {
1125 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1126 "Counter": "0,1,2,3",
1127 "EventCode": "0xB7, 0xBB",
1128 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1129 "MSRIndex": "0x1a6,0x1a7",
1130 "MSRValue": "0x844",
1131 "Offcore": "1",
1132 "SampleAfterValue": "100000",
1133 "UMask": "0x1"
1134 },
1135 {
1136 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1137 "Counter": "0,1,2,3",
1138 "EventCode": "0xB7, 0xBB",
1139 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1140 "MSRIndex": "0x1a6,0x1a7",
1141 "MSRValue": "0x50ff",
1142 "Offcore": "1",
1143 "SampleAfterValue": "100000",
1144 "UMask": "0x1"
1145 },
1146 {
1147 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
1148 "Counter": "0,1,2,3",
1149 "EventCode": "0xB7, 0xBB",
1150 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1151 "MSRIndex": "0x1a6,0x1a7",
1152 "MSRValue": "0x7fff",
1153 "Offcore": "1",
1154 "SampleAfterValue": "100000",
1155 "UMask": "0x1"
1156 },
1157 {
1158 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
1159 "Counter": "0,1,2,3",
1160 "EventCode": "0xB7, 0xBB",
1161 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1162 "MSRIndex": "0x1a6,0x1a7",
1163 "MSRValue": "0xffff",
1164 "Offcore": "1",
1165 "SampleAfterValue": "100000",
1166 "UMask": "0x1"
1167 },
1168 {
1169 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
1170 "Counter": "0,1,2,3",
1171 "EventCode": "0xB7, 0xBB",
1172 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1173 "MSRIndex": "0x1a6,0x1a7",
1174 "MSRValue": "0x80ff",
1175 "Offcore": "1",
1176 "SampleAfterValue": "100000",
1177 "UMask": "0x1"
1178 },
1179 {
1180 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1181 "Counter": "0,1,2,3",
1182 "EventCode": "0xB7, 0xBB",
1183 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1184 "MSRIndex": "0x1a6,0x1a7",
1185 "MSRValue": "0x1ff",
1186 "Offcore": "1",
1187 "SampleAfterValue": "100000",
1188 "UMask": "0x1"
1189 },
1190 {
1191 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1192 "Counter": "0,1,2,3",
1193 "EventCode": "0xB7, 0xBB",
1194 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1195 "MSRIndex": "0x1a6,0x1a7",
1196 "MSRValue": "0x2ff",
1197 "Offcore": "1",
1198 "SampleAfterValue": "100000",
1199 "UMask": "0x1"
1200 },
1201 {
1202 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1203 "Counter": "0,1,2,3",
1204 "EventCode": "0xB7, 0xBB",
1205 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1206 "MSRIndex": "0x1a6,0x1a7",
1207 "MSRValue": "0x4ff",
1208 "Offcore": "1",
1209 "SampleAfterValue": "100000",
1210 "UMask": "0x1"
1211 },
1212 {
1213 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
1214 "Counter": "0,1,2,3",
1215 "EventCode": "0xB7, 0xBB",
1216 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1217 "MSRIndex": "0x1a6,0x1a7",
1218 "MSRValue": "0x7ff",
1219 "Offcore": "1",
1220 "SampleAfterValue": "100000",
1221 "UMask": "0x1"
1222 },
1223 {
1224 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1225 "Counter": "0,1,2,3",
1226 "EventCode": "0xB7, 0xBB",
1227 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1228 "MSRIndex": "0x1a6,0x1a7",
1229 "MSRValue": "0x10ff",
1230 "Offcore": "1",
1231 "SampleAfterValue": "100000",
1232 "UMask": "0x1"
1233 },
1234 {
1235 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
1236 "Counter": "0,1,2,3",
1237 "EventCode": "0xB7, 0xBB",
1238 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1239 "MSRIndex": "0x1a6,0x1a7",
1240 "MSRValue": "0x8ff",
1241 "Offcore": "1",
1242 "SampleAfterValue": "100000",
1243 "UMask": "0x1"
1244 },
1245 {
1246 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1247 "Counter": "0,1,2,3",
1248 "EventCode": "0xB7, 0xBB",
1249 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1250 "MSRIndex": "0x1a6,0x1a7",
1251 "MSRValue": "0x5022",
1252 "Offcore": "1",
1253 "SampleAfterValue": "100000",
1254 "UMask": "0x1"
1255 },
1256 {
1257 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
1258 "Counter": "0,1,2,3",
1259 "EventCode": "0xB7, 0xBB",
1260 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1261 "MSRIndex": "0x1a6,0x1a7",
1262 "MSRValue": "0x7f22",
1263 "Offcore": "1",
1264 "SampleAfterValue": "100000",
1265 "UMask": "0x1"
1266 },
1267 {
1268 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
1269 "Counter": "0,1,2,3",
1270 "EventCode": "0xB7, 0xBB",
1271 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1272 "MSRIndex": "0x1a6,0x1a7",
1273 "MSRValue": "0xff22",
1274 "Offcore": "1",
1275 "SampleAfterValue": "100000",
1276 "UMask": "0x1"
1277 },
1278 {
1279 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
1280 "Counter": "0,1,2,3",
1281 "EventCode": "0xB7, 0xBB",
1282 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1283 "MSRIndex": "0x1a6,0x1a7",
1284 "MSRValue": "0x8022",
1285 "Offcore": "1",
1286 "SampleAfterValue": "100000",
1287 "UMask": "0x1"
1288 },
1289 {
1290 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1291 "Counter": "0,1,2,3",
1292 "EventCode": "0xB7, 0xBB",
1293 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1294 "MSRIndex": "0x1a6,0x1a7",
1295 "MSRValue": "0x122",
1296 "Offcore": "1",
1297 "SampleAfterValue": "100000",
1298 "UMask": "0x1"
1299 },
1300 {
1301 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1302 "Counter": "0,1,2,3",
1303 "EventCode": "0xB7, 0xBB",
1304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1305 "MSRIndex": "0x1a6,0x1a7",
1306 "MSRValue": "0x222",
1307 "Offcore": "1",
1308 "SampleAfterValue": "100000",
1309 "UMask": "0x1"
1310 },
1311 {
1312 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1313 "Counter": "0,1,2,3",
1314 "EventCode": "0xB7, 0xBB",
1315 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1316 "MSRIndex": "0x1a6,0x1a7",
1317 "MSRValue": "0x422",
1318 "Offcore": "1",
1319 "SampleAfterValue": "100000",
1320 "UMask": "0x1"
1321 },
1322 {
1323 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
1324 "Counter": "0,1,2,3",
1325 "EventCode": "0xB7, 0xBB",
1326 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1327 "MSRIndex": "0x1a6,0x1a7",
1328 "MSRValue": "0x722",
1329 "Offcore": "1",
1330 "SampleAfterValue": "100000",
1331 "UMask": "0x1"
1332 },
1333 {
1334 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1335 "Counter": "0,1,2,3",
1336 "EventCode": "0xB7, 0xBB",
1337 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1338 "MSRIndex": "0x1a6,0x1a7",
1339 "MSRValue": "0x1022",
1340 "Offcore": "1",
1341 "SampleAfterValue": "100000",
1342 "UMask": "0x1"
1343 },
1344 {
1345 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
1346 "Counter": "0,1,2,3",
1347 "EventCode": "0xB7, 0xBB",
1348 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1349 "MSRIndex": "0x1a6,0x1a7",
1350 "MSRValue": "0x822",
1351 "Offcore": "1",
1352 "SampleAfterValue": "100000",
1353 "UMask": "0x1"
1354 },
1355 {
1356 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1357 "Counter": "0,1,2,3",
1358 "EventCode": "0xB7, 0xBB",
1359 "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1360 "MSRIndex": "0x1a6,0x1a7",
1361 "MSRValue": "0x5008",
1362 "Offcore": "1",
1363 "SampleAfterValue": "100000",
1364 "UMask": "0x1"
1365 },
1366 {
1367 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
1368 "Counter": "0,1,2,3",
1369 "EventCode": "0xB7, 0xBB",
1370 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1371 "MSRIndex": "0x1a6,0x1a7",
1372 "MSRValue": "0x7f08",
1373 "Offcore": "1",
1374 "SampleAfterValue": "100000",
1375 "UMask": "0x1"
1376 },
1377 {
1378 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
1379 "Counter": "0,1,2,3",
1380 "EventCode": "0xB7, 0xBB",
1381 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1382 "MSRIndex": "0x1a6,0x1a7",
1383 "MSRValue": "0xff08",
1384 "Offcore": "1",
1385 "SampleAfterValue": "100000",
1386 "UMask": "0x1"
1387 },
1388 {
1389 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
1390 "Counter": "0,1,2,3",
1391 "EventCode": "0xB7, 0xBB",
1392 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1393 "MSRIndex": "0x1a6,0x1a7",
1394 "MSRValue": "0x8008",
1395 "Offcore": "1",
1396 "SampleAfterValue": "100000",
1397 "UMask": "0x1"
1398 },
1399 {
1400 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1401 "Counter": "0,1,2,3",
1402 "EventCode": "0xB7, 0xBB",
1403 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1404 "MSRIndex": "0x1a6,0x1a7",
1405 "MSRValue": "0x108",
1406 "Offcore": "1",
1407 "SampleAfterValue": "100000",
1408 "UMask": "0x1"
1409 },
1410 {
1411 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1412 "Counter": "0,1,2,3",
1413 "EventCode": "0xB7, 0xBB",
1414 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
1415 "MSRIndex": "0x1a6,0x1a7",
1416 "MSRValue": "0x208",
1417 "Offcore": "1",
1418 "SampleAfterValue": "100000",
1419 "UMask": "0x1"
1420 },
1421 {
1422 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1423 "Counter": "0,1,2,3",
1424 "EventCode": "0xB7, 0xBB",
1425 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1426 "MSRIndex": "0x1a6,0x1a7",
1427 "MSRValue": "0x408",
1428 "Offcore": "1",
1429 "SampleAfterValue": "100000",
1430 "UMask": "0x1"
1431 },
1432 {
1433 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
1434 "Counter": "0,1,2,3",
1435 "EventCode": "0xB7, 0xBB",
1436 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1437 "MSRIndex": "0x1a6,0x1a7",
1438 "MSRValue": "0x708",
1439 "Offcore": "1",
1440 "SampleAfterValue": "100000",
1441 "UMask": "0x1"
1442 },
1443 {
1444 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1445 "Counter": "0,1,2,3",
1446 "EventCode": "0xB7, 0xBB",
1447 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1448 "MSRIndex": "0x1a6,0x1a7",
1449 "MSRValue": "0x1008",
1450 "Offcore": "1",
1451 "SampleAfterValue": "100000",
1452 "UMask": "0x1"
1453 },
1454 {
1455 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
1456 "Counter": "0,1,2,3",
1457 "EventCode": "0xB7, 0xBB",
1458 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1459 "MSRIndex": "0x1a6,0x1a7",
1460 "MSRValue": "0x808",
1461 "Offcore": "1",
1462 "SampleAfterValue": "100000",
1463 "UMask": "0x1"
1464 },
1465 {
1466 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1467 "Counter": "0,1,2,3",
1468 "EventCode": "0xB7, 0xBB",
1469 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1470 "MSRIndex": "0x1a6,0x1a7",
1471 "MSRValue": "0x5077",
1472 "Offcore": "1",
1473 "SampleAfterValue": "100000",
1474 "UMask": "0x1"
1475 },
1476 {
1477 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1478 "Counter": "0,1,2,3",
1479 "EventCode": "0xB7, 0xBB",
1480 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1481 "MSRIndex": "0x1a6,0x1a7",
1482 "MSRValue": "0x7f77",
1483 "Offcore": "1",
1484 "SampleAfterValue": "100000",
1485 "UMask": "0x1"
1486 },
1487 {
1488 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
1489 "Counter": "0,1,2,3",
1490 "EventCode": "0xB7, 0xBB",
1491 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1492 "MSRIndex": "0x1a6,0x1a7",
1493 "MSRValue": "0xff77",
1494 "Offcore": "1",
1495 "SampleAfterValue": "100000",
1496 "UMask": "0x1"
1497 },
1498 {
1499 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
1500 "Counter": "0,1,2,3",
1501 "EventCode": "0xB7, 0xBB",
1502 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1503 "MSRIndex": "0x1a6,0x1a7",
1504 "MSRValue": "0x8077",
1505 "Offcore": "1",
1506 "SampleAfterValue": "100000",
1507 "UMask": "0x1"
1508 },
1509 {
1510 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1511 "Counter": "0,1,2,3",
1512 "EventCode": "0xB7, 0xBB",
1513 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1514 "MSRIndex": "0x1a6,0x1a7",
1515 "MSRValue": "0x177",
1516 "Offcore": "1",
1517 "SampleAfterValue": "100000",
1518 "UMask": "0x1"
1519 },
1520 {
1521 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1522 "Counter": "0,1,2,3",
1523 "EventCode": "0xB7, 0xBB",
1524 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1525 "MSRIndex": "0x1a6,0x1a7",
1526 "MSRValue": "0x277",
1527 "Offcore": "1",
1528 "SampleAfterValue": "100000",
1529 "UMask": "0x1"
1530 },
1531 {
1532 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1533 "Counter": "0,1,2,3",
1534 "EventCode": "0xB7, 0xBB",
1535 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1536 "MSRIndex": "0x1a6,0x1a7",
1537 "MSRValue": "0x477",
1538 "Offcore": "1",
1539 "SampleAfterValue": "100000",
1540 "UMask": "0x1"
1541 },
1542 {
1543 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
1544 "Counter": "0,1,2,3",
1545 "EventCode": "0xB7, 0xBB",
1546 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1547 "MSRIndex": "0x1a6,0x1a7",
1548 "MSRValue": "0x777",
1549 "Offcore": "1",
1550 "SampleAfterValue": "100000",
1551 "UMask": "0x1"
1552 },
1553 {
1554 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1555 "Counter": "0,1,2,3",
1556 "EventCode": "0xB7, 0xBB",
1557 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1558 "MSRIndex": "0x1a6,0x1a7",
1559 "MSRValue": "0x1077",
1560 "Offcore": "1",
1561 "SampleAfterValue": "100000",
1562 "UMask": "0x1"
1563 },
1564 {
1565 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1566 "Counter": "0,1,2,3",
1567 "EventCode": "0xB7, 0xBB",
1568 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1569 "MSRIndex": "0x1a6,0x1a7",
1570 "MSRValue": "0x877",
1571 "Offcore": "1",
1572 "SampleAfterValue": "100000",
1573 "UMask": "0x1"
1574 },
1575 {
1576 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1577 "Counter": "0,1,2,3",
1578 "EventCode": "0xB7, 0xBB",
1579 "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1580 "MSRIndex": "0x1a6,0x1a7",
1581 "MSRValue": "0x5033",
1582 "Offcore": "1",
1583 "SampleAfterValue": "100000",
1584 "UMask": "0x1"
1585 },
1586 {
1587 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
1588 "Counter": "0,1,2,3",
1589 "EventCode": "0xB7, 0xBB",
1590 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1591 "MSRIndex": "0x1a6,0x1a7",
1592 "MSRValue": "0x7f33",
1593 "Offcore": "1",
1594 "SampleAfterValue": "100000",
1595 "UMask": "0x1"
1596 },
1597 {
1598 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
1599 "Counter": "0,1,2,3",
1600 "EventCode": "0xB7, 0xBB",
1601 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1602 "MSRIndex": "0x1a6,0x1a7",
1603 "MSRValue": "0xff33",
1604 "Offcore": "1",
1605 "SampleAfterValue": "100000",
1606 "UMask": "0x1"
1607 },
1608 {
1609 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
1610 "Counter": "0,1,2,3",
1611 "EventCode": "0xB7, 0xBB",
1612 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1613 "MSRIndex": "0x1a6,0x1a7",
1614 "MSRValue": "0x8033",
1615 "Offcore": "1",
1616 "SampleAfterValue": "100000",
1617 "UMask": "0x1"
1618 },
1619 {
1620 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1621 "Counter": "0,1,2,3",
1622 "EventCode": "0xB7, 0xBB",
1623 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1624 "MSRIndex": "0x1a6,0x1a7",
1625 "MSRValue": "0x133",
1626 "Offcore": "1",
1627 "SampleAfterValue": "100000",
1628 "UMask": "0x1"
1629 },
1630 {
1631 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1632 "Counter": "0,1,2,3",
1633 "EventCode": "0xB7, 0xBB",
1634 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1635 "MSRIndex": "0x1a6,0x1a7",
1636 "MSRValue": "0x233",
1637 "Offcore": "1",
1638 "SampleAfterValue": "100000",
1639 "UMask": "0x1"
1640 },
1641 {
1642 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1643 "Counter": "0,1,2,3",
1644 "EventCode": "0xB7, 0xBB",
1645 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1646 "MSRIndex": "0x1a6,0x1a7",
1647 "MSRValue": "0x433",
1648 "Offcore": "1",
1649 "SampleAfterValue": "100000",
1650 "UMask": "0x1"
1651 },
1652 {
1653 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
1654 "Counter": "0,1,2,3",
1655 "EventCode": "0xB7, 0xBB",
1656 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1657 "MSRIndex": "0x1a6,0x1a7",
1658 "MSRValue": "0x733",
1659 "Offcore": "1",
1660 "SampleAfterValue": "100000",
1661 "UMask": "0x1"
1662 },
1663 {
1664 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1665 "Counter": "0,1,2,3",
1666 "EventCode": "0xB7, 0xBB",
1667 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1668 "MSRIndex": "0x1a6,0x1a7",
1669 "MSRValue": "0x1033",
1670 "Offcore": "1",
1671 "SampleAfterValue": "100000",
1672 "UMask": "0x1"
1673 },
1674 {
1675 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
1676 "Counter": "0,1,2,3",
1677 "EventCode": "0xB7, 0xBB",
1678 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1679 "MSRIndex": "0x1a6,0x1a7",
1680 "MSRValue": "0x833",
1681 "Offcore": "1",
1682 "SampleAfterValue": "100000",
1683 "UMask": "0x1"
1684 },
1685 {
1686 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1687 "Counter": "0,1,2,3",
1688 "EventCode": "0xB7, 0xBB",
1689 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1690 "MSRIndex": "0x1a6,0x1a7",
1691 "MSRValue": "0x5003",
1692 "Offcore": "1",
1693 "SampleAfterValue": "100000",
1694 "UMask": "0x1"
1695 },
1696 {
1697 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
1698 "Counter": "0,1,2,3",
1699 "EventCode": "0xB7, 0xBB",
1700 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1701 "MSRIndex": "0x1a6,0x1a7",
1702 "MSRValue": "0x7f03",
1703 "Offcore": "1",
1704 "SampleAfterValue": "100000",
1705 "UMask": "0x1"
1706 },
1707 {
1708 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
1709 "Counter": "0,1,2,3",
1710 "EventCode": "0xB7, 0xBB",
1711 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1712 "MSRIndex": "0x1a6,0x1a7",
1713 "MSRValue": "0xff03",
1714 "Offcore": "1",
1715 "SampleAfterValue": "100000",
1716 "UMask": "0x1"
1717 },
1718 {
1719 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
1720 "Counter": "0,1,2,3",
1721 "EventCode": "0xB7, 0xBB",
1722 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1723 "MSRIndex": "0x1a6,0x1a7",
1724 "MSRValue": "0x8003",
1725 "Offcore": "1",
1726 "SampleAfterValue": "100000",
1727 "UMask": "0x1"
1728 },
1729 {
1730 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1731 "Counter": "0,1,2,3",
1732 "EventCode": "0xB7, 0xBB",
1733 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1734 "MSRIndex": "0x1a6,0x1a7",
1735 "MSRValue": "0x103",
1736 "Offcore": "1",
1737 "SampleAfterValue": "100000",
1738 "UMask": "0x1"
1739 },
1740 {
1741 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1742 "Counter": "0,1,2,3",
1743 "EventCode": "0xB7, 0xBB",
1744 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1745 "MSRIndex": "0x1a6,0x1a7",
1746 "MSRValue": "0x203",
1747 "Offcore": "1",
1748 "SampleAfterValue": "100000",
1749 "UMask": "0x1"
1750 },
1751 {
1752 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1753 "Counter": "0,1,2,3",
1754 "EventCode": "0xB7, 0xBB",
1755 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1756 "MSRIndex": "0x1a6,0x1a7",
1757 "MSRValue": "0x403",
1758 "Offcore": "1",
1759 "SampleAfterValue": "100000",
1760 "UMask": "0x1"
1761 },
1762 {
1763 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
1764 "Counter": "0,1,2,3",
1765 "EventCode": "0xB7, 0xBB",
1766 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1767 "MSRIndex": "0x1a6,0x1a7",
1768 "MSRValue": "0x703",
1769 "Offcore": "1",
1770 "SampleAfterValue": "100000",
1771 "UMask": "0x1"
1772 },
1773 {
1774 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1775 "Counter": "0,1,2,3",
1776 "EventCode": "0xB7, 0xBB",
1777 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1778 "MSRIndex": "0x1a6,0x1a7",
1779 "MSRValue": "0x1003",
1780 "Offcore": "1",
1781 "SampleAfterValue": "100000",
1782 "UMask": "0x1"
1783 },
1784 {
1785 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
1786 "Counter": "0,1,2,3",
1787 "EventCode": "0xB7, 0xBB",
1788 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1789 "MSRIndex": "0x1a6,0x1a7",
1790 "MSRValue": "0x803",
1791 "Offcore": "1",
1792 "SampleAfterValue": "100000",
1793 "UMask": "0x1"
1794 },
1795 {
1796 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1797 "Counter": "0,1,2,3",
1798 "EventCode": "0xB7, 0xBB",
1799 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1800 "MSRIndex": "0x1a6,0x1a7",
1801 "MSRValue": "0x5001",
1802 "Offcore": "1",
1803 "SampleAfterValue": "100000",
1804 "UMask": "0x1"
1805 },
1806 {
1807 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1808 "Counter": "0,1,2,3",
1809 "EventCode": "0xB7, 0xBB",
1810 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1811 "MSRIndex": "0x1a6,0x1a7",
1812 "MSRValue": "0x7f01",
1813 "Offcore": "1",
1814 "SampleAfterValue": "100000",
1815 "UMask": "0x1"
1816 },
1817 {
1818 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
1819 "Counter": "0,1,2,3",
1820 "EventCode": "0xB7, 0xBB",
1821 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1822 "MSRIndex": "0x1a6,0x1a7",
1823 "MSRValue": "0xff01",
1824 "Offcore": "1",
1825 "SampleAfterValue": "100000",
1826 "UMask": "0x1"
1827 },
1828 {
1829 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
1830 "Counter": "0,1,2,3",
1831 "EventCode": "0xB7, 0xBB",
1832 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1833 "MSRIndex": "0x1a6,0x1a7",
1834 "MSRValue": "0x8001",
1835 "Offcore": "1",
1836 "SampleAfterValue": "100000",
1837 "UMask": "0x1"
1838 },
1839 {
1840 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1841 "Counter": "0,1,2,3",
1842 "EventCode": "0xB7, 0xBB",
1843 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1844 "MSRIndex": "0x1a6,0x1a7",
1845 "MSRValue": "0x101",
1846 "Offcore": "1",
1847 "SampleAfterValue": "100000",
1848 "UMask": "0x1"
1849 },
1850 {
1851 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1852 "Counter": "0,1,2,3",
1853 "EventCode": "0xB7, 0xBB",
1854 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1855 "MSRIndex": "0x1a6,0x1a7",
1856 "MSRValue": "0x201",
1857 "Offcore": "1",
1858 "SampleAfterValue": "100000",
1859 "UMask": "0x1"
1860 },
1861 {
1862 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1863 "Counter": "0,1,2,3",
1864 "EventCode": "0xB7, 0xBB",
1865 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1866 "MSRIndex": "0x1a6,0x1a7",
1867 "MSRValue": "0x401",
1868 "Offcore": "1",
1869 "SampleAfterValue": "100000",
1870 "UMask": "0x1"
1871 },
1872 {
1873 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
1874 "Counter": "0,1,2,3",
1875 "EventCode": "0xB7, 0xBB",
1876 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1877 "MSRIndex": "0x1a6,0x1a7",
1878 "MSRValue": "0x701",
1879 "Offcore": "1",
1880 "SampleAfterValue": "100000",
1881 "UMask": "0x1"
1882 },
1883 {
1884 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1885 "Counter": "0,1,2,3",
1886 "EventCode": "0xB7, 0xBB",
1887 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1888 "MSRIndex": "0x1a6,0x1a7",
1889 "MSRValue": "0x1001",
1890 "Offcore": "1",
1891 "SampleAfterValue": "100000",
1892 "UMask": "0x1"
1893 },
1894 {
1895 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
1896 "Counter": "0,1,2,3",
1897 "EventCode": "0xB7, 0xBB",
1898 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1899 "MSRIndex": "0x1a6,0x1a7",
1900 "MSRValue": "0x801",
1901 "Offcore": "1",
1902 "SampleAfterValue": "100000",
1903 "UMask": "0x1"
1904 },
1905 {
1906 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1907 "Counter": "0,1,2,3",
1908 "EventCode": "0xB7, 0xBB",
1909 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1910 "MSRIndex": "0x1a6,0x1a7",
1911 "MSRValue": "0x5004",
1912 "Offcore": "1",
1913 "SampleAfterValue": "100000",
1914 "UMask": "0x1"
1915 },
1916 {
1917 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1918 "Counter": "0,1,2,3",
1919 "EventCode": "0xB7, 0xBB",
1920 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
1921 "MSRIndex": "0x1a6,0x1a7",
1922 "MSRValue": "0x7f04",
1923 "Offcore": "1",
1924 "SampleAfterValue": "100000",
1925 "UMask": "0x1"
1926 },
1927 {
1928 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
1929 "Counter": "0,1,2,3",
1930 "EventCode": "0xB7, 0xBB",
1931 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
1932 "MSRIndex": "0x1a6,0x1a7",
1933 "MSRValue": "0xff04",
1934 "Offcore": "1",
1935 "SampleAfterValue": "100000",
1936 "UMask": "0x1"
1937 },
1938 {
1939 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
1940 "Counter": "0,1,2,3",
1941 "EventCode": "0xB7, 0xBB",
1942 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
1943 "MSRIndex": "0x1a6,0x1a7",
1944 "MSRValue": "0x8004",
1945 "Offcore": "1",
1946 "SampleAfterValue": "100000",
1947 "UMask": "0x1"
1948 },
1949 {
1950 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1951 "Counter": "0,1,2,3",
1952 "EventCode": "0xB7, 0xBB",
1953 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
1954 "MSRIndex": "0x1a6,0x1a7",
1955 "MSRValue": "0x104",
1956 "Offcore": "1",
1957 "SampleAfterValue": "100000",
1958 "UMask": "0x1"
1959 },
1960 {
1961 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1962 "Counter": "0,1,2,3",
1963 "EventCode": "0xB7, 0xBB",
1964 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1965 "MSRIndex": "0x1a6,0x1a7",
1966 "MSRValue": "0x204",
1967 "Offcore": "1",
1968 "SampleAfterValue": "100000",
1969 "UMask": "0x1"
1970 },
1971 {
1972 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1973 "Counter": "0,1,2,3",
1974 "EventCode": "0xB7, 0xBB",
1975 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1976 "MSRIndex": "0x1a6,0x1a7",
1977 "MSRValue": "0x404",
1978 "Offcore": "1",
1979 "SampleAfterValue": "100000",
1980 "UMask": "0x1"
1981 },
1982 {
1983 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
1984 "Counter": "0,1,2,3",
1985 "EventCode": "0xB7, 0xBB",
1986 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
1987 "MSRIndex": "0x1a6,0x1a7",
1988 "MSRValue": "0x704",
1989 "Offcore": "1",
1990 "SampleAfterValue": "100000",
1991 "UMask": "0x1"
1992 },
1993 {
1994 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1995 "Counter": "0,1,2,3",
1996 "EventCode": "0xB7, 0xBB",
1997 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1998 "MSRIndex": "0x1a6,0x1a7",
1999 "MSRValue": "0x1004",
2000 "Offcore": "1",
2001 "SampleAfterValue": "100000",
2002 "UMask": "0x1"
2003 },
2004 {
2005 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2006 "Counter": "0,1,2,3",
2007 "EventCode": "0xB7, 0xBB",
2008 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2009 "MSRIndex": "0x1a6,0x1a7",
2010 "MSRValue": "0x804",
2011 "Offcore": "1",
2012 "SampleAfterValue": "100000",
2013 "UMask": "0x1"
2014 },
2015 {
2016 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2017 "Counter": "0,1,2,3",
2018 "EventCode": "0xB7, 0xBB",
2019 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2020 "MSRIndex": "0x1a6,0x1a7",
2021 "MSRValue": "0x5002",
2022 "Offcore": "1",
2023 "SampleAfterValue": "100000",
2024 "UMask": "0x1"
2025 },
2026 {
2027 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
2028 "Counter": "0,1,2,3",
2029 "EventCode": "0xB7, 0xBB",
2030 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2031 "MSRIndex": "0x1a6,0x1a7",
2032 "MSRValue": "0x7f02",
2033 "Offcore": "1",
2034 "SampleAfterValue": "100000",
2035 "UMask": "0x1"
2036 },
2037 {
2038 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
2039 "Counter": "0,1,2,3",
2040 "EventCode": "0xB7, 0xBB",
2041 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2042 "MSRIndex": "0x1a6,0x1a7",
2043 "MSRValue": "0xff02",
2044 "Offcore": "1",
2045 "SampleAfterValue": "100000",
2046 "UMask": "0x1"
2047 },
2048 {
2049 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
2050 "Counter": "0,1,2,3",
2051 "EventCode": "0xB7, 0xBB",
2052 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2053 "MSRIndex": "0x1a6,0x1a7",
2054 "MSRValue": "0x8002",
2055 "Offcore": "1",
2056 "SampleAfterValue": "100000",
2057 "UMask": "0x1"
2058 },
2059 {
2060 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2061 "Counter": "0,1,2,3",
2062 "EventCode": "0xB7, 0xBB",
2063 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2064 "MSRIndex": "0x1a6,0x1a7",
2065 "MSRValue": "0x102",
2066 "Offcore": "1",
2067 "SampleAfterValue": "100000",
2068 "UMask": "0x1"
2069 },
2070 {
2071 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2072 "Counter": "0,1,2,3",
2073 "EventCode": "0xB7, 0xBB",
2074 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2075 "MSRIndex": "0x1a6,0x1a7",
2076 "MSRValue": "0x202",
2077 "Offcore": "1",
2078 "SampleAfterValue": "100000",
2079 "UMask": "0x1"
2080 },
2081 {
2082 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2083 "Counter": "0,1,2,3",
2084 "EventCode": "0xB7, 0xBB",
2085 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2086 "MSRIndex": "0x1a6,0x1a7",
2087 "MSRValue": "0x402",
2088 "Offcore": "1",
2089 "SampleAfterValue": "100000",
2090 "UMask": "0x1"
2091 },
2092 {
2093 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
2094 "Counter": "0,1,2,3",
2095 "EventCode": "0xB7, 0xBB",
2096 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2097 "MSRIndex": "0x1a6,0x1a7",
2098 "MSRValue": "0x702",
2099 "Offcore": "1",
2100 "SampleAfterValue": "100000",
2101 "UMask": "0x1"
2102 },
2103 {
2104 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2105 "Counter": "0,1,2,3",
2106 "EventCode": "0xB7, 0xBB",
2107 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2108 "MSRIndex": "0x1a6,0x1a7",
2109 "MSRValue": "0x1002",
2110 "Offcore": "1",
2111 "SampleAfterValue": "100000",
2112 "UMask": "0x1"
2113 },
2114 {
2115 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
2116 "Counter": "0,1,2,3",
2117 "EventCode": "0xB7, 0xBB",
2118 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2119 "MSRIndex": "0x1a6,0x1a7",
2120 "MSRValue": "0x802",
2121 "Offcore": "1",
2122 "SampleAfterValue": "100000",
2123 "UMask": "0x1"
2124 },
2125 {
2126 "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2127 "Counter": "0,1,2,3",
2128 "EventCode": "0xB7, 0xBB",
2129 "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2130 "MSRIndex": "0x1a6,0x1a7",
2131 "MSRValue": "0x5080",
2132 "Offcore": "1",
2133 "SampleAfterValue": "100000",
2134 "UMask": "0x1"
2135 },
2136 {
2137 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
2138 "Counter": "0,1,2,3",
2139 "EventCode": "0xB7, 0xBB",
2140 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2141 "MSRIndex": "0x1a6,0x1a7",
2142 "MSRValue": "0x7f80",
2143 "Offcore": "1",
2144 "SampleAfterValue": "100000",
2145 "UMask": "0x1"
2146 },
2147 {
2148 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
2149 "Counter": "0,1,2,3",
2150 "EventCode": "0xB7, 0xBB",
2151 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2152 "MSRIndex": "0x1a6,0x1a7",
2153 "MSRValue": "0xff80",
2154 "Offcore": "1",
2155 "SampleAfterValue": "100000",
2156 "UMask": "0x1"
2157 },
2158 {
2159 "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
2160 "Counter": "0,1,2,3",
2161 "EventCode": "0xB7, 0xBB",
2162 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2163 "MSRIndex": "0x1a6,0x1a7",
2164 "MSRValue": "0x8080",
2165 "Offcore": "1",
2166 "SampleAfterValue": "100000",
2167 "UMask": "0x1"
2168 },
2169 {
2170 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2171 "Counter": "0,1,2,3",
2172 "EventCode": "0xB7, 0xBB",
2173 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2174 "MSRIndex": "0x1a6,0x1a7",
2175 "MSRValue": "0x180",
2176 "Offcore": "1",
2177 "SampleAfterValue": "100000",
2178 "UMask": "0x1"
2179 },
2180 {
2181 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2182 "Counter": "0,1,2,3",
2183 "EventCode": "0xB7, 0xBB",
2184 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2185 "MSRIndex": "0x1a6,0x1a7",
2186 "MSRValue": "0x280",
2187 "Offcore": "1",
2188 "SampleAfterValue": "100000",
2189 "UMask": "0x1"
2190 },
2191 {
2192 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2193 "Counter": "0,1,2,3",
2194 "EventCode": "0xB7, 0xBB",
2195 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2196 "MSRIndex": "0x1a6,0x1a7",
2197 "MSRValue": "0x480",
2198 "Offcore": "1",
2199 "SampleAfterValue": "100000",
2200 "UMask": "0x1"
2201 },
2202 {
2203 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
2204 "Counter": "0,1,2,3",
2205 "EventCode": "0xB7, 0xBB",
2206 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2207 "MSRIndex": "0x1a6,0x1a7",
2208 "MSRValue": "0x780",
2209 "Offcore": "1",
2210 "SampleAfterValue": "100000",
2211 "UMask": "0x1"
2212 },
2213 {
2214 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2215 "Counter": "0,1,2,3",
2216 "EventCode": "0xB7, 0xBB",
2217 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2218 "MSRIndex": "0x1a6,0x1a7",
2219 "MSRValue": "0x1080",
2220 "Offcore": "1",
2221 "SampleAfterValue": "100000",
2222 "UMask": "0x1"
2223 },
2224 {
2225 "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
2226 "Counter": "0,1,2,3",
2227 "EventCode": "0xB7, 0xBB",
2228 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2229 "MSRIndex": "0x1a6,0x1a7",
2230 "MSRValue": "0x880",
2231 "Offcore": "1",
2232 "SampleAfterValue": "100000",
2233 "UMask": "0x1"
2234 },
2235 {
2236 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2237 "Counter": "0,1,2,3",
2238 "EventCode": "0xB7, 0xBB",
2239 "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2240 "MSRIndex": "0x1a6,0x1a7",
2241 "MSRValue": "0x5050",
2242 "Offcore": "1",
2243 "SampleAfterValue": "100000",
2244 "UMask": "0x1"
2245 },
2246 {
2247 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
2248 "Counter": "0,1,2,3",
2249 "EventCode": "0xB7, 0xBB",
2250 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2251 "MSRIndex": "0x1a6,0x1a7",
2252 "MSRValue": "0x7f50",
2253 "Offcore": "1",
2254 "SampleAfterValue": "100000",
2255 "UMask": "0x1"
2256 },
2257 {
2258 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
2259 "Counter": "0,1,2,3",
2260 "EventCode": "0xB7, 0xBB",
2261 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2262 "MSRIndex": "0x1a6,0x1a7",
2263 "MSRValue": "0xff50",
2264 "Offcore": "1",
2265 "SampleAfterValue": "100000",
2266 "UMask": "0x1"
2267 },
2268 {
2269 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
2270 "Counter": "0,1,2,3",
2271 "EventCode": "0xB7, 0xBB",
2272 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2273 "MSRIndex": "0x1a6,0x1a7",
2274 "MSRValue": "0x8050",
2275 "Offcore": "1",
2276 "SampleAfterValue": "100000",
2277 "UMask": "0x1"
2278 },
2279 {
2280 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2281 "Counter": "0,1,2,3",
2282 "EventCode": "0xB7, 0xBB",
2283 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2284 "MSRIndex": "0x1a6,0x1a7",
2285 "MSRValue": "0x150",
2286 "Offcore": "1",
2287 "SampleAfterValue": "100000",
2288 "UMask": "0x1"
2289 },
2290 {
2291 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2292 "Counter": "0,1,2,3",
2293 "EventCode": "0xB7, 0xBB",
2294 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2295 "MSRIndex": "0x1a6,0x1a7",
2296 "MSRValue": "0x250",
2297 "Offcore": "1",
2298 "SampleAfterValue": "100000",
2299 "UMask": "0x1"
2300 },
2301 {
2302 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2303 "Counter": "0,1,2,3",
2304 "EventCode": "0xB7, 0xBB",
2305 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2306 "MSRIndex": "0x1a6,0x1a7",
2307 "MSRValue": "0x450",
2308 "Offcore": "1",
2309 "SampleAfterValue": "100000",
2310 "UMask": "0x1"
2311 },
2312 {
2313 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
2314 "Counter": "0,1,2,3",
2315 "EventCode": "0xB7, 0xBB",
2316 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2317 "MSRIndex": "0x1a6,0x1a7",
2318 "MSRValue": "0x750",
2319 "Offcore": "1",
2320 "SampleAfterValue": "100000",
2321 "UMask": "0x1"
2322 },
2323 {
2324 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2325 "Counter": "0,1,2,3",
2326 "EventCode": "0xB7, 0xBB",
2327 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2328 "MSRIndex": "0x1a6,0x1a7",
2329 "MSRValue": "0x1050",
2330 "Offcore": "1",
2331 "SampleAfterValue": "100000",
2332 "UMask": "0x1"
2333 },
2334 {
2335 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
2336 "Counter": "0,1,2,3",
2337 "EventCode": "0xB7, 0xBB",
2338 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2339 "MSRIndex": "0x1a6,0x1a7",
2340 "MSRValue": "0x850",
2341 "Offcore": "1",
2342 "SampleAfterValue": "100000",
2343 "UMask": "0x1"
2344 },
2345 {
2346 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2347 "Counter": "0,1,2,3",
2348 "EventCode": "0xB7, 0xBB",
2349 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2350 "MSRIndex": "0x1a6,0x1a7",
2351 "MSRValue": "0x5010",
2352 "Offcore": "1",
2353 "SampleAfterValue": "100000",
2354 "UMask": "0x1"
2355 },
2356 {
2357 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
2358 "Counter": "0,1,2,3",
2359 "EventCode": "0xB7, 0xBB",
2360 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2361 "MSRIndex": "0x1a6,0x1a7",
2362 "MSRValue": "0x7f10",
2363 "Offcore": "1",
2364 "SampleAfterValue": "100000",
2365 "UMask": "0x1"
2366 },
2367 {
2368 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
2369 "Counter": "0,1,2,3",
2370 "EventCode": "0xB7, 0xBB",
2371 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2372 "MSRIndex": "0x1a6,0x1a7",
2373 "MSRValue": "0xff10",
2374 "Offcore": "1",
2375 "SampleAfterValue": "100000",
2376 "UMask": "0x1"
2377 },
2378 {
2379 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
2380 "Counter": "0,1,2,3",
2381 "EventCode": "0xB7, 0xBB",
2382 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2383 "MSRIndex": "0x1a6,0x1a7",
2384 "MSRValue": "0x8010",
2385 "Offcore": "1",
2386 "SampleAfterValue": "100000",
2387 "UMask": "0x1"
2388 },
2389 {
2390 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2391 "Counter": "0,1,2,3",
2392 "EventCode": "0xB7, 0xBB",
2393 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2394 "MSRIndex": "0x1a6,0x1a7",
2395 "MSRValue": "0x110",
2396 "Offcore": "1",
2397 "SampleAfterValue": "100000",
2398 "UMask": "0x1"
2399 },
2400 {
2401 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2402 "Counter": "0,1,2,3",
2403 "EventCode": "0xB7, 0xBB",
2404 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2405 "MSRIndex": "0x1a6,0x1a7",
2406 "MSRValue": "0x210",
2407 "Offcore": "1",
2408 "SampleAfterValue": "100000",
2409 "UMask": "0x1"
2410 },
2411 {
2412 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2413 "Counter": "0,1,2,3",
2414 "EventCode": "0xB7, 0xBB",
2415 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2416 "MSRIndex": "0x1a6,0x1a7",
2417 "MSRValue": "0x410",
2418 "Offcore": "1",
2419 "SampleAfterValue": "100000",
2420 "UMask": "0x1"
2421 },
2422 {
2423 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
2424 "Counter": "0,1,2,3",
2425 "EventCode": "0xB7, 0xBB",
2426 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2427 "MSRIndex": "0x1a6,0x1a7",
2428 "MSRValue": "0x710",
2429 "Offcore": "1",
2430 "SampleAfterValue": "100000",
2431 "UMask": "0x1"
2432 },
2433 {
2434 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2435 "Counter": "0,1,2,3",
2436 "EventCode": "0xB7, 0xBB",
2437 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2438 "MSRIndex": "0x1a6,0x1a7",
2439 "MSRValue": "0x1010",
2440 "Offcore": "1",
2441 "SampleAfterValue": "100000",
2442 "UMask": "0x1"
2443 },
2444 {
2445 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
2446 "Counter": "0,1,2,3",
2447 "EventCode": "0xB7, 0xBB",
2448 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2449 "MSRIndex": "0x1a6,0x1a7",
2450 "MSRValue": "0x810",
2451 "Offcore": "1",
2452 "SampleAfterValue": "100000",
2453 "UMask": "0x1"
2454 },
2455 {
2456 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2457 "Counter": "0,1,2,3",
2458 "EventCode": "0xB7, 0xBB",
2459 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2460 "MSRIndex": "0x1a6,0x1a7",
2461 "MSRValue": "0x5040",
2462 "Offcore": "1",
2463 "SampleAfterValue": "100000",
2464 "UMask": "0x1"
2465 },
2466 {
2467 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
2468 "Counter": "0,1,2,3",
2469 "EventCode": "0xB7, 0xBB",
2470 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2471 "MSRIndex": "0x1a6,0x1a7",
2472 "MSRValue": "0x7f40",
2473 "Offcore": "1",
2474 "SampleAfterValue": "100000",
2475 "UMask": "0x1"
2476 },
2477 {
2478 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
2479 "Counter": "0,1,2,3",
2480 "EventCode": "0xB7, 0xBB",
2481 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2482 "MSRIndex": "0x1a6,0x1a7",
2483 "MSRValue": "0xff40",
2484 "Offcore": "1",
2485 "SampleAfterValue": "100000",
2486 "UMask": "0x1"
2487 },
2488 {
2489 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
2490 "Counter": "0,1,2,3",
2491 "EventCode": "0xB7, 0xBB",
2492 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2493 "MSRIndex": "0x1a6,0x1a7",
2494 "MSRValue": "0x8040",
2495 "Offcore": "1",
2496 "SampleAfterValue": "100000",
2497 "UMask": "0x1"
2498 },
2499 {
2500 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2501 "Counter": "0,1,2,3",
2502 "EventCode": "0xB7, 0xBB",
2503 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2504 "MSRIndex": "0x1a6,0x1a7",
2505 "MSRValue": "0x140",
2506 "Offcore": "1",
2507 "SampleAfterValue": "100000",
2508 "UMask": "0x1"
2509 },
2510 {
2511 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2512 "Counter": "0,1,2,3",
2513 "EventCode": "0xB7, 0xBB",
2514 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2515 "MSRIndex": "0x1a6,0x1a7",
2516 "MSRValue": "0x240",
2517 "Offcore": "1",
2518 "SampleAfterValue": "100000",
2519 "UMask": "0x1"
2520 },
2521 {
2522 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2523 "Counter": "0,1,2,3",
2524 "EventCode": "0xB7, 0xBB",
2525 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2526 "MSRIndex": "0x1a6,0x1a7",
2527 "MSRValue": "0x440",
2528 "Offcore": "1",
2529 "SampleAfterValue": "100000",
2530 "UMask": "0x1"
2531 },
2532 {
2533 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
2534 "Counter": "0,1,2,3",
2535 "EventCode": "0xB7, 0xBB",
2536 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2537 "MSRIndex": "0x1a6,0x1a7",
2538 "MSRValue": "0x740",
2539 "Offcore": "1",
2540 "SampleAfterValue": "100000",
2541 "UMask": "0x1"
2542 },
2543 {
2544 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2545 "Counter": "0,1,2,3",
2546 "EventCode": "0xB7, 0xBB",
2547 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2548 "MSRIndex": "0x1a6,0x1a7",
2549 "MSRValue": "0x1040",
2550 "Offcore": "1",
2551 "SampleAfterValue": "100000",
2552 "UMask": "0x1"
2553 },
2554 {
2555 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
2556 "Counter": "0,1,2,3",
2557 "EventCode": "0xB7, 0xBB",
2558 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2559 "MSRIndex": "0x1a6,0x1a7",
2560 "MSRValue": "0x840",
2561 "Offcore": "1",
2562 "SampleAfterValue": "100000",
2563 "UMask": "0x1"
2564 },
2565 {
2566 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2567 "Counter": "0,1,2,3",
2568 "EventCode": "0xB7, 0xBB",
2569 "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2570 "MSRIndex": "0x1a6,0x1a7",
2571 "MSRValue": "0x5020",
2572 "Offcore": "1",
2573 "SampleAfterValue": "100000",
2574 "UMask": "0x1"
2575 },
2576 {
2577 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
2578 "Counter": "0,1,2,3",
2579 "EventCode": "0xB7, 0xBB",
2580 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2581 "MSRIndex": "0x1a6,0x1a7",
2582 "MSRValue": "0x7f20",
2583 "Offcore": "1",
2584 "SampleAfterValue": "100000",
2585 "UMask": "0x1"
2586 },
2587 {
2588 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
2589 "Counter": "0,1,2,3",
2590 "EventCode": "0xB7, 0xBB",
2591 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2592 "MSRIndex": "0x1a6,0x1a7",
2593 "MSRValue": "0xff20",
2594 "Offcore": "1",
2595 "SampleAfterValue": "100000",
2596 "UMask": "0x1"
2597 },
2598 {
2599 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
2600 "Counter": "0,1,2,3",
2601 "EventCode": "0xB7, 0xBB",
2602 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2603 "MSRIndex": "0x1a6,0x1a7",
2604 "MSRValue": "0x8020",
2605 "Offcore": "1",
2606 "SampleAfterValue": "100000",
2607 "UMask": "0x1"
2608 },
2609 {
2610 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2611 "Counter": "0,1,2,3",
2612 "EventCode": "0xB7, 0xBB",
2613 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2614 "MSRIndex": "0x1a6,0x1a7",
2615 "MSRValue": "0x120",
2616 "Offcore": "1",
2617 "SampleAfterValue": "100000",
2618 "UMask": "0x1"
2619 },
2620 {
2621 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2622 "Counter": "0,1,2,3",
2623 "EventCode": "0xB7, 0xBB",
2624 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2625 "MSRIndex": "0x1a6,0x1a7",
2626 "MSRValue": "0x220",
2627 "Offcore": "1",
2628 "SampleAfterValue": "100000",
2629 "UMask": "0x1"
2630 },
2631 {
2632 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2633 "Counter": "0,1,2,3",
2634 "EventCode": "0xB7, 0xBB",
2635 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2636 "MSRIndex": "0x1a6,0x1a7",
2637 "MSRValue": "0x420",
2638 "Offcore": "1",
2639 "SampleAfterValue": "100000",
2640 "UMask": "0x1"
2641 },
2642 {
2643 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
2644 "Counter": "0,1,2,3",
2645 "EventCode": "0xB7, 0xBB",
2646 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2647 "MSRIndex": "0x1a6,0x1a7",
2648 "MSRValue": "0x720",
2649 "Offcore": "1",
2650 "SampleAfterValue": "100000",
2651 "UMask": "0x1"
2652 },
2653 {
2654 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2655 "Counter": "0,1,2,3",
2656 "EventCode": "0xB7, 0xBB",
2657 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2658 "MSRIndex": "0x1a6,0x1a7",
2659 "MSRValue": "0x1020",
2660 "Offcore": "1",
2661 "SampleAfterValue": "100000",
2662 "UMask": "0x1"
2663 },
2664 {
2665 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2666 "Counter": "0,1,2,3",
2667 "EventCode": "0xB7, 0xBB",
2668 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2669 "MSRIndex": "0x1a6,0x1a7",
2670 "MSRValue": "0x820",
2671 "Offcore": "1",
2672 "SampleAfterValue": "100000",
2673 "UMask": "0x1"
2674 },
2675 {
2676 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2677 "Counter": "0,1,2,3",
2678 "EventCode": "0xB7, 0xBB",
2679 "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2680 "MSRIndex": "0x1a6,0x1a7",
2681 "MSRValue": "0x5070",
2682 "Offcore": "1",
2683 "SampleAfterValue": "100000",
2684 "UMask": "0x1"
2685 },
2686 {
2687 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
2688 "Counter": "0,1,2,3",
2689 "EventCode": "0xB7, 0xBB",
2690 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2691 "MSRIndex": "0x1a6,0x1a7",
2692 "MSRValue": "0x7f70",
2693 "Offcore": "1",
2694 "SampleAfterValue": "100000",
2695 "UMask": "0x1"
2696 },
2697 {
2698 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
2699 "Counter": "0,1,2,3",
2700 "EventCode": "0xB7, 0xBB",
2701 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2702 "MSRIndex": "0x1a6,0x1a7",
2703 "MSRValue": "0xff70",
2704 "Offcore": "1",
2705 "SampleAfterValue": "100000",
2706 "UMask": "0x1"
2707 },
2708 {
2709 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
2710 "Counter": "0,1,2,3",
2711 "EventCode": "0xB7, 0xBB",
2712 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2713 "MSRIndex": "0x1a6,0x1a7",
2714 "MSRValue": "0x8070",
2715 "Offcore": "1",
2716 "SampleAfterValue": "100000",
2717 "UMask": "0x1"
2718 },
2719 {
2720 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2721 "Counter": "0,1,2,3",
2722 "EventCode": "0xB7, 0xBB",
2723 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2724 "MSRIndex": "0x1a6,0x1a7",
2725 "MSRValue": "0x170",
2726 "Offcore": "1",
2727 "SampleAfterValue": "100000",
2728 "UMask": "0x1"
2729 },
2730 {
2731 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2732 "Counter": "0,1,2,3",
2733 "EventCode": "0xB7, 0xBB",
2734 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2735 "MSRIndex": "0x1a6,0x1a7",
2736 "MSRValue": "0x270",
2737 "Offcore": "1",
2738 "SampleAfterValue": "100000",
2739 "UMask": "0x1"
2740 },
2741 {
2742 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2743 "Counter": "0,1,2,3",
2744 "EventCode": "0xB7, 0xBB",
2745 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2746 "MSRIndex": "0x1a6,0x1a7",
2747 "MSRValue": "0x470",
2748 "Offcore": "1",
2749 "SampleAfterValue": "100000",
2750 "UMask": "0x1"
2751 },
2752 {
2753 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
2754 "Counter": "0,1,2,3",
2755 "EventCode": "0xB7, 0xBB",
2756 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2757 "MSRIndex": "0x1a6,0x1a7",
2758 "MSRValue": "0x770",
2759 "Offcore": "1",
2760 "SampleAfterValue": "100000",
2761 "UMask": "0x1"
2762 },
2763 {
2764 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2765 "Counter": "0,1,2,3",
2766 "EventCode": "0xB7, 0xBB",
2767 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2768 "MSRIndex": "0x1a6,0x1a7",
2769 "MSRValue": "0x1070",
2770 "Offcore": "1",
2771 "SampleAfterValue": "100000",
2772 "UMask": "0x1"
2773 },
2774 {
2775 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
2776 "Counter": "0,1,2,3",
2777 "EventCode": "0xB7, 0xBB",
2778 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2779 "MSRIndex": "0x1a6,0x1a7",
2780 "MSRValue": "0x870",
2781 "Offcore": "1",
2782 "SampleAfterValue": "100000",
2783 "UMask": "0x1"
2784 },
2785 {
2786 "BriefDescription": "Super Queue LRU hints sent to LLC",
2787 "Counter": "0,1,2,3",
2788 "EventCode": "0xF4",
2789 "EventName": "SQ_MISC.LRU_HINTS",
2790 "SampleAfterValue": "2000000",
2791 "UMask": "0x4"
2792 },
2793 {
2794 "BriefDescription": "Super Queue lock splits across a cache line",
2795 "Counter": "0,1,2,3",
2796 "EventCode": "0xF4",
2797 "EventName": "SQ_MISC.SPLIT_LOCK",
2798 "SampleAfterValue": "2000000",
2799 "UMask": "0x10"
2800 },
2801 {
2802 "BriefDescription": "Loads delayed with at-Retirement block code",
2803 "Counter": "0,1,2,3",
2804 "EventCode": "0x6",
2805 "EventName": "STORE_BLOCKS.AT_RET",
2806 "SampleAfterValue": "200000",
2807 "UMask": "0x4"
2808 },
2809 {
2810 "BriefDescription": "Cacheable loads delayed with L1D block code",
2811 "Counter": "0,1,2,3",
2812 "EventCode": "0x6",
2813 "EventName": "STORE_BLOCKS.L1D_BLOCK",
2814 "SampleAfterValue": "200000",
2815 "UMask": "0x8"
2816 }
2817 ]
