0001 [
0002 {
0003 "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
0004 "CounterType": "PGMABLE",
0005 "EventCode": "0x80",
0006 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
0007 "PerPkg": "1",
0008 "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL",
0009 "UMask": "0x01",
0010 "Unit": "ARB"
0011 },
0012 {
0013 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
0014 "Counter": "1",
0015 "CounterType": "FREERUN",
0016 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
0017 "PerPkg": "1",
0018 "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN",
0019 "Unit": "h_imc"
0020 },
0021 {
0022 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
0023 "CounterType": "FREERUN",
0024 "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
0025 "PerPkg": "1",
0026 "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
0027 "Unit": "h_imc"
0028 },
0029 {
0030 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
0031 "Counter": "2",
0032 "CounterType": "FREERUN",
0033 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
0034 "PerPkg": "1",
0035 "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN",
0036 "Unit": "h_imc"
0037 },
0038 {
0039 "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
0040 "Counter": "4",
0041 "CounterType": "FREERUN",
0042 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
0043 "PerPkg": "1",
0044 "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN",
0045 "Unit": "h_imc"
0046 },
0047 {
0048 "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
0049 "Counter": "3",
0050 "CounterType": "FREERUN",
0051 "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
0052 "PerPkg": "1",
0053 "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
0054 "Unit": "h_imc"
0055 },
0056 {
0057 "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
0058 "Counter": "5",
0059 "CounterType": "FREERUN",
0060 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
0061 "PerPkg": "1",
0062 "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN",
0063 "Unit": "h_imc"
0064 }
0065 ]
