0001 [
0002 {
0003 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3",
0006 "CounterMask": "6",
0007 "EventCode": "0xa3",
0008 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
0009 "PEBScounters": "0,1,2,3",
0010 "SampleAfterValue": "1000003",
0011 "UMask": "0x6"
0012 },
0013 {
0014 "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0xc3",
0018 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0019 "PEBScounters": "0,1,2,3,4,5,6,7",
0020 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
0021 "SampleAfterValue": "100003",
0022 "UMask": "0x2"
0023 },
0024 {
0025 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "0,1,2,3,4,5,6,7",
0028 "Data_LA": "1",
0029 "EventCode": "0xcd",
0030 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0031 "MSRIndex": "0x3F6",
0032 "MSRValue": "0x80",
0033 "PEBS": "2",
0034 "PEBScounters": "0,1,2,3,4,5,6,7",
0035 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
0036 "SampleAfterValue": "1009",
0037 "TakenAlone": "1",
0038 "UMask": "0x1"
0039 },
0040 {
0041 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
0042 "CollectPEBSRecord": "2",
0043 "Counter": "0,1,2,3,4,5,6,7",
0044 "Data_LA": "1",
0045 "EventCode": "0xcd",
0046 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0047 "MSRIndex": "0x3F6",
0048 "MSRValue": "0x10",
0049 "PEBS": "2",
0050 "PEBScounters": "0,1,2,3,4,5,6,7",
0051 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
0052 "SampleAfterValue": "20011",
0053 "TakenAlone": "1",
0054 "UMask": "0x1"
0055 },
0056 {
0057 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
0058 "CollectPEBSRecord": "2",
0059 "Counter": "0,1,2,3,4,5,6,7",
0060 "Data_LA": "1",
0061 "EventCode": "0xcd",
0062 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0063 "MSRIndex": "0x3F6",
0064 "MSRValue": "0x100",
0065 "PEBS": "2",
0066 "PEBScounters": "0,1,2,3,4,5,6,7",
0067 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
0068 "SampleAfterValue": "503",
0069 "TakenAlone": "1",
0070 "UMask": "0x1"
0071 },
0072 {
0073 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
0074 "CollectPEBSRecord": "2",
0075 "Counter": "0,1,2,3,4,5,6,7",
0076 "Data_LA": "1",
0077 "EventCode": "0xcd",
0078 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0079 "MSRIndex": "0x3F6",
0080 "MSRValue": "0x20",
0081 "PEBS": "2",
0082 "PEBScounters": "0,1,2,3,4,5,6,7",
0083 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
0084 "SampleAfterValue": "100007",
0085 "TakenAlone": "1",
0086 "UMask": "0x1"
0087 },
0088 {
0089 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
0090 "CollectPEBSRecord": "2",
0091 "Counter": "0,1,2,3,4,5,6,7",
0092 "Data_LA": "1",
0093 "EventCode": "0xcd",
0094 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0095 "MSRIndex": "0x3F6",
0096 "MSRValue": "0x4",
0097 "PEBS": "2",
0098 "PEBScounters": "0,1,2,3,4,5,6,7",
0099 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
0100 "SampleAfterValue": "100003",
0101 "TakenAlone": "1",
0102 "UMask": "0x1"
0103 },
0104 {
0105 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
0106 "CollectPEBSRecord": "2",
0107 "Counter": "0,1,2,3,4,5,6,7",
0108 "Data_LA": "1",
0109 "EventCode": "0xcd",
0110 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0111 "MSRIndex": "0x3F6",
0112 "MSRValue": "0x200",
0113 "PEBS": "2",
0114 "PEBScounters": "0,1,2,3,4,5,6,7",
0115 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
0116 "SampleAfterValue": "101",
0117 "TakenAlone": "1",
0118 "UMask": "0x1"
0119 },
0120 {
0121 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
0122 "CollectPEBSRecord": "2",
0123 "Counter": "0,1,2,3,4,5,6,7",
0124 "Data_LA": "1",
0125 "EventCode": "0xcd",
0126 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0127 "MSRIndex": "0x3F6",
0128 "MSRValue": "0x40",
0129 "PEBS": "2",
0130 "PEBScounters": "0,1,2,3,4,5,6,7",
0131 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
0132 "SampleAfterValue": "2003",
0133 "TakenAlone": "1",
0134 "UMask": "0x1"
0135 },
0136 {
0137 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
0138 "CollectPEBSRecord": "2",
0139 "Counter": "0,1,2,3,4,5,6,7",
0140 "Data_LA": "1",
0141 "EventCode": "0xcd",
0142 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0143 "MSRIndex": "0x3F6",
0144 "MSRValue": "0x8",
0145 "PEBS": "2",
0146 "PEBScounters": "0,1,2,3,4,5,6,7",
0147 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
0148 "SampleAfterValue": "50021",
0149 "TakenAlone": "1",
0150 "UMask": "0x1"
0151 },
0152 {
0153 "BriefDescription": "Demand Data Read requests who miss L3 cache",
0154 "CollectPEBSRecord": "2",
0155 "Counter": "0,1,2,3",
0156 "EventCode": "0xb0",
0157 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
0158 "PEBScounters": "0,1,2,3",
0159 "PublicDescription": "Demand Data Read requests who miss L3 cache.",
0160 "SampleAfterValue": "100003",
0161 "UMask": "0x10"
0162 },
0163 {
0164 "BriefDescription": "Number of times an RTM execution aborted.",
0165 "CollectPEBSRecord": "2",
0166 "Counter": "0,1,2,3,4,5,6,7",
0167 "EventCode": "0xc9",
0168 "EventName": "RTM_RETIRED.ABORTED",
0169 "PEBScounters": "0,1,2,3,4,5,6,7",
0170 "PublicDescription": "Counts the number of times RTM abort was triggered.",
0171 "SampleAfterValue": "100003",
0172 "UMask": "0x4"
0173 },
0174 {
0175 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
0176 "CollectPEBSRecord": "2",
0177 "Counter": "0,1,2,3,4,5,6,7",
0178 "EventCode": "0xc9",
0179 "EventName": "RTM_RETIRED.ABORTED_EVENTS",
0180 "PEBScounters": "0,1,2,3,4,5,6,7",
0181 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
0182 "SampleAfterValue": "100003",
0183 "UMask": "0x80"
0184 },
0185 {
0186 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
0187 "CollectPEBSRecord": "2",
0188 "Counter": "0,1,2,3,4,5,6,7",
0189 "EventCode": "0xc9",
0190 "EventName": "RTM_RETIRED.ABORTED_MEM",
0191 "PEBScounters": "0,1,2,3,4,5,6,7",
0192 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
0193 "SampleAfterValue": "100003",
0194 "UMask": "0x8"
0195 },
0196 {
0197 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
0198 "CollectPEBSRecord": "2",
0199 "Counter": "0,1,2,3,4,5,6,7",
0200 "EventCode": "0xc9",
0201 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
0202 "PEBScounters": "0,1,2,3,4,5,6,7",
0203 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
0204 "SampleAfterValue": "100003",
0205 "UMask": "0x40"
0206 },
0207 {
0208 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
0209 "CollectPEBSRecord": "2",
0210 "Counter": "0,1,2,3,4,5,6,7",
0211 "EventCode": "0xc9",
0212 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
0213 "PEBScounters": "0,1,2,3,4,5,6,7",
0214 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
0215 "SampleAfterValue": "100003",
0216 "UMask": "0x20"
0217 },
0218 {
0219 "BriefDescription": "Number of times an RTM execution successfully committed",
0220 "CollectPEBSRecord": "2",
0221 "Counter": "0,1,2,3,4,5,6,7",
0222 "EventCode": "0xc9",
0223 "EventName": "RTM_RETIRED.COMMIT",
0224 "PEBScounters": "0,1,2,3,4,5,6,7",
0225 "PublicDescription": "Counts the number of times RTM commit succeeded.",
0226 "SampleAfterValue": "100003",
0227 "UMask": "0x2"
0228 },
0229 {
0230 "BriefDescription": "Number of times an RTM execution started.",
0231 "CollectPEBSRecord": "2",
0232 "Counter": "0,1,2,3,4,5,6,7",
0233 "EventCode": "0xc9",
0234 "EventName": "RTM_RETIRED.START",
0235 "PEBScounters": "0,1,2,3,4,5,6,7",
0236 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
0237 "SampleAfterValue": "100003",
0238 "UMask": "0x1"
0239 },
0240 {
0241 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
0242 "CollectPEBSRecord": "2",
0243 "Counter": "0,1,2,3,4,5,6,7",
0244 "EventCode": "0x5d",
0245 "EventName": "TX_EXEC.MISC2",
0246 "PEBScounters": "0,1,2,3,4,5,6,7",
0247 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
0248 "SampleAfterValue": "100003",
0249 "UMask": "0x2"
0250 },
0251 {
0252 "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
0253 "CollectPEBSRecord": "2",
0254 "Counter": "0,1,2,3,4,5,6,7",
0255 "EventCode": "0x5d",
0256 "EventName": "TX_EXEC.MISC3",
0257 "PEBScounters": "0,1,2,3,4,5,6,7",
0258 "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
0259 "SampleAfterValue": "100003",
0260 "UMask": "0x4"
0261 },
0262 {
0263 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
0264 "CollectPEBSRecord": "2",
0265 "Counter": "0,1,2,3",
0266 "EventCode": "0x54",
0267 "EventName": "TX_MEM.ABORT_CAPACITY_READ",
0268 "PEBScounters": "0,1,2,3",
0269 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
0270 "SampleAfterValue": "100003",
0271 "UMask": "0x80"
0272 },
0273 {
0274 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
0275 "CollectPEBSRecord": "2",
0276 "Counter": "0,1,2,3",
0277 "EventCode": "0x54",
0278 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
0279 "PEBScounters": "0,1,2,3",
0280 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
0281 "SampleAfterValue": "100003",
0282 "UMask": "0x2"
0283 },
0284 {
0285 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
0286 "CollectPEBSRecord": "2",
0287 "Counter": "0,1,2,3",
0288 "EventCode": "0x54",
0289 "EventName": "TX_MEM.ABORT_CONFLICT",
0290 "PEBScounters": "0,1,2,3",
0291 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
0292 "SampleAfterValue": "100003",
0293 "UMask": "0x1"
0294 }
0295 ]
