0001 [
0002 {
0003 "BriefDescription": "Counts all microcode FP assists.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xc1",
0007 "EventName": "ASSISTS.FP",
0008 "PEBScounters": "0,1,2,3,4,5,6,7",
0009 "PublicDescription": "Counts all microcode Floating Point assists.",
0010 "SampleAfterValue": "100003",
0011 "UMask": "0x2"
0012 },
0013 {
0014 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0xc7",
0018 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
0019 "PEBScounters": "0,1,2,3,4,5,6,7",
0020 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0021 "SampleAfterValue": "100003",
0022 "UMask": "0x4"
0023 },
0024 {
0025 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "0,1,2,3,4,5,6,7",
0028 "EventCode": "0xc7",
0029 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
0030 "PEBScounters": "0,1,2,3,4,5,6,7",
0031 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0032 "SampleAfterValue": "100003",
0033 "UMask": "0x8"
0034 },
0035 {
0036 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0037 "CollectPEBSRecord": "2",
0038 "Counter": "0,1,2,3,4,5,6,7",
0039 "EventCode": "0xc7",
0040 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
0041 "PEBScounters": "0,1,2,3,4,5,6,7",
0042 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0043 "SampleAfterValue": "100003",
0044 "UMask": "0x10"
0045 },
0046 {
0047 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0048 "CollectPEBSRecord": "2",
0049 "Counter": "0,1,2,3,4,5,6,7",
0050 "EventCode": "0xc7",
0051 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
0052 "PEBScounters": "0,1,2,3,4,5,6,7",
0053 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0054 "SampleAfterValue": "100003",
0055 "UMask": "0x20"
0056 },
0057 {
0058 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0059 "CollectPEBSRecord": "2",
0060 "Counter": "0,1,2,3,4,5,6,7",
0061 "EventCode": "0xc7",
0062 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
0063 "PEBScounters": "0,1,2,3,4,5,6,7",
0064 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0065 "SampleAfterValue": "100003",
0066 "UMask": "0x40"
0067 },
0068 {
0069 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0070 "CollectPEBSRecord": "2",
0071 "Counter": "0,1,2,3,4,5,6,7",
0072 "EventCode": "0xc7",
0073 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
0074 "PEBScounters": "0,1,2,3,4,5,6,7",
0075 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0076 "SampleAfterValue": "100003",
0077 "UMask": "0x80"
0078 },
0079 {
0080 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0081 "CollectPEBSRecord": "2",
0082 "Counter": "0,1,2,3,4,5,6,7",
0083 "EventCode": "0xc7",
0084 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
0085 "PEBScounters": "0,1,2,3,4,5,6,7",
0086 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0087 "SampleAfterValue": "100003",
0088 "UMask": "0x1"
0089 },
0090 {
0091 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0092 "CollectPEBSRecord": "2",
0093 "Counter": "0,1,2,3,4,5,6,7",
0094 "EventCode": "0xc7",
0095 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
0096 "PEBScounters": "0,1,2,3,4,5,6,7",
0097 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0098 "SampleAfterValue": "100003",
0099 "UMask": "0x2"
0100 }
0101 ]
