0001 [
0002 {
0003 "BriefDescription": "pclk Cycles",
0004 "Counter": "0,1,2,3",
0005 "EventName": "UNC_P_CLOCKTICKS",
0006 "PerPkg": "1",
0007 "Unit": "PCU"
0008 },
0009 {
0010 "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
0011 "Counter": "0,1,2,3",
0012 "EventCode": "0x60",
0013 "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
0014 "PerPkg": "1",
0015 "Unit": "PCU"
0016 },
0017 {
0018 "BriefDescription": "UNC_P_DEMOTIONS",
0019 "Counter": "0,1,2,3",
0020 "EventCode": "0x30",
0021 "EventName": "UNC_P_DEMOTIONS",
0022 "PerPkg": "1",
0023 "Unit": "PCU"
0024 },
0025 {
0026 "BriefDescription": "Phase Shed 0 Cycles",
0027 "Counter": "0,1,2,3",
0028 "EventCode": "0x75",
0029 "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
0030 "PerPkg": "1",
0031 "Unit": "PCU"
0032 },
0033 {
0034 "BriefDescription": "Phase Shed 1 Cycles",
0035 "Counter": "0,1,2,3",
0036 "EventCode": "0x76",
0037 "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
0038 "PerPkg": "1",
0039 "Unit": "PCU"
0040 },
0041 {
0042 "BriefDescription": "Phase Shed 2 Cycles",
0043 "Counter": "0,1,2,3",
0044 "EventCode": "0x77",
0045 "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
0046 "PerPkg": "1",
0047 "Unit": "PCU"
0048 },
0049 {
0050 "BriefDescription": "Phase Shed 3 Cycles",
0051 "Counter": "0,1,2,3",
0052 "EventCode": "0x78",
0053 "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
0054 "PerPkg": "1",
0055 "Unit": "PCU"
0056 },
0057 {
0058 "BriefDescription": "Thermal Strongest Upper Limit Cycles",
0059 "Counter": "0,1,2,3",
0060 "EventCode": "0x4",
0061 "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
0062 "PerPkg": "1",
0063 "Unit": "PCU"
0064 },
0065 {
0066 "BriefDescription": "Power Strongest Upper Limit Cycles",
0067 "Counter": "0,1,2,3",
0068 "EventCode": "0x5",
0069 "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
0070 "PerPkg": "1",
0071 "Unit": "PCU"
0072 },
0073 {
0074 "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
0075 "Counter": "0,1,2,3",
0076 "EventCode": "0x73",
0077 "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
0078 "PerPkg": "1",
0079 "Unit": "PCU"
0080 },
0081 {
0082 "BriefDescription": "Cycles spent changing Frequency",
0083 "Counter": "0,1,2,3",
0084 "EventCode": "0x74",
0085 "EventName": "UNC_P_FREQ_TRANS_CYCLES",
0086 "PerPkg": "1",
0087 "Unit": "PCU"
0088 },
0089 {
0090 "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
0091 "Counter": "0,1,2,3",
0092 "EventCode": "0x6",
0093 "EventName": "UNC_P_MCP_PROCHOT_CYCLES",
0094 "PerPkg": "1",
0095 "Unit": "PCU"
0096 },
0097 {
0098 "BriefDescription": "Memory Phase Shedding Cycles",
0099 "Counter": "0,1,2,3",
0100 "EventCode": "0x2F",
0101 "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
0102 "PerPkg": "1",
0103 "Unit": "PCU"
0104 },
0105 {
0106 "BriefDescription": "Package C State Residency - C0",
0107 "Counter": "0,1,2,3",
0108 "EventCode": "0x2A",
0109 "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
0110 "PerPkg": "1",
0111 "Unit": "PCU"
0112 },
0113 {
0114 "BriefDescription": "Package C State Residency - C2E",
0115 "Counter": "0,1,2,3",
0116 "EventCode": "0x2B",
0117 "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
0118 "PerPkg": "1",
0119 "Unit": "PCU"
0120 },
0121 {
0122 "BriefDescription": "Package C State Residency - C3",
0123 "Counter": "0,1,2,3",
0124 "EventCode": "0x2C",
0125 "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
0126 "PerPkg": "1",
0127 "Unit": "PCU"
0128 },
0129 {
0130 "BriefDescription": "Package C State Residency - C6",
0131 "Counter": "0,1,2,3",
0132 "EventCode": "0x2D",
0133 "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
0134 "PerPkg": "1",
0135 "Unit": "PCU"
0136 },
0137 {
0138 "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
0139 "Counter": "0,1,2,3",
0140 "EventCode": "0x7",
0141 "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
0142 "PerPkg": "1",
0143 "Unit": "PCU"
0144 },
0145 {
0146 "BriefDescription": "Number of cores in C-State; C0 and C1",
0147 "Counter": "0,1,2,3",
0148 "EventCode": "0x80",
0149 "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
0150 "PerPkg": "1",
0151 "Unit": "PCU"
0152 },
0153 {
0154 "BriefDescription": "Number of cores in C-State; C3",
0155 "Counter": "0,1,2,3",
0156 "EventCode": "0x80",
0157 "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
0158 "PerPkg": "1",
0159 "Unit": "PCU"
0160 },
0161 {
0162 "BriefDescription": "Number of cores in C-State; C6 and C7",
0163 "Counter": "0,1,2,3",
0164 "EventCode": "0x80",
0165 "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
0166 "PerPkg": "1",
0167 "Unit": "PCU"
0168 },
0169 {
0170 "BriefDescription": "External Prochot",
0171 "Counter": "0,1,2,3",
0172 "EventCode": "0xA",
0173 "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
0174 "PerPkg": "1",
0175 "Unit": "PCU"
0176 },
0177 {
0178 "BriefDescription": "Internal Prochot",
0179 "Counter": "0,1,2,3",
0180 "EventCode": "0x9",
0181 "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
0182 "PerPkg": "1",
0183 "Unit": "PCU"
0184 },
0185 {
0186 "BriefDescription": "Total Core C State Transition Cycles",
0187 "Counter": "0,1,2,3",
0188 "EventCode": "0x72",
0189 "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
0190 "PerPkg": "1",
0191 "Unit": "PCU"
0192 },
0193 {
0194 "BriefDescription": "VR Hot",
0195 "Counter": "0,1,2,3",
0196 "EventCode": "0x42",
0197 "EventName": "UNC_P_VR_HOT_CYCLES",
0198 "PerPkg": "1",
0199 "Unit": "PCU"
0200 }
0201 ]
