0001 [
0002 {
0003 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x28",
0007 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
0008 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
0009 "SampleAfterValue": "200003",
0010 "UMask": "0x7"
0011 },
0012 {
0013 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "EventCode": "0x28",
0017 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
0018 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
0019 "SampleAfterValue": "200003",
0020 "UMask": "0x18"
0021 },
0022 {
0023 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
0024 "Counter": "0,1,2,3",
0025 "CounterHTOff": "0,1,2,3,4,5,6,7",
0026 "EventCode": "0x28",
0027 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
0028 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
0029 "SampleAfterValue": "200003",
0030 "UMask": "0x20"
0031 },
0032 {
0033 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
0034 "Counter": "0,1,2,3",
0035 "CounterHTOff": "0,1,2,3,4,5,6,7",
0036 "EventCode": "0x28",
0037 "EventName": "CORE_POWER.THROTTLE",
0038 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
0039 "SampleAfterValue": "200003",
0040 "UMask": "0x40"
0041 },
0042 {
0043 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
0044 "Counter": "0,1,2,3",
0045 "CounterHTOff": "0,1,2,3,4,5,6,7",
0046 "EventCode": "0xEF",
0047 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
0048 "SampleAfterValue": "2000003",
0049 "UMask": "0x20"
0050 },
0051 {
0052 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
0053 "Counter": "0,1,2,3",
0054 "CounterHTOff": "0,1,2,3,4,5,6,7",
0055 "EventCode": "0xEF",
0056 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
0057 "SampleAfterValue": "2000003",
0058 "UMask": "0x10"
0059 },
0060 {
0061 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
0062 "Counter": "0,1,2,3",
0063 "CounterHTOff": "0,1,2,3,4,5,6,7",
0064 "EventCode": "0xEF",
0065 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
0066 "SampleAfterValue": "2000003",
0067 "UMask": "0x2"
0068 },
0069 {
0070 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
0071 "Counter": "0,1,2,3",
0072 "CounterHTOff": "0,1,2,3,4,5,6,7",
0073 "EventCode": "0xEF",
0074 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
0075 "SampleAfterValue": "2000003",
0076 "UMask": "0x1"
0077 },
0078 {
0079 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
0080 "Counter": "0,1,2,3",
0081 "CounterHTOff": "0,1,2,3,4,5,6,7",
0082 "EventCode": "0xEF",
0083 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
0084 "SampleAfterValue": "2000003",
0085 "UMask": "0x40"
0086 },
0087 {
0088 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
0089 "Counter": "0,1,2,3",
0090 "CounterHTOff": "0,1,2,3,4,5,6,7",
0091 "EventCode": "0xEF",
0092 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
0093 "SampleAfterValue": "2000003",
0094 "UMask": "0x8"
0095 },
0096 {
0097 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
0098 "Counter": "0,1,2,3",
0099 "CounterHTOff": "0,1,2,3,4,5,6,7",
0100 "EventCode": "0xEF",
0101 "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
0102 "SampleAfterValue": "2000003",
0103 "UMask": "0x4"
0104 },
0105 {
0106 "BriefDescription": "Number of hardware interrupts received by the processor.",
0107 "Counter": "0,1,2,3",
0108 "CounterHTOff": "0,1,2,3,4,5,6,7",
0109 "EventCode": "0xCB",
0110 "EventName": "HW_INTERRUPTS.RECEIVED",
0111 "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
0112 "SampleAfterValue": "203",
0113 "UMask": "0x1"
0114 },
0115 {
0116 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
0117 "Counter": "0,1,2,3",
0118 "CounterHTOff": "0,1,2,3,4,5,6,7",
0119 "EventCode": "0xFE",
0120 "EventName": "IDI_MISC.WB_DOWNGRADE",
0121 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
0122 "SampleAfterValue": "100003",
0123 "UMask": "0x4"
0124 },
0125 {
0126 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
0127 "Counter": "0,1,2,3",
0128 "CounterHTOff": "0,1,2,3,4,5,6,7",
0129 "EventCode": "0xFE",
0130 "EventName": "IDI_MISC.WB_UPGRADE",
0131 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
0132 "SampleAfterValue": "100003",
0133 "UMask": "0x2"
0134 },
0135 {
0136 "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
0137 "Counter": "0,1,2,3",
0138 "CounterHTOff": "0,1,2,3,4,5,6,7",
0139 "EventCode": "0x09",
0140 "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
0141 "SampleAfterValue": "2000003",
0142 "UMask": "0x1"
0143 }
0144 ]
