0001 [
0002 {
0003 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "CounterMask": "2",
0007 "EventCode": "0xA3",
0008 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
0009 "SampleAfterValue": "2000003",
0010 "UMask": "0x2"
0011 },
0012 {
0013 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "CounterMask": "6",
0017 "EventCode": "0xA3",
0018 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
0019 "SampleAfterValue": "2000003",
0020 "UMask": "0x6"
0021 },
0022 {
0023 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
0024 "Counter": "0,1,2,3",
0025 "CounterHTOff": "0,1,2,3,4,5,6,7",
0026 "EventCode": "0xC8",
0027 "EventName": "HLE_RETIRED.ABORTED",
0028 "PEBS": "1",
0029 "PublicDescription": "Number of times HLE abort was triggered.",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x4"
0032 },
0033 {
0034 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
0035 "Counter": "0,1,2,3",
0036 "CounterHTOff": "0,1,2,3,4,5,6,7",
0037 "EventCode": "0xC8",
0038 "EventName": "HLE_RETIRED.ABORTED_EVENTS",
0039 "SampleAfterValue": "2000003",
0040 "UMask": "0x80"
0041 },
0042 {
0043 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
0044 "Counter": "0,1,2,3",
0045 "CounterHTOff": "0,1,2,3,4,5,6,7",
0046 "EventCode": "0xC8",
0047 "EventName": "HLE_RETIRED.ABORTED_MEM",
0048 "SampleAfterValue": "2000003",
0049 "UMask": "0x8"
0050 },
0051 {
0052 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
0053 "Counter": "0,1,2,3",
0054 "CounterHTOff": "0,1,2,3,4,5,6,7",
0055 "EventCode": "0xC8",
0056 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
0057 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
0058 "SampleAfterValue": "2000003",
0059 "UMask": "0x40"
0060 },
0061 {
0062 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
0063 "Counter": "0,1,2,3",
0064 "CounterHTOff": "0,1,2,3,4,5,6,7",
0065 "EventCode": "0xC8",
0066 "EventName": "HLE_RETIRED.ABORTED_TIMER",
0067 "SampleAfterValue": "2000003",
0068 "UMask": "0x10"
0069 },
0070 {
0071 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
0072 "Counter": "0,1,2,3",
0073 "CounterHTOff": "0,1,2,3,4,5,6,7",
0074 "EventCode": "0xC8",
0075 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
0076 "SampleAfterValue": "2000003",
0077 "UMask": "0x20"
0078 },
0079 {
0080 "BriefDescription": "Number of times an HLE execution successfully committed",
0081 "Counter": "0,1,2,3",
0082 "CounterHTOff": "0,1,2,3,4,5,6,7",
0083 "EventCode": "0xC8",
0084 "EventName": "HLE_RETIRED.COMMIT",
0085 "PublicDescription": "Number of times HLE commit succeeded.",
0086 "SampleAfterValue": "2000003",
0087 "UMask": "0x2"
0088 },
0089 {
0090 "BriefDescription": "Number of times an HLE execution started.",
0091 "Counter": "0,1,2,3",
0092 "CounterHTOff": "0,1,2,3,4,5,6,7",
0093 "EventCode": "0xC8",
0094 "EventName": "HLE_RETIRED.START",
0095 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
0096 "SampleAfterValue": "2000003",
0097 "UMask": "0x1"
0098 },
0099 {
0100 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
0101 "Counter": "0,1,2,3",
0102 "CounterHTOff": "0,1,2,3,4,5,6,7",
0103 "Errata": "SKL089",
0104 "EventCode": "0xC3",
0105 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0106 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
0107 "SampleAfterValue": "100003",
0108 "UMask": "0x2"
0109 },
0110 {
0111 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
0112 "Counter": "0,1,2,3",
0113 "CounterHTOff": "0,1,2,3",
0114 "Data_LA": "1",
0115 "EventCode": "0xcd",
0116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0117 "MSRIndex": "0x3F6",
0118 "MSRValue": "0x80",
0119 "PEBS": "2",
0120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
0121 "SampleAfterValue": "1009",
0122 "TakenAlone": "1",
0123 "UMask": "0x1"
0124 },
0125 {
0126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
0127 "Counter": "0,1,2,3",
0128 "CounterHTOff": "0,1,2,3",
0129 "Data_LA": "1",
0130 "EventCode": "0xcd",
0131 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0132 "MSRIndex": "0x3F6",
0133 "MSRValue": "0x10",
0134 "PEBS": "2",
0135 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
0136 "SampleAfterValue": "20011",
0137 "TakenAlone": "1",
0138 "UMask": "0x1"
0139 },
0140 {
0141 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
0142 "Counter": "0,1,2,3",
0143 "CounterHTOff": "0,1,2,3",
0144 "Data_LA": "1",
0145 "EventCode": "0xcd",
0146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0147 "MSRIndex": "0x3F6",
0148 "MSRValue": "0x100",
0149 "PEBS": "2",
0150 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
0151 "SampleAfterValue": "503",
0152 "TakenAlone": "1",
0153 "UMask": "0x1"
0154 },
0155 {
0156 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
0157 "Counter": "0,1,2,3",
0158 "CounterHTOff": "0,1,2,3",
0159 "Data_LA": "1",
0160 "EventCode": "0xcd",
0161 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0162 "MSRIndex": "0x3F6",
0163 "MSRValue": "0x20",
0164 "PEBS": "2",
0165 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
0166 "SampleAfterValue": "100007",
0167 "TakenAlone": "1",
0168 "UMask": "0x1"
0169 },
0170 {
0171 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
0172 "Counter": "0,1,2,3",
0173 "CounterHTOff": "0,1,2,3",
0174 "Data_LA": "1",
0175 "EventCode": "0xcd",
0176 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0177 "MSRIndex": "0x3F6",
0178 "MSRValue": "0x4",
0179 "PEBS": "2",
0180 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
0181 "SampleAfterValue": "100003",
0182 "TakenAlone": "1",
0183 "UMask": "0x1"
0184 },
0185 {
0186 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
0187 "Counter": "0,1,2,3",
0188 "CounterHTOff": "0,1,2,3",
0189 "Data_LA": "1",
0190 "EventCode": "0xcd",
0191 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0192 "MSRIndex": "0x3F6",
0193 "MSRValue": "0x200",
0194 "PEBS": "2",
0195 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
0196 "SampleAfterValue": "101",
0197 "TakenAlone": "1",
0198 "UMask": "0x1"
0199 },
0200 {
0201 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
0202 "Counter": "0,1,2,3",
0203 "CounterHTOff": "0,1,2,3",
0204 "Data_LA": "1",
0205 "EventCode": "0xcd",
0206 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0207 "MSRIndex": "0x3F6",
0208 "MSRValue": "0x40",
0209 "PEBS": "2",
0210 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
0211 "SampleAfterValue": "2003",
0212 "TakenAlone": "1",
0213 "UMask": "0x1"
0214 },
0215 {
0216 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
0217 "Counter": "0,1,2,3",
0218 "CounterHTOff": "0,1,2,3",
0219 "Data_LA": "1",
0220 "EventCode": "0xcd",
0221 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0222 "MSRIndex": "0x3F6",
0223 "MSRValue": "0x8",
0224 "PEBS": "2",
0225 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
0226 "SampleAfterValue": "50021",
0227 "TakenAlone": "1",
0228 "UMask": "0x1"
0229 },
0230 {
0231 "BriefDescription": "Demand Data Read requests who miss L3 cache",
0232 "Counter": "0,1,2,3",
0233 "CounterHTOff": "0,1,2,3,4,5,6,7",
0234 "EventCode": "0xB0",
0235 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
0236 "PublicDescription": "Demand Data Read requests who miss L3 cache.",
0237 "SampleAfterValue": "100003",
0238 "UMask": "0x10"
0239 },
0240 {
0241 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
0242 "Counter": "0,1,2,3",
0243 "CounterHTOff": "0,1,2,3,4,5,6,7",
0244 "CounterMask": "1",
0245 "EventCode": "0x60",
0246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
0247 "SampleAfterValue": "2000003",
0248 "UMask": "0x10"
0249 },
0250 {
0251 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
0252 "Counter": "0,1,2,3",
0253 "CounterHTOff": "0,1,2,3,4,5,6,7",
0254 "EventCode": "0x60",
0255 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
0256 "SampleAfterValue": "2000003",
0257 "UMask": "0x10"
0258 },
0259 {
0260 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
0261 "Counter": "0,1,2,3",
0262 "CounterHTOff": "0,1,2,3,4,5,6,7",
0263 "CounterMask": "6",
0264 "EventCode": "0x60",
0265 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
0266 "SampleAfterValue": "2000003",
0267 "UMask": "0x10"
0268 },
0269 {
0270 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
0271 "Counter": "0,1,2,3",
0272 "CounterHTOff": "0,1,2,3",
0273 "EventCode": "0xB7, 0xBB",
0274 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
0275 "MSRIndex": "0x1a6,0x1a7",
0276 "MSRValue": "0x3FBC000491",
0277 "Offcore": "1",
0278 "SampleAfterValue": "100003",
0279 "UMask": "0x1"
0280 },
0281 {
0282 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
0283 "Counter": "0,1,2,3",
0284 "CounterHTOff": "0,1,2,3",
0285 "EventCode": "0xB7, 0xBB",
0286 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
0287 "MSRIndex": "0x1a6,0x1a7",
0288 "MSRValue": "0x103FC00491",
0289 "Offcore": "1",
0290 "SampleAfterValue": "100003",
0291 "UMask": "0x1"
0292 },
0293 {
0294 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
0295 "Counter": "0,1,2,3",
0296 "CounterHTOff": "0,1,2,3",
0297 "EventCode": "0xB7, 0xBB",
0298 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
0299 "MSRIndex": "0x1a6,0x1a7",
0300 "MSRValue": "0x83FC00491",
0301 "Offcore": "1",
0302 "SampleAfterValue": "100003",
0303 "UMask": "0x1"
0304 },
0305 {
0306 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
0307 "Counter": "0,1,2,3",
0308 "CounterHTOff": "0,1,2,3",
0309 "EventCode": "0xB7, 0xBB",
0310 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0311 "MSRIndex": "0x1a6,0x1a7",
0312 "MSRValue": "0x63FC00491",
0313 "Offcore": "1",
0314 "SampleAfterValue": "100003",
0315 "UMask": "0x1"
0316 },
0317 {
0318 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
0319 "Counter": "0,1,2,3",
0320 "CounterHTOff": "0,1,2,3",
0321 "EventCode": "0xB7, 0xBB",
0322 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0323 "MSRIndex": "0x1a6,0x1a7",
0324 "MSRValue": "0x604000491",
0325 "Offcore": "1",
0326 "SampleAfterValue": "100003",
0327 "UMask": "0x1"
0328 },
0329 {
0330 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
0331 "Counter": "0,1,2,3",
0332 "CounterHTOff": "0,1,2,3",
0333 "EventCode": "0xB7, 0xBB",
0334 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0335 "MSRIndex": "0x1a6,0x1a7",
0336 "MSRValue": "0x63B800491",
0337 "Offcore": "1",
0338 "SampleAfterValue": "100003",
0339 "UMask": "0x1"
0340 },
0341 {
0342 "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
0343 "Counter": "0,1,2,3",
0344 "CounterHTOff": "0,1,2,3",
0345 "EventCode": "0xB7, 0xBB",
0346 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
0347 "MSRIndex": "0x1a6,0x1a7",
0348 "MSRValue": "0x3FBC000490",
0349 "Offcore": "1",
0350 "SampleAfterValue": "100003",
0351 "UMask": "0x1"
0352 },
0353 {
0354 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
0355 "Counter": "0,1,2,3",
0356 "CounterHTOff": "0,1,2,3",
0357 "EventCode": "0xB7, 0xBB",
0358 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
0359 "MSRIndex": "0x1a6,0x1a7",
0360 "MSRValue": "0x103FC00490",
0361 "Offcore": "1",
0362 "SampleAfterValue": "100003",
0363 "UMask": "0x1"
0364 },
0365 {
0366 "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
0367 "Counter": "0,1,2,3",
0368 "CounterHTOff": "0,1,2,3",
0369 "EventCode": "0xB7, 0xBB",
0370 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
0371 "MSRIndex": "0x1a6,0x1a7",
0372 "MSRValue": "0x83FC00490",
0373 "Offcore": "1",
0374 "SampleAfterValue": "100003",
0375 "UMask": "0x1"
0376 },
0377 {
0378 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
0379 "Counter": "0,1,2,3",
0380 "CounterHTOff": "0,1,2,3",
0381 "EventCode": "0xB7, 0xBB",
0382 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0383 "MSRIndex": "0x1a6,0x1a7",
0384 "MSRValue": "0x63FC00490",
0385 "Offcore": "1",
0386 "SampleAfterValue": "100003",
0387 "UMask": "0x1"
0388 },
0389 {
0390 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
0391 "Counter": "0,1,2,3",
0392 "CounterHTOff": "0,1,2,3",
0393 "EventCode": "0xB7, 0xBB",
0394 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0395 "MSRIndex": "0x1a6,0x1a7",
0396 "MSRValue": "0x604000490",
0397 "Offcore": "1",
0398 "SampleAfterValue": "100003",
0399 "UMask": "0x1"
0400 },
0401 {
0402 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
0403 "Counter": "0,1,2,3",
0404 "CounterHTOff": "0,1,2,3",
0405 "EventCode": "0xB7, 0xBB",
0406 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0407 "MSRIndex": "0x1a6,0x1a7",
0408 "MSRValue": "0x63B800490",
0409 "Offcore": "1",
0410 "SampleAfterValue": "100003",
0411 "UMask": "0x1"
0412 },
0413 {
0414 "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
0415 "Counter": "0,1,2,3",
0416 "CounterHTOff": "0,1,2,3",
0417 "EventCode": "0xB7, 0xBB",
0418 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
0419 "MSRIndex": "0x1a6,0x1a7",
0420 "MSRValue": "0x3FBC000120",
0421 "Offcore": "1",
0422 "SampleAfterValue": "100003",
0423 "UMask": "0x1"
0424 },
0425 {
0426 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
0427 "Counter": "0,1,2,3",
0428 "CounterHTOff": "0,1,2,3",
0429 "EventCode": "0xB7, 0xBB",
0430 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
0431 "MSRIndex": "0x1a6,0x1a7",
0432 "MSRValue": "0x103FC00120",
0433 "Offcore": "1",
0434 "SampleAfterValue": "100003",
0435 "UMask": "0x1"
0436 },
0437 {
0438 "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
0439 "Counter": "0,1,2,3",
0440 "CounterHTOff": "0,1,2,3",
0441 "EventCode": "0xB7, 0xBB",
0442 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
0443 "MSRIndex": "0x1a6,0x1a7",
0444 "MSRValue": "0x83FC00120",
0445 "Offcore": "1",
0446 "SampleAfterValue": "100003",
0447 "UMask": "0x1"
0448 },
0449 {
0450 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
0451 "Counter": "0,1,2,3",
0452 "CounterHTOff": "0,1,2,3",
0453 "EventCode": "0xB7, 0xBB",
0454 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0455 "MSRIndex": "0x1a6,0x1a7",
0456 "MSRValue": "0x63FC00120",
0457 "Offcore": "1",
0458 "SampleAfterValue": "100003",
0459 "UMask": "0x1"
0460 },
0461 {
0462 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
0463 "Counter": "0,1,2,3",
0464 "CounterHTOff": "0,1,2,3",
0465 "EventCode": "0xB7, 0xBB",
0466 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0467 "MSRIndex": "0x1a6,0x1a7",
0468 "MSRValue": "0x604000120",
0469 "Offcore": "1",
0470 "SampleAfterValue": "100003",
0471 "UMask": "0x1"
0472 },
0473 {
0474 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
0475 "Counter": "0,1,2,3",
0476 "CounterHTOff": "0,1,2,3",
0477 "EventCode": "0xB7, 0xBB",
0478 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0479 "MSRIndex": "0x1a6,0x1a7",
0480 "MSRValue": "0x63B800120",
0481 "Offcore": "1",
0482 "SampleAfterValue": "100003",
0483 "UMask": "0x1"
0484 },
0485 {
0486 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
0487 "Counter": "0,1,2,3",
0488 "CounterHTOff": "0,1,2,3",
0489 "EventCode": "0xB7, 0xBB",
0490 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
0491 "MSRIndex": "0x1a6,0x1a7",
0492 "MSRValue": "0x3FBC000122",
0493 "Offcore": "1",
0494 "SampleAfterValue": "100003",
0495 "UMask": "0x1"
0496 },
0497 {
0498 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
0499 "Counter": "0,1,2,3",
0500 "CounterHTOff": "0,1,2,3",
0501 "EventCode": "0xB7, 0xBB",
0502 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
0503 "MSRIndex": "0x1a6,0x1a7",
0504 "MSRValue": "0x103FC00122",
0505 "Offcore": "1",
0506 "SampleAfterValue": "100003",
0507 "UMask": "0x1"
0508 },
0509 {
0510 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
0511 "Counter": "0,1,2,3",
0512 "CounterHTOff": "0,1,2,3",
0513 "EventCode": "0xB7, 0xBB",
0514 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
0515 "MSRIndex": "0x1a6,0x1a7",
0516 "MSRValue": "0x83FC00122",
0517 "Offcore": "1",
0518 "SampleAfterValue": "100003",
0519 "UMask": "0x1"
0520 },
0521 {
0522 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
0523 "Counter": "0,1,2,3",
0524 "CounterHTOff": "0,1,2,3",
0525 "EventCode": "0xB7, 0xBB",
0526 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0527 "MSRIndex": "0x1a6,0x1a7",
0528 "MSRValue": "0x63FC00122",
0529 "Offcore": "1",
0530 "SampleAfterValue": "100003",
0531 "UMask": "0x1"
0532 },
0533 {
0534 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
0535 "Counter": "0,1,2,3",
0536 "CounterHTOff": "0,1,2,3",
0537 "EventCode": "0xB7, 0xBB",
0538 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0539 "MSRIndex": "0x1a6,0x1a7",
0540 "MSRValue": "0x604000122",
0541 "Offcore": "1",
0542 "SampleAfterValue": "100003",
0543 "UMask": "0x1"
0544 },
0545 {
0546 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
0547 "Counter": "0,1,2,3",
0548 "CounterHTOff": "0,1,2,3",
0549 "EventCode": "0xB7, 0xBB",
0550 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0551 "MSRIndex": "0x1a6,0x1a7",
0552 "MSRValue": "0x63B800122",
0553 "Offcore": "1",
0554 "SampleAfterValue": "100003",
0555 "UMask": "0x1"
0556 },
0557 {
0558 "BriefDescription": "Counts all demand code reads that miss in the L3.",
0559 "Counter": "0,1,2,3",
0560 "CounterHTOff": "0,1,2,3",
0561 "EventCode": "0xB7, 0xBB",
0562 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
0563 "MSRIndex": "0x1a6,0x1a7",
0564 "MSRValue": "0x3FBC000004",
0565 "Offcore": "1",
0566 "SampleAfterValue": "100003",
0567 "UMask": "0x1"
0568 },
0569 {
0570 "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
0571 "Counter": "0,1,2,3",
0572 "CounterHTOff": "0,1,2,3",
0573 "EventCode": "0xB7, 0xBB",
0574 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
0575 "MSRIndex": "0x1a6,0x1a7",
0576 "MSRValue": "0x103FC00004",
0577 "Offcore": "1",
0578 "SampleAfterValue": "100003",
0579 "UMask": "0x1"
0580 },
0581 {
0582 "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
0583 "Counter": "0,1,2,3",
0584 "CounterHTOff": "0,1,2,3",
0585 "EventCode": "0xB7, 0xBB",
0586 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
0587 "MSRIndex": "0x1a6,0x1a7",
0588 "MSRValue": "0x83FC00004",
0589 "Offcore": "1",
0590 "SampleAfterValue": "100003",
0591 "UMask": "0x1"
0592 },
0593 {
0594 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
0595 "Counter": "0,1,2,3",
0596 "CounterHTOff": "0,1,2,3",
0597 "EventCode": "0xB7, 0xBB",
0598 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0599 "MSRIndex": "0x1a6,0x1a7",
0600 "MSRValue": "0x63FC00004",
0601 "Offcore": "1",
0602 "SampleAfterValue": "100003",
0603 "UMask": "0x1"
0604 },
0605 {
0606 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
0607 "Counter": "0,1,2,3",
0608 "CounterHTOff": "0,1,2,3",
0609 "EventCode": "0xB7, 0xBB",
0610 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0611 "MSRIndex": "0x1a6,0x1a7",
0612 "MSRValue": "0x604000004",
0613 "Offcore": "1",
0614 "SampleAfterValue": "100003",
0615 "UMask": "0x1"
0616 },
0617 {
0618 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
0619 "Counter": "0,1,2,3",
0620 "CounterHTOff": "0,1,2,3",
0621 "EventCode": "0xB7, 0xBB",
0622 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0623 "MSRIndex": "0x1a6,0x1a7",
0624 "MSRValue": "0x63B800004",
0625 "Offcore": "1",
0626 "SampleAfterValue": "100003",
0627 "UMask": "0x1"
0628 },
0629 {
0630 "BriefDescription": "Counts demand data reads that miss in the L3.",
0631 "Counter": "0,1,2,3",
0632 "CounterHTOff": "0,1,2,3",
0633 "EventCode": "0xB7, 0xBB",
0634 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
0635 "MSRIndex": "0x1a6,0x1a7",
0636 "MSRValue": "0x3FBC000001",
0637 "Offcore": "1",
0638 "SampleAfterValue": "100003",
0639 "UMask": "0x1"
0640 },
0641 {
0642 "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
0643 "Counter": "0,1,2,3",
0644 "CounterHTOff": "0,1,2,3",
0645 "EventCode": "0xB7, 0xBB",
0646 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
0647 "MSRIndex": "0x1a6,0x1a7",
0648 "MSRValue": "0x103FC00001",
0649 "Offcore": "1",
0650 "SampleAfterValue": "100003",
0651 "UMask": "0x1"
0652 },
0653 {
0654 "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
0655 "Counter": "0,1,2,3",
0656 "CounterHTOff": "0,1,2,3",
0657 "EventCode": "0xB7, 0xBB",
0658 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
0659 "MSRIndex": "0x1a6,0x1a7",
0660 "MSRValue": "0x83FC00001",
0661 "Offcore": "1",
0662 "SampleAfterValue": "100003",
0663 "UMask": "0x1"
0664 },
0665 {
0666 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
0667 "Counter": "0,1,2,3",
0668 "CounterHTOff": "0,1,2,3",
0669 "EventCode": "0xB7, 0xBB",
0670 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0671 "MSRIndex": "0x1a6,0x1a7",
0672 "MSRValue": "0x63FC00001",
0673 "Offcore": "1",
0674 "SampleAfterValue": "100003",
0675 "UMask": "0x1"
0676 },
0677 {
0678 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
0679 "Counter": "0,1,2,3",
0680 "CounterHTOff": "0,1,2,3",
0681 "EventCode": "0xB7, 0xBB",
0682 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0683 "MSRIndex": "0x1a6,0x1a7",
0684 "MSRValue": "0x604000001",
0685 "Offcore": "1",
0686 "SampleAfterValue": "100003",
0687 "UMask": "0x1"
0688 },
0689 {
0690 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
0691 "Counter": "0,1,2,3",
0692 "CounterHTOff": "0,1,2,3",
0693 "EventCode": "0xB7, 0xBB",
0694 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0695 "MSRIndex": "0x1a6,0x1a7",
0696 "MSRValue": "0x63B800001",
0697 "Offcore": "1",
0698 "SampleAfterValue": "100003",
0699 "UMask": "0x1"
0700 },
0701 {
0702 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
0703 "Counter": "0,1,2,3",
0704 "CounterHTOff": "0,1,2,3",
0705 "EventCode": "0xB7, 0xBB",
0706 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
0707 "MSRIndex": "0x1a6,0x1a7",
0708 "MSRValue": "0x3FBC000002",
0709 "Offcore": "1",
0710 "SampleAfterValue": "100003",
0711 "UMask": "0x1"
0712 },
0713 {
0714 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
0715 "Counter": "0,1,2,3",
0716 "CounterHTOff": "0,1,2,3",
0717 "EventCode": "0xB7, 0xBB",
0718 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
0719 "MSRIndex": "0x1a6,0x1a7",
0720 "MSRValue": "0x103FC00002",
0721 "Offcore": "1",
0722 "SampleAfterValue": "100003",
0723 "UMask": "0x1"
0724 },
0725 {
0726 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
0727 "Counter": "0,1,2,3",
0728 "CounterHTOff": "0,1,2,3",
0729 "EventCode": "0xB7, 0xBB",
0730 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
0731 "MSRIndex": "0x1a6,0x1a7",
0732 "MSRValue": "0x83FC00002",
0733 "Offcore": "1",
0734 "SampleAfterValue": "100003",
0735 "UMask": "0x1"
0736 },
0737 {
0738 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
0739 "Counter": "0,1,2,3",
0740 "CounterHTOff": "0,1,2,3",
0741 "EventCode": "0xB7, 0xBB",
0742 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0743 "MSRIndex": "0x1a6,0x1a7",
0744 "MSRValue": "0x63FC00002",
0745 "Offcore": "1",
0746 "SampleAfterValue": "100003",
0747 "UMask": "0x1"
0748 },
0749 {
0750 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
0751 "Counter": "0,1,2,3",
0752 "CounterHTOff": "0,1,2,3",
0753 "EventCode": "0xB7, 0xBB",
0754 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0755 "MSRIndex": "0x1a6,0x1a7",
0756 "MSRValue": "0x604000002",
0757 "Offcore": "1",
0758 "SampleAfterValue": "100003",
0759 "UMask": "0x1"
0760 },
0761 {
0762 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
0763 "Counter": "0,1,2,3",
0764 "CounterHTOff": "0,1,2,3",
0765 "EventCode": "0xB7, 0xBB",
0766 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0767 "MSRIndex": "0x1a6,0x1a7",
0768 "MSRValue": "0x63B800002",
0769 "Offcore": "1",
0770 "SampleAfterValue": "100003",
0771 "UMask": "0x1"
0772 },
0773 {
0774 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
0775 "Counter": "0,1,2,3",
0776 "CounterHTOff": "0,1,2,3",
0777 "EventCode": "0xB7, 0xBB",
0778 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
0779 "MSRIndex": "0x1a6,0x1a7",
0780 "MSRValue": "0x3FBC000400",
0781 "Offcore": "1",
0782 "SampleAfterValue": "100003",
0783 "UMask": "0x1"
0784 },
0785 {
0786 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
0787 "Counter": "0,1,2,3",
0788 "CounterHTOff": "0,1,2,3",
0789 "EventCode": "0xB7, 0xBB",
0790 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
0791 "MSRIndex": "0x1a6,0x1a7",
0792 "MSRValue": "0x103FC00400",
0793 "Offcore": "1",
0794 "SampleAfterValue": "100003",
0795 "UMask": "0x1"
0796 },
0797 {
0798 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
0799 "Counter": "0,1,2,3",
0800 "CounterHTOff": "0,1,2,3",
0801 "EventCode": "0xB7, 0xBB",
0802 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
0803 "MSRIndex": "0x1a6,0x1a7",
0804 "MSRValue": "0x83FC00400",
0805 "Offcore": "1",
0806 "SampleAfterValue": "100003",
0807 "UMask": "0x1"
0808 },
0809 {
0810 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
0811 "Counter": "0,1,2,3",
0812 "CounterHTOff": "0,1,2,3",
0813 "EventCode": "0xB7, 0xBB",
0814 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0815 "MSRIndex": "0x1a6,0x1a7",
0816 "MSRValue": "0x63FC00400",
0817 "Offcore": "1",
0818 "SampleAfterValue": "100003",
0819 "UMask": "0x1"
0820 },
0821 {
0822 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
0823 "Counter": "0,1,2,3",
0824 "CounterHTOff": "0,1,2,3",
0825 "EventCode": "0xB7, 0xBB",
0826 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0827 "MSRIndex": "0x1a6,0x1a7",
0828 "MSRValue": "0x604000400",
0829 "Offcore": "1",
0830 "SampleAfterValue": "100003",
0831 "UMask": "0x1"
0832 },
0833 {
0834 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
0835 "Counter": "0,1,2,3",
0836 "CounterHTOff": "0,1,2,3",
0837 "EventCode": "0xB7, 0xBB",
0838 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0839 "MSRIndex": "0x1a6,0x1a7",
0840 "MSRValue": "0x63B800400",
0841 "Offcore": "1",
0842 "SampleAfterValue": "100003",
0843 "UMask": "0x1"
0844 },
0845 {
0846 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
0847 "Counter": "0,1,2,3",
0848 "CounterHTOff": "0,1,2,3",
0849 "EventCode": "0xB7, 0xBB",
0850 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
0851 "MSRIndex": "0x1a6,0x1a7",
0852 "MSRValue": "0x3FBC000010",
0853 "Offcore": "1",
0854 "SampleAfterValue": "100003",
0855 "UMask": "0x1"
0856 },
0857 {
0858 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
0859 "Counter": "0,1,2,3",
0860 "CounterHTOff": "0,1,2,3",
0861 "EventCode": "0xB7, 0xBB",
0862 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
0863 "MSRIndex": "0x1a6,0x1a7",
0864 "MSRValue": "0x103FC00010",
0865 "Offcore": "1",
0866 "SampleAfterValue": "100003",
0867 "UMask": "0x1"
0868 },
0869 {
0870 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
0871 "Counter": "0,1,2,3",
0872 "CounterHTOff": "0,1,2,3",
0873 "EventCode": "0xB7, 0xBB",
0874 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
0875 "MSRIndex": "0x1a6,0x1a7",
0876 "MSRValue": "0x83FC00010",
0877 "Offcore": "1",
0878 "SampleAfterValue": "100003",
0879 "UMask": "0x1"
0880 },
0881 {
0882 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
0883 "Counter": "0,1,2,3",
0884 "CounterHTOff": "0,1,2,3",
0885 "EventCode": "0xB7, 0xBB",
0886 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0887 "MSRIndex": "0x1a6,0x1a7",
0888 "MSRValue": "0x63FC00010",
0889 "Offcore": "1",
0890 "SampleAfterValue": "100003",
0891 "UMask": "0x1"
0892 },
0893 {
0894 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
0895 "Counter": "0,1,2,3",
0896 "CounterHTOff": "0,1,2,3",
0897 "EventCode": "0xB7, 0xBB",
0898 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0899 "MSRIndex": "0x1a6,0x1a7",
0900 "MSRValue": "0x604000010",
0901 "Offcore": "1",
0902 "SampleAfterValue": "100003",
0903 "UMask": "0x1"
0904 },
0905 {
0906 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
0907 "Counter": "0,1,2,3",
0908 "CounterHTOff": "0,1,2,3",
0909 "EventCode": "0xB7, 0xBB",
0910 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0911 "MSRIndex": "0x1a6,0x1a7",
0912 "MSRValue": "0x63B800010",
0913 "Offcore": "1",
0914 "SampleAfterValue": "100003",
0915 "UMask": "0x1"
0916 },
0917 {
0918 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
0919 "Counter": "0,1,2,3",
0920 "CounterHTOff": "0,1,2,3",
0921 "EventCode": "0xB7, 0xBB",
0922 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
0923 "MSRIndex": "0x1a6,0x1a7",
0924 "MSRValue": "0x3FBC000020",
0925 "Offcore": "1",
0926 "SampleAfterValue": "100003",
0927 "UMask": "0x1"
0928 },
0929 {
0930 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
0931 "Counter": "0,1,2,3",
0932 "CounterHTOff": "0,1,2,3",
0933 "EventCode": "0xB7, 0xBB",
0934 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
0935 "MSRIndex": "0x1a6,0x1a7",
0936 "MSRValue": "0x103FC00020",
0937 "Offcore": "1",
0938 "SampleAfterValue": "100003",
0939 "UMask": "0x1"
0940 },
0941 {
0942 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
0943 "Counter": "0,1,2,3",
0944 "CounterHTOff": "0,1,2,3",
0945 "EventCode": "0xB7, 0xBB",
0946 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
0947 "MSRIndex": "0x1a6,0x1a7",
0948 "MSRValue": "0x83FC00020",
0949 "Offcore": "1",
0950 "SampleAfterValue": "100003",
0951 "UMask": "0x1"
0952 },
0953 {
0954 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
0955 "Counter": "0,1,2,3",
0956 "CounterHTOff": "0,1,2,3",
0957 "EventCode": "0xB7, 0xBB",
0958 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
0959 "MSRIndex": "0x1a6,0x1a7",
0960 "MSRValue": "0x63FC00020",
0961 "Offcore": "1",
0962 "SampleAfterValue": "100003",
0963 "UMask": "0x1"
0964 },
0965 {
0966 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
0967 "Counter": "0,1,2,3",
0968 "CounterHTOff": "0,1,2,3",
0969 "EventCode": "0xB7, 0xBB",
0970 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
0971 "MSRIndex": "0x1a6,0x1a7",
0972 "MSRValue": "0x604000020",
0973 "Offcore": "1",
0974 "SampleAfterValue": "100003",
0975 "UMask": "0x1"
0976 },
0977 {
0978 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
0979 "Counter": "0,1,2,3",
0980 "CounterHTOff": "0,1,2,3",
0981 "EventCode": "0xB7, 0xBB",
0982 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
0983 "MSRIndex": "0x1a6,0x1a7",
0984 "MSRValue": "0x63B800020",
0985 "Offcore": "1",
0986 "SampleAfterValue": "100003",
0987 "UMask": "0x1"
0988 },
0989 {
0990 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
0991 "Counter": "0,1,2,3",
0992 "CounterHTOff": "0,1,2,3",
0993 "EventCode": "0xB7, 0xBB",
0994 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
0995 "MSRIndex": "0x1a6,0x1a7",
0996 "MSRValue": "0x3FBC000080",
0997 "Offcore": "1",
0998 "SampleAfterValue": "100003",
0999 "UMask": "0x1"
1000 },
1001 {
1002 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
1003 "Counter": "0,1,2,3",
1004 "CounterHTOff": "0,1,2,3",
1005 "EventCode": "0xB7, 0xBB",
1006 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
1007 "MSRIndex": "0x1a6,0x1a7",
1008 "MSRValue": "0x103FC00080",
1009 "Offcore": "1",
1010 "SampleAfterValue": "100003",
1011 "UMask": "0x1"
1012 },
1013 {
1014 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
1015 "Counter": "0,1,2,3",
1016 "CounterHTOff": "0,1,2,3",
1017 "EventCode": "0xB7, 0xBB",
1018 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
1019 "MSRIndex": "0x1a6,0x1a7",
1020 "MSRValue": "0x83FC00080",
1021 "Offcore": "1",
1022 "SampleAfterValue": "100003",
1023 "UMask": "0x1"
1024 },
1025 {
1026 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
1027 "Counter": "0,1,2,3",
1028 "CounterHTOff": "0,1,2,3",
1029 "EventCode": "0xB7, 0xBB",
1030 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1031 "MSRIndex": "0x1a6,0x1a7",
1032 "MSRValue": "0x63FC00080",
1033 "Offcore": "1",
1034 "SampleAfterValue": "100003",
1035 "UMask": "0x1"
1036 },
1037 {
1038 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
1039 "Counter": "0,1,2,3",
1040 "CounterHTOff": "0,1,2,3",
1041 "EventCode": "0xB7, 0xBB",
1042 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1043 "MSRIndex": "0x1a6,0x1a7",
1044 "MSRValue": "0x604000080",
1045 "Offcore": "1",
1046 "SampleAfterValue": "100003",
1047 "UMask": "0x1"
1048 },
1049 {
1050 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
1051 "Counter": "0,1,2,3",
1052 "CounterHTOff": "0,1,2,3",
1053 "EventCode": "0xB7, 0xBB",
1054 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1055 "MSRIndex": "0x1a6,0x1a7",
1056 "MSRValue": "0x63B800080",
1057 "Offcore": "1",
1058 "SampleAfterValue": "100003",
1059 "UMask": "0x1"
1060 },
1061 {
1062 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
1063 "Counter": "0,1,2,3",
1064 "CounterHTOff": "0,1,2,3",
1065 "EventCode": "0xB7, 0xBB",
1066 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
1067 "MSRIndex": "0x1a6,0x1a7",
1068 "MSRValue": "0x3FBC000100",
1069 "Offcore": "1",
1070 "SampleAfterValue": "100003",
1071 "UMask": "0x1"
1072 },
1073 {
1074 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
1075 "Counter": "0,1,2,3",
1076 "CounterHTOff": "0,1,2,3",
1077 "EventCode": "0xB7, 0xBB",
1078 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
1079 "MSRIndex": "0x1a6,0x1a7",
1080 "MSRValue": "0x103FC00100",
1081 "Offcore": "1",
1082 "SampleAfterValue": "100003",
1083 "UMask": "0x1"
1084 },
1085 {
1086 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
1087 "Counter": "0,1,2,3",
1088 "CounterHTOff": "0,1,2,3",
1089 "EventCode": "0xB7, 0xBB",
1090 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
1091 "MSRIndex": "0x1a6,0x1a7",
1092 "MSRValue": "0x83FC00100",
1093 "Offcore": "1",
1094 "SampleAfterValue": "100003",
1095 "UMask": "0x1"
1096 },
1097 {
1098 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
1099 "Counter": "0,1,2,3",
1100 "CounterHTOff": "0,1,2,3",
1101 "EventCode": "0xB7, 0xBB",
1102 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1103 "MSRIndex": "0x1a6,0x1a7",
1104 "MSRValue": "0x63FC00100",
1105 "Offcore": "1",
1106 "SampleAfterValue": "100003",
1107 "UMask": "0x1"
1108 },
1109 {
1110 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
1111 "Counter": "0,1,2,3",
1112 "CounterHTOff": "0,1,2,3",
1113 "EventCode": "0xB7, 0xBB",
1114 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1115 "MSRIndex": "0x1a6,0x1a7",
1116 "MSRValue": "0x604000100",
1117 "Offcore": "1",
1118 "SampleAfterValue": "100003",
1119 "UMask": "0x1"
1120 },
1121 {
1122 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
1123 "Counter": "0,1,2,3",
1124 "CounterHTOff": "0,1,2,3",
1125 "EventCode": "0xB7, 0xBB",
1126 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1127 "MSRIndex": "0x1a6,0x1a7",
1128 "MSRValue": "0x63B800100",
1129 "Offcore": "1",
1130 "SampleAfterValue": "100003",
1131 "UMask": "0x1"
1132 },
1133 {
1134 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
1135 "Counter": "0,1,2,3",
1136 "CounterHTOff": "0,1,2,3,4,5,6,7",
1137 "EventCode": "0xC9",
1138 "EventName": "RTM_RETIRED.ABORTED",
1139 "PEBS": "1",
1140 "PublicDescription": "Number of times RTM abort was triggered.",
1141 "SampleAfterValue": "2000003",
1142 "UMask": "0x4"
1143 },
1144 {
1145 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
1146 "Counter": "0,1,2,3",
1147 "CounterHTOff": "0,1,2,3,4,5,6,7",
1148 "EventCode": "0xC9",
1149 "EventName": "RTM_RETIRED.ABORTED_EVENTS",
1150 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
1151 "SampleAfterValue": "2000003",
1152 "UMask": "0x80"
1153 },
1154 {
1155 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
1156 "Counter": "0,1,2,3",
1157 "CounterHTOff": "0,1,2,3,4,5,6,7",
1158 "EventCode": "0xC9",
1159 "EventName": "RTM_RETIRED.ABORTED_MEM",
1160 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
1161 "SampleAfterValue": "2000003",
1162 "UMask": "0x8"
1163 },
1164 {
1165 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
1166 "Counter": "0,1,2,3",
1167 "CounterHTOff": "0,1,2,3,4,5,6,7",
1168 "EventCode": "0xC9",
1169 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
1170 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
1171 "SampleAfterValue": "2000003",
1172 "UMask": "0x40"
1173 },
1174 {
1175 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
1176 "Counter": "0,1,2,3",
1177 "CounterHTOff": "0,1,2,3,4,5,6,7",
1178 "EventCode": "0xC9",
1179 "EventName": "RTM_RETIRED.ABORTED_TIMER",
1180 "SampleAfterValue": "2000003",
1181 "UMask": "0x10"
1182 },
1183 {
1184 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
1185 "Counter": "0,1,2,3",
1186 "CounterHTOff": "0,1,2,3,4,5,6,7",
1187 "EventCode": "0xC9",
1188 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
1189 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
1190 "SampleAfterValue": "2000003",
1191 "UMask": "0x20"
1192 },
1193 {
1194 "BriefDescription": "Number of times an RTM execution successfully committed",
1195 "Counter": "0,1,2,3",
1196 "CounterHTOff": "0,1,2,3,4,5,6,7",
1197 "EventCode": "0xC9",
1198 "EventName": "RTM_RETIRED.COMMIT",
1199 "PublicDescription": "Number of times RTM commit succeeded.",
1200 "SampleAfterValue": "2000003",
1201 "UMask": "0x2"
1202 },
1203 {
1204 "BriefDescription": "Number of times an RTM execution started.",
1205 "Counter": "0,1,2,3",
1206 "CounterHTOff": "0,1,2,3,4,5,6,7",
1207 "EventCode": "0xC9",
1208 "EventName": "RTM_RETIRED.START",
1209 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
1210 "SampleAfterValue": "2000003",
1211 "UMask": "0x1"
1212 },
1213 {
1214 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1215 "Counter": "0,1,2,3",
1216 "CounterHTOff": "0,1,2,3,4,5,6,7",
1217 "EventCode": "0x5d",
1218 "EventName": "TX_EXEC.MISC1",
1219 "SampleAfterValue": "2000003",
1220 "UMask": "0x1"
1221 },
1222 {
1223 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1224 "Counter": "0,1,2,3",
1225 "CounterHTOff": "0,1,2,3,4,5,6,7",
1226 "EventCode": "0x5d",
1227 "EventName": "TX_EXEC.MISC2",
1228 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
1229 "SampleAfterValue": "2000003",
1230 "UMask": "0x2"
1231 },
1232 {
1233 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1234 "Counter": "0,1,2,3",
1235 "CounterHTOff": "0,1,2,3,4,5,6,7",
1236 "EventCode": "0x5d",
1237 "EventName": "TX_EXEC.MISC3",
1238 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
1239 "SampleAfterValue": "2000003",
1240 "UMask": "0x4"
1241 },
1242 {
1243 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1244 "Counter": "0,1,2,3",
1245 "CounterHTOff": "0,1,2,3,4,5,6,7",
1246 "EventCode": "0x5d",
1247 "EventName": "TX_EXEC.MISC4",
1248 "PublicDescription": "RTM region detected inside HLE.",
1249 "SampleAfterValue": "2000003",
1250 "UMask": "0x8"
1251 },
1252 {
1253 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1254 "Counter": "0,1,2,3",
1255 "CounterHTOff": "0,1,2,3,4,5,6,7",
1256 "EventCode": "0x5d",
1257 "EventName": "TX_EXEC.MISC5",
1258 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
1259 "SampleAfterValue": "2000003",
1260 "UMask": "0x10"
1261 },
1262 {
1263 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1264 "Counter": "0,1,2,3",
1265 "CounterHTOff": "0,1,2,3,4,5,6,7",
1266 "EventCode": "0x54",
1267 "EventName": "TX_MEM.ABORT_CAPACITY",
1268 "SampleAfterValue": "2000003",
1269 "UMask": "0x2"
1270 },
1271 {
1272 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1273 "Counter": "0,1,2,3",
1274 "CounterHTOff": "0,1,2,3,4,5,6,7",
1275 "EventCode": "0x54",
1276 "EventName": "TX_MEM.ABORT_CONFLICT",
1277 "PublicDescription": "Number of times a TSX line had a cache conflict.",
1278 "SampleAfterValue": "2000003",
1279 "UMask": "0x1"
1280 },
1281 {
1282 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1283 "Counter": "0,1,2,3",
1284 "CounterHTOff": "0,1,2,3,4,5,6,7",
1285 "EventCode": "0x54",
1286 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1287 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
1288 "SampleAfterValue": "2000003",
1289 "UMask": "0x10"
1290 },
1291 {
1292 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1293 "Counter": "0,1,2,3",
1294 "CounterHTOff": "0,1,2,3,4,5,6,7",
1295 "EventCode": "0x54",
1296 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1297 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
1298 "SampleAfterValue": "2000003",
1299 "UMask": "0x8"
1300 },
1301 {
1302 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1303 "Counter": "0,1,2,3",
1304 "CounterHTOff": "0,1,2,3,4,5,6,7",
1305 "EventCode": "0x54",
1306 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1307 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
1308 "SampleAfterValue": "2000003",
1309 "UMask": "0x20"
1310 },
1311 {
1312 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1313 "Counter": "0,1,2,3",
1314 "CounterHTOff": "0,1,2,3,4,5,6,7",
1315 "EventCode": "0x54",
1316 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1317 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
1318 "SampleAfterValue": "2000003",
1319 "UMask": "0x4"
1320 },
1321 {
1322 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1323 "Counter": "0,1,2,3",
1324 "CounterHTOff": "0,1,2,3,4,5,6,7",
1325 "EventCode": "0x54",
1326 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1327 "PublicDescription": "Number of times we could not allocate Lock Buffer.",
1328 "SampleAfterValue": "2000003",
1329 "UMask": "0x40"
1330 }
1331 ]
