0001 [
0002 {
0003 "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
0004 "Counter": "0,1",
0005 "EventCode": "0x84",
0006 "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
0007 "PerPkg": "1",
0008 "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
0009 "UMask": "0x01",
0010 "Unit": "ARB"
0011 },
0012 {
0013 "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
0014 "EventCode": "0x80",
0015 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
0016 "PerPkg": "1",
0017 "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
0018 "UMask": "0x01",
0019 "Unit": "ARB"
0020 },
0021 {
0022 "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
0023 "CounterMask": "1",
0024 "EventCode": "0x80",
0025 "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
0026 "PerPkg": "1",
0027 "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
0028 "UMask": "0x01",
0029 "Unit": "ARB"
0030 },
0031 {
0032 "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
0033 "EventCode": "0x80",
0034 "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
0035 "PerPkg": "1",
0036 "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
0037 "UMask": "0x02",
0038 "Unit": "ARB"
0039 },
0040 {
0041 "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
0042 "Counter": "0,1",
0043 "EventCode": "0x81",
0044 "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
0045 "PerPkg": "1",
0046 "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
0047 "UMask": "0x02",
0048 "Unit": "ARB"
0049 },
0050 {
0051 "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
0052 "Counter": "0,1",
0053 "EventCode": "0x81",
0054 "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
0055 "PerPkg": "1",
0056 "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
0057 "UMask": "0x02",
0058 "Unit": "ARB"
0059 },
0060 {
0061 "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
0062 "Counter": "0,1",
0063 "EventCode": "0x81",
0064 "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
0065 "PerPkg": "1",
0066 "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
0067 "UMask": "0x20",
0068 "Unit": "ARB"
0069 },
0070 {
0071 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
0072 "Counter": "FIXED",
0073 "EventCode": "0xff",
0074 "EventName": "UNC_CLOCK.SOCKET",
0075 "PerPkg": "1",
0076 "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
0077 "Unit": "CLOCK"
0078 }
0079 ]
