0001 [
0002 {
0003 "BriefDescription": "ARITH.FPDIV_ACTIVE",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "CounterMask": "1",
0007 "EventCode": "0xb0",
0008 "EventName": "ARITH.FPDIV_ACTIVE",
0009 "PEBScounters": "0,1,2,3,4,5,6,7",
0010 "SampleAfterValue": "1000003",
0011 "Speculative": "1",
0012 "UMask": "0x1"
0013 },
0014 {
0015 "BriefDescription": "Counts all microcode FP assists.",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5,6,7",
0018 "EventCode": "0xc1",
0019 "EventName": "ASSISTS.FP",
0020 "PEBScounters": "0,1,2,3,4,5,6,7",
0021 "PublicDescription": "Counts all microcode Floating Point assists.",
0022 "SampleAfterValue": "100003",
0023 "Speculative": "1",
0024 "UMask": "0x2"
0025 },
0026 {
0027 "BriefDescription": "ASSISTS.SSE_AVX_MIX",
0028 "CollectPEBSRecord": "2",
0029 "Counter": "0,1,2,3,4,5,6,7",
0030 "EventCode": "0xc1",
0031 "EventName": "ASSISTS.SSE_AVX_MIX",
0032 "PEBScounters": "0,1,2,3,4,5,6,7",
0033 "SampleAfterValue": "1000003",
0034 "Speculative": "1",
0035 "UMask": "0x10"
0036 },
0037 {
0038 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
0039 "CollectPEBSRecord": "2",
0040 "Counter": "0,1,2,3,4,5,6,7",
0041 "EventCode": "0xb3",
0042 "EventName": "FP_ARITH_DISPATCHED.PORT_0",
0043 "PEBScounters": "0,1,2,3,4,5,6,7",
0044 "SampleAfterValue": "2000003",
0045 "Speculative": "1",
0046 "UMask": "0x1"
0047 },
0048 {
0049 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
0050 "CollectPEBSRecord": "2",
0051 "Counter": "0,1,2,3,4,5,6,7",
0052 "EventCode": "0xb3",
0053 "EventName": "FP_ARITH_DISPATCHED.PORT_1",
0054 "PEBScounters": "0,1,2,3,4,5,6,7",
0055 "SampleAfterValue": "2000003",
0056 "Speculative": "1",
0057 "UMask": "0x2"
0058 },
0059 {
0060 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
0061 "CollectPEBSRecord": "2",
0062 "Counter": "0,1,2,3,4,5,6,7",
0063 "EventCode": "0xb3",
0064 "EventName": "FP_ARITH_DISPATCHED.PORT_5",
0065 "PEBScounters": "0,1,2,3,4,5,6,7",
0066 "SampleAfterValue": "2000003",
0067 "Speculative": "1",
0068 "UMask": "0x4"
0069 },
0070 {
0071 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0072 "CollectPEBSRecord": "2",
0073 "Counter": "0,1,2,3,4,5,6,7",
0074 "EventCode": "0xc7",
0075 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
0076 "PEBScounters": "0,1,2,3,4,5,6,7",
0077 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0078 "SampleAfterValue": "100003",
0079 "UMask": "0x4"
0080 },
0081 {
0082 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0083 "CollectPEBSRecord": "2",
0084 "Counter": "0,1,2,3,4,5,6,7",
0085 "EventCode": "0xc7",
0086 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
0087 "PEBScounters": "0,1,2,3,4,5,6,7",
0088 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0089 "SampleAfterValue": "100003",
0090 "UMask": "0x8"
0091 },
0092 {
0093 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0094 "CollectPEBSRecord": "2",
0095 "Counter": "0,1,2,3,4,5,6,7",
0096 "EventCode": "0xc7",
0097 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
0098 "PEBScounters": "0,1,2,3,4,5,6,7",
0099 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0100 "SampleAfterValue": "100003",
0101 "UMask": "0x10"
0102 },
0103 {
0104 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0105 "CollectPEBSRecord": "2",
0106 "Counter": "0,1,2,3,4,5,6,7",
0107 "EventCode": "0xc7",
0108 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
0109 "PEBScounters": "0,1,2,3,4,5,6,7",
0110 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0111 "SampleAfterValue": "100003",
0112 "UMask": "0x20"
0113 },
0114 {
0115 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0116 "CollectPEBSRecord": "2",
0117 "Counter": "0,1,2,3,4,5,6,7",
0118 "EventCode": "0xc7",
0119 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
0120 "PEBScounters": "0,1,2,3,4,5,6,7",
0121 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0122 "SampleAfterValue": "100003",
0123 "UMask": "0x40"
0124 },
0125 {
0126 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0127 "CollectPEBSRecord": "2",
0128 "Counter": "0,1,2,3,4,5,6,7",
0129 "EventCode": "0xc7",
0130 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
0131 "PEBScounters": "0,1,2,3,4,5,6,7",
0132 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0133 "SampleAfterValue": "100003",
0134 "UMask": "0x80"
0135 },
0136 {
0137 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0138 "CollectPEBSRecord": "2",
0139 "Counter": "0,1,2,3,4,5,6,7",
0140 "EventCode": "0xc7",
0141 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
0142 "PEBScounters": "0,1,2,3,4,5,6,7",
0143 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0144 "SampleAfterValue": "100003",
0145 "UMask": "0x1"
0146 },
0147 {
0148 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0149 "CollectPEBSRecord": "2",
0150 "Counter": "0,1,2,3,4,5,6,7",
0151 "EventCode": "0xc7",
0152 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
0153 "PEBScounters": "0,1,2,3,4,5,6,7",
0154 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0155 "SampleAfterValue": "100003",
0156 "UMask": "0x2"
0157 },
0158 {
0159 "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
0160 "Counter": "0,1,2,3,4,5,6,7",
0161 "EventCode": "0xcf",
0162 "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
0163 "PEBScounters": "0,1,2,3,4,5,6,7",
0164 "SampleAfterValue": "100003",
0165 "UMask": "0x4"
0166 },
0167 {
0168 "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
0169 "Counter": "0,1,2,3,4,5,6,7",
0170 "EventCode": "0xcf",
0171 "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
0172 "PEBScounters": "0,1,2,3,4,5,6,7",
0173 "SampleAfterValue": "100003",
0174 "UMask": "0x8"
0175 },
0176 {
0177 "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
0178 "CollectPEBSRecord": "2",
0179 "Counter": "0,1,2,3,4,5,6,7",
0180 "EventCode": "0xcf",
0181 "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
0182 "PEBScounters": "0,1,2,3,4,5,6,7",
0183 "SampleAfterValue": "100003",
0184 "UMask": "0x10"
0185 },
0186 {
0187 "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
0188 "Counter": "0,1,2,3,4,5,6,7",
0189 "EventCode": "0xcf",
0190 "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
0191 "PEBScounters": "0,1,2,3,4,5,6,7",
0192 "SampleAfterValue": "100003",
0193 "UMask": "0x2"
0194 },
0195 {
0196 "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
0197 "Counter": "0,1,2,3,4,5,6,7",
0198 "EventCode": "0xcf",
0199 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
0200 "PEBScounters": "0,1,2,3,4,5,6,7",
0201 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
0202 "SampleAfterValue": "100003",
0203 "UMask": "0x3"
0204 },
0205 {
0206 "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
0207 "Counter": "0,1,2,3,4,5,6,7",
0208 "EventCode": "0xcf",
0209 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
0210 "PEBScounters": "0,1,2,3,4,5,6,7",
0211 "SampleAfterValue": "100003",
0212 "UMask": "0x1"
0213 },
0214 {
0215 "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
0216 "Counter": "0,1,2,3,4,5,6,7",
0217 "EventCode": "0xcf",
0218 "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
0219 "PEBScounters": "0,1,2,3,4,5,6,7",
0220 "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
0221 "SampleAfterValue": "100003",
0222 "UMask": "0x1c"
0223 }
0224 ]
