x86/nehalemep/virtual-memory.json

0001 [
0002     {
0003         "BriefDescription": "DTLB load misses",
0004         "Counter": "0,1,2,3",
0005         "EventCode": "0x8",
0006         "EventName": "DTLB_LOAD_MISSES.ANY",
0007         "SampleAfterValue": "200000",
0008         "UMask": "0x1"
0009     },
0010     {
0011         "BriefDescription": "DTLB load miss caused by low part of address",
0012         "Counter": "0,1,2,3",
0013         "EventCode": "0x8",
0014         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
0015         "SampleAfterValue": "200000",
0016         "UMask": "0x20"
0017     },
0018     {
0019         "BriefDescription": "DTLB second level hit",
0020         "Counter": "0,1,2,3",
0021         "EventCode": "0x8",
0022         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
0023         "SampleAfterValue": "2000000",
0024         "UMask": "0x10"
0025     },
0026     {
0027         "BriefDescription": "DTLB load miss page walks complete",
0028         "Counter": "0,1,2,3",
0029         "EventCode": "0x8",
0030         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0031         "SampleAfterValue": "200000",
0032         "UMask": "0x2"
0033     },
0034     {
0035         "BriefDescription": "DTLB misses",
0036         "Counter": "0,1,2,3",
0037         "EventCode": "0x49",
0038         "EventName": "DTLB_MISSES.ANY",
0039         "SampleAfterValue": "200000",
0040         "UMask": "0x1"
0041     },
0042     {
0043         "BriefDescription": "DTLB first level misses but second level hit",
0044         "Counter": "0,1,2,3",
0045         "EventCode": "0x49",
0046         "EventName": "DTLB_MISSES.STLB_HIT",
0047         "SampleAfterValue": "200000",
0048         "UMask": "0x10"
0049     },
0050     {
0051         "BriefDescription": "DTLB miss page walks",
0052         "Counter": "0,1,2,3",
0053         "EventCode": "0x49",
0054         "EventName": "DTLB_MISSES.WALK_COMPLETED",
0055         "SampleAfterValue": "200000",
0056         "UMask": "0x2"
0057     },
0058     {
0059         "BriefDescription": "ITLB flushes",
0060         "Counter": "0,1,2,3",
0061         "EventCode": "0xAE",
0062         "EventName": "ITLB_FLUSH",
0063         "SampleAfterValue": "2000000",
0064         "UMask": "0x1"
0065     },
0066     {
0067         "BriefDescription": "ITLB miss",
0068         "Counter": "0,1,2,3",
0069         "EventCode": "0x85",
0070         "EventName": "ITLB_MISSES.ANY",
0071         "SampleAfterValue": "200000",
0072         "UMask": "0x1"
0073     },
0074     {
0075         "BriefDescription": "ITLB miss page walks",
0076         "Counter": "0,1,2,3",
0077         "EventCode": "0x85",
0078         "EventName": "ITLB_MISSES.WALK_COMPLETED",
0079         "SampleAfterValue": "200000",
0080         "UMask": "0x2"
0081     },
0082     {
0083         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
0084         "Counter": "0,1,2,3",
0085         "EventCode": "0xC8",
0086         "EventName": "ITLB_MISS_RETIRED",
0087         "PEBS": "1",
0088         "SampleAfterValue": "200000",
0089         "UMask": "0x20"
0090     },
0091     {
0092         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
0093         "Counter": "0,1,2,3",
0094         "EventCode": "0xCB",
0095         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
0096         "PEBS": "1",
0097         "SampleAfterValue": "200000",
0098         "UMask": "0x80"
0099     },
0100     {
0101         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
0102         "Counter": "0,1,2,3",
0103         "EventCode": "0xC",
0104         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
0105         "PEBS": "1",
0106         "SampleAfterValue": "200000",
0107         "UMask": "0x1"
0108     }
0109 ]