0001 [
0002 {
0003 "BriefDescription": "Cycles the divider is busy",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0x14",
0006 "EventName": "ARITH.CYCLES_DIV_BUSY",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0x1"
0009 },
0010 {
0011 "BriefDescription": "Divide Operations executed",
0012 "Counter": "0,1,2,3",
0013 "CounterMask": "1",
0014 "EdgeDetect": "1",
0015 "EventCode": "0x14",
0016 "EventName": "ARITH.DIV",
0017 "Invert": "1",
0018 "SampleAfterValue": "2000000",
0019 "UMask": "0x1"
0020 },
0021 {
0022 "BriefDescription": "Multiply operations executed",
0023 "Counter": "0,1,2,3",
0024 "EventCode": "0x14",
0025 "EventName": "ARITH.MUL",
0026 "SampleAfterValue": "2000000",
0027 "UMask": "0x2"
0028 },
0029 {
0030 "BriefDescription": "BACLEAR asserted with bad target address",
0031 "Counter": "0,1,2,3",
0032 "EventCode": "0xE6",
0033 "EventName": "BACLEAR.BAD_TARGET",
0034 "SampleAfterValue": "2000000",
0035 "UMask": "0x2"
0036 },
0037 {
0038 "BriefDescription": "BACLEAR asserted, regardless of cause",
0039 "Counter": "0,1,2,3",
0040 "EventCode": "0xE6",
0041 "EventName": "BACLEAR.CLEAR",
0042 "SampleAfterValue": "2000000",
0043 "UMask": "0x1"
0044 },
0045 {
0046 "BriefDescription": "Instruction queue forced BACLEAR",
0047 "Counter": "0,1,2,3",
0048 "EventCode": "0xA7",
0049 "EventName": "BACLEAR_FORCE_IQ",
0050 "SampleAfterValue": "2000000",
0051 "UMask": "0x1"
0052 },
0053 {
0054 "BriefDescription": "Early Branch Prediciton Unit clears",
0055 "Counter": "0,1,2,3",
0056 "EventCode": "0xE8",
0057 "EventName": "BPU_CLEARS.EARLY",
0058 "SampleAfterValue": "2000000",
0059 "UMask": "0x1"
0060 },
0061 {
0062 "BriefDescription": "Late Branch Prediction Unit clears",
0063 "Counter": "0,1,2,3",
0064 "EventCode": "0xE8",
0065 "EventName": "BPU_CLEARS.LATE",
0066 "SampleAfterValue": "2000000",
0067 "UMask": "0x2"
0068 },
0069 {
0070 "BriefDescription": "Branch prediction unit missed call or return",
0071 "Counter": "0,1,2,3",
0072 "EventCode": "0xE5",
0073 "EventName": "BPU_MISSED_CALL_RET",
0074 "SampleAfterValue": "2000000",
0075 "UMask": "0x1"
0076 },
0077 {
0078 "BriefDescription": "Branch instructions decoded",
0079 "Counter": "0,1,2,3",
0080 "EventCode": "0xE0",
0081 "EventName": "BR_INST_DECODED",
0082 "SampleAfterValue": "2000000",
0083 "UMask": "0x1"
0084 },
0085 {
0086 "BriefDescription": "Branch instructions executed",
0087 "Counter": "0,1,2,3",
0088 "EventCode": "0x88",
0089 "EventName": "BR_INST_EXEC.ANY",
0090 "SampleAfterValue": "200000",
0091 "UMask": "0x7f"
0092 },
0093 {
0094 "BriefDescription": "Conditional branch instructions executed",
0095 "Counter": "0,1,2,3",
0096 "EventCode": "0x88",
0097 "EventName": "BR_INST_EXEC.COND",
0098 "SampleAfterValue": "200000",
0099 "UMask": "0x1"
0100 },
0101 {
0102 "BriefDescription": "Unconditional branches executed",
0103 "Counter": "0,1,2,3",
0104 "EventCode": "0x88",
0105 "EventName": "BR_INST_EXEC.DIRECT",
0106 "SampleAfterValue": "200000",
0107 "UMask": "0x2"
0108 },
0109 {
0110 "BriefDescription": "Unconditional call branches executed",
0111 "Counter": "0,1,2,3",
0112 "EventCode": "0x88",
0113 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
0114 "SampleAfterValue": "20000",
0115 "UMask": "0x10"
0116 },
0117 {
0118 "BriefDescription": "Indirect call branches executed",
0119 "Counter": "0,1,2,3",
0120 "EventCode": "0x88",
0121 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
0122 "SampleAfterValue": "20000",
0123 "UMask": "0x20"
0124 },
0125 {
0126 "BriefDescription": "Indirect non call branches executed",
0127 "Counter": "0,1,2,3",
0128 "EventCode": "0x88",
0129 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
0130 "SampleAfterValue": "20000",
0131 "UMask": "0x4"
0132 },
0133 {
0134 "BriefDescription": "Call branches executed",
0135 "Counter": "0,1,2,3",
0136 "EventCode": "0x88",
0137 "EventName": "BR_INST_EXEC.NEAR_CALLS",
0138 "SampleAfterValue": "20000",
0139 "UMask": "0x30"
0140 },
0141 {
0142 "BriefDescription": "All non call branches executed",
0143 "Counter": "0,1,2,3",
0144 "EventCode": "0x88",
0145 "EventName": "BR_INST_EXEC.NON_CALLS",
0146 "SampleAfterValue": "200000",
0147 "UMask": "0x7"
0148 },
0149 {
0150 "BriefDescription": "Indirect return branches executed",
0151 "Counter": "0,1,2,3",
0152 "EventCode": "0x88",
0153 "EventName": "BR_INST_EXEC.RETURN_NEAR",
0154 "SampleAfterValue": "20000",
0155 "UMask": "0x8"
0156 },
0157 {
0158 "BriefDescription": "Taken branches executed",
0159 "Counter": "0,1,2,3",
0160 "EventCode": "0x88",
0161 "EventName": "BR_INST_EXEC.TAKEN",
0162 "SampleAfterValue": "200000",
0163 "UMask": "0x40"
0164 },
0165 {
0166 "BriefDescription": "Retired branch instructions (Precise Event)",
0167 "Counter": "0,1,2,3",
0168 "EventCode": "0xC4",
0169 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
0170 "PEBS": "1",
0171 "SampleAfterValue": "200000",
0172 "UMask": "0x4"
0173 },
0174 {
0175 "BriefDescription": "Retired conditional branch instructions (Precise Event)",
0176 "Counter": "0,1,2,3",
0177 "EventCode": "0xC4",
0178 "EventName": "BR_INST_RETIRED.CONDITIONAL",
0179 "PEBS": "1",
0180 "SampleAfterValue": "200000",
0181 "UMask": "0x1"
0182 },
0183 {
0184 "BriefDescription": "Retired near call instructions (Precise Event)",
0185 "Counter": "0,1,2,3",
0186 "EventCode": "0xC4",
0187 "EventName": "BR_INST_RETIRED.NEAR_CALL",
0188 "PEBS": "1",
0189 "SampleAfterValue": "20000",
0190 "UMask": "0x2"
0191 },
0192 {
0193 "BriefDescription": "Mispredicted branches executed",
0194 "Counter": "0,1,2,3",
0195 "EventCode": "0x89",
0196 "EventName": "BR_MISP_EXEC.ANY",
0197 "SampleAfterValue": "20000",
0198 "UMask": "0x7f"
0199 },
0200 {
0201 "BriefDescription": "Mispredicted conditional branches executed",
0202 "Counter": "0,1,2,3",
0203 "EventCode": "0x89",
0204 "EventName": "BR_MISP_EXEC.COND",
0205 "SampleAfterValue": "20000",
0206 "UMask": "0x1"
0207 },
0208 {
0209 "BriefDescription": "Mispredicted unconditional branches executed",
0210 "Counter": "0,1,2,3",
0211 "EventCode": "0x89",
0212 "EventName": "BR_MISP_EXEC.DIRECT",
0213 "SampleAfterValue": "20000",
0214 "UMask": "0x2"
0215 },
0216 {
0217 "BriefDescription": "Mispredicted non call branches executed",
0218 "Counter": "0,1,2,3",
0219 "EventCode": "0x89",
0220 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
0221 "SampleAfterValue": "2000",
0222 "UMask": "0x10"
0223 },
0224 {
0225 "BriefDescription": "Mispredicted indirect call branches executed",
0226 "Counter": "0,1,2,3",
0227 "EventCode": "0x89",
0228 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
0229 "SampleAfterValue": "2000",
0230 "UMask": "0x20"
0231 },
0232 {
0233 "BriefDescription": "Mispredicted indirect non call branches executed",
0234 "Counter": "0,1,2,3",
0235 "EventCode": "0x89",
0236 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
0237 "SampleAfterValue": "2000",
0238 "UMask": "0x4"
0239 },
0240 {
0241 "BriefDescription": "Mispredicted call branches executed",
0242 "Counter": "0,1,2,3",
0243 "EventCode": "0x89",
0244 "EventName": "BR_MISP_EXEC.NEAR_CALLS",
0245 "SampleAfterValue": "2000",
0246 "UMask": "0x30"
0247 },
0248 {
0249 "BriefDescription": "Mispredicted non call branches executed",
0250 "Counter": "0,1,2,3",
0251 "EventCode": "0x89",
0252 "EventName": "BR_MISP_EXEC.NON_CALLS",
0253 "SampleAfterValue": "20000",
0254 "UMask": "0x7"
0255 },
0256 {
0257 "BriefDescription": "Mispredicted return branches executed",
0258 "Counter": "0,1,2,3",
0259 "EventCode": "0x89",
0260 "EventName": "BR_MISP_EXEC.RETURN_NEAR",
0261 "SampleAfterValue": "2000",
0262 "UMask": "0x8"
0263 },
0264 {
0265 "BriefDescription": "Mispredicted taken branches executed",
0266 "Counter": "0,1,2,3",
0267 "EventCode": "0x89",
0268 "EventName": "BR_MISP_EXEC.TAKEN",
0269 "SampleAfterValue": "20000",
0270 "UMask": "0x40"
0271 },
0272 {
0273 "BriefDescription": "Mispredicted near retired calls (Precise Event)",
0274 "Counter": "0,1,2,3",
0275 "EventCode": "0xC5",
0276 "EventName": "BR_MISP_RETIRED.NEAR_CALL",
0277 "PEBS": "1",
0278 "SampleAfterValue": "2000",
0279 "UMask": "0x2"
0280 },
0281 {
0282 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
0283 "Counter": "Fixed counter 3",
0284 "EventCode": "0x0",
0285 "EventName": "CPU_CLK_UNHALTED.REF",
0286 "SampleAfterValue": "2000000",
0287 "UMask": "0x0"
0288 },
0289 {
0290 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
0291 "Counter": "0,1,2,3",
0292 "EventCode": "0x3C",
0293 "EventName": "CPU_CLK_UNHALTED.REF_P",
0294 "SampleAfterValue": "100000",
0295 "UMask": "0x1"
0296 },
0297 {
0298 "BriefDescription": "Cycles when thread is not halted (fixed counter)",
0299 "Counter": "Fixed counter 2",
0300 "EventCode": "0x0",
0301 "EventName": "CPU_CLK_UNHALTED.THREAD",
0302 "SampleAfterValue": "2000000",
0303 "UMask": "0x0"
0304 },
0305 {
0306 "BriefDescription": "Cycles when thread is not halted (programmable counter)",
0307 "Counter": "0,1,2,3",
0308 "EventCode": "0x3C",
0309 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
0310 "SampleAfterValue": "2000000",
0311 "UMask": "0x0"
0312 },
0313 {
0314 "BriefDescription": "Total CPU cycles",
0315 "Counter": "0,1,2,3",
0316 "CounterMask": "2",
0317 "EventCode": "0x3C",
0318 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
0319 "Invert": "1",
0320 "SampleAfterValue": "2000000",
0321 "UMask": "0x0"
0322 },
0323 {
0324 "BriefDescription": "Any Instruction Length Decoder stall cycles",
0325 "Counter": "0,1,2,3",
0326 "EventCode": "0x87",
0327 "EventName": "ILD_STALL.ANY",
0328 "SampleAfterValue": "2000000",
0329 "UMask": "0xf"
0330 },
0331 {
0332 "BriefDescription": "Instruction Queue full stall cycles",
0333 "Counter": "0,1,2,3",
0334 "EventCode": "0x87",
0335 "EventName": "ILD_STALL.IQ_FULL",
0336 "SampleAfterValue": "2000000",
0337 "UMask": "0x4"
0338 },
0339 {
0340 "BriefDescription": "Length Change Prefix stall cycles",
0341 "Counter": "0,1,2,3",
0342 "EventCode": "0x87",
0343 "EventName": "ILD_STALL.LCP",
0344 "SampleAfterValue": "2000000",
0345 "UMask": "0x1"
0346 },
0347 {
0348 "BriefDescription": "Stall cycles due to BPU MRU bypass",
0349 "Counter": "0,1,2,3",
0350 "EventCode": "0x87",
0351 "EventName": "ILD_STALL.MRU",
0352 "SampleAfterValue": "2000000",
0353 "UMask": "0x2"
0354 },
0355 {
0356 "BriefDescription": "Regen stall cycles",
0357 "Counter": "0,1,2,3",
0358 "EventCode": "0x87",
0359 "EventName": "ILD_STALL.REGEN",
0360 "SampleAfterValue": "2000000",
0361 "UMask": "0x8"
0362 },
0363 {
0364 "BriefDescription": "Instructions that must be decoded by decoder 0",
0365 "Counter": "0,1,2,3",
0366 "EventCode": "0x18",
0367 "EventName": "INST_DECODED.DEC0",
0368 "SampleAfterValue": "2000000",
0369 "UMask": "0x1"
0370 },
0371 {
0372 "BriefDescription": "Instructions written to instruction queue.",
0373 "Counter": "0,1,2,3",
0374 "EventCode": "0x17",
0375 "EventName": "INST_QUEUE_WRITES",
0376 "SampleAfterValue": "2000000",
0377 "UMask": "0x1"
0378 },
0379 {
0380 "BriefDescription": "Cycles instructions are written to the instruction queue",
0381 "Counter": "0,1,2,3",
0382 "EventCode": "0x1E",
0383 "EventName": "INST_QUEUE_WRITE_CYCLES",
0384 "SampleAfterValue": "2000000",
0385 "UMask": "0x1"
0386 },
0387 {
0388 "BriefDescription": "Instructions retired (fixed counter)",
0389 "Counter": "Fixed counter 1",
0390 "EventCode": "0x0",
0391 "EventName": "INST_RETIRED.ANY",
0392 "SampleAfterValue": "2000000",
0393 "UMask": "0x0"
0394 },
0395 {
0396 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
0397 "Counter": "0,1,2,3",
0398 "EventCode": "0xC0",
0399 "EventName": "INST_RETIRED.ANY_P",
0400 "PEBS": "1",
0401 "SampleAfterValue": "2000000",
0402 "UMask": "0x1"
0403 },
0404 {
0405 "BriefDescription": "Retired MMX instructions (Precise Event)",
0406 "Counter": "0,1,2,3",
0407 "EventCode": "0xC0",
0408 "EventName": "INST_RETIRED.MMX",
0409 "PEBS": "1",
0410 "SampleAfterValue": "2000000",
0411 "UMask": "0x4"
0412 },
0413 {
0414 "BriefDescription": "Total cycles (Precise Event)",
0415 "Counter": "0,1,2,3",
0416 "CounterMask": "16",
0417 "EventCode": "0xC0",
0418 "EventName": "INST_RETIRED.TOTAL_CYCLES",
0419 "Invert": "1",
0420 "PEBS": "1",
0421 "SampleAfterValue": "2000000",
0422 "UMask": "0x1"
0423 },
0424 {
0425 "BriefDescription": "Total cycles (Precise Event)",
0426 "Counter": "0,1,2,3",
0427 "CounterMask": "16",
0428 "EventCode": "0xC0",
0429 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
0430 "Invert": "1",
0431 "PEBS": "2",
0432 "SampleAfterValue": "2000000",
0433 "UMask": "0x1"
0434 },
0435 {
0436 "BriefDescription": "Retired floating-point operations (Precise Event)",
0437 "Counter": "0,1,2,3",
0438 "EventCode": "0xC0",
0439 "EventName": "INST_RETIRED.X87",
0440 "PEBS": "1",
0441 "SampleAfterValue": "2000000",
0442 "UMask": "0x2"
0443 },
0444 {
0445 "BriefDescription": "Load operations conflicting with software prefetches",
0446 "Counter": "0,1",
0447 "EventCode": "0x4C",
0448 "EventName": "LOAD_HIT_PRE",
0449 "SampleAfterValue": "200000",
0450 "UMask": "0x1"
0451 },
0452 {
0453 "BriefDescription": "Cycles when uops were delivered by the LSD",
0454 "Counter": "0,1,2,3",
0455 "CounterMask": "1",
0456 "EventCode": "0xA8",
0457 "EventName": "LSD.ACTIVE",
0458 "SampleAfterValue": "2000000",
0459 "UMask": "0x1"
0460 },
0461 {
0462 "BriefDescription": "Cycles no uops were delivered by the LSD",
0463 "Counter": "0,1,2,3",
0464 "CounterMask": "1",
0465 "EventCode": "0xA8",
0466 "EventName": "LSD.INACTIVE",
0467 "Invert": "1",
0468 "SampleAfterValue": "2000000",
0469 "UMask": "0x1"
0470 },
0471 {
0472 "BriefDescription": "Loops that can't stream from the instruction queue",
0473 "Counter": "0,1,2,3",
0474 "EventCode": "0x20",
0475 "EventName": "LSD_OVERFLOW",
0476 "SampleAfterValue": "2000000",
0477 "UMask": "0x1"
0478 },
0479 {
0480 "BriefDescription": "Cycles machine clear asserted",
0481 "Counter": "0,1,2,3",
0482 "EventCode": "0xC3",
0483 "EventName": "MACHINE_CLEARS.CYCLES",
0484 "SampleAfterValue": "20000",
0485 "UMask": "0x1"
0486 },
0487 {
0488 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
0489 "Counter": "0,1,2,3",
0490 "EventCode": "0xC3",
0491 "EventName": "MACHINE_CLEARS.MEM_ORDER",
0492 "SampleAfterValue": "20000",
0493 "UMask": "0x2"
0494 },
0495 {
0496 "BriefDescription": "Self-Modifying Code detected",
0497 "Counter": "0,1,2,3",
0498 "EventCode": "0xC3",
0499 "EventName": "MACHINE_CLEARS.SMC",
0500 "SampleAfterValue": "20000",
0501 "UMask": "0x4"
0502 },
0503 {
0504 "BriefDescription": "All RAT stall cycles",
0505 "Counter": "0,1,2,3",
0506 "EventCode": "0xD2",
0507 "EventName": "RAT_STALLS.ANY",
0508 "SampleAfterValue": "2000000",
0509 "UMask": "0xf"
0510 },
0511 {
0512 "BriefDescription": "Flag stall cycles",
0513 "Counter": "0,1,2,3",
0514 "EventCode": "0xD2",
0515 "EventName": "RAT_STALLS.FLAGS",
0516 "SampleAfterValue": "2000000",
0517 "UMask": "0x1"
0518 },
0519 {
0520 "BriefDescription": "Partial register stall cycles",
0521 "Counter": "0,1,2,3",
0522 "EventCode": "0xD2",
0523 "EventName": "RAT_STALLS.REGISTERS",
0524 "SampleAfterValue": "2000000",
0525 "UMask": "0x2"
0526 },
0527 {
0528 "BriefDescription": "ROB read port stalls cycles",
0529 "Counter": "0,1,2,3",
0530 "EventCode": "0xD2",
0531 "EventName": "RAT_STALLS.ROB_READ_PORT",
0532 "SampleAfterValue": "2000000",
0533 "UMask": "0x4"
0534 },
0535 {
0536 "BriefDescription": "Scoreboard stall cycles",
0537 "Counter": "0,1,2,3",
0538 "EventCode": "0xD2",
0539 "EventName": "RAT_STALLS.SCOREBOARD",
0540 "SampleAfterValue": "2000000",
0541 "UMask": "0x8"
0542 },
0543 {
0544 "BriefDescription": "Resource related stall cycles",
0545 "Counter": "0,1,2,3",
0546 "EventCode": "0xA2",
0547 "EventName": "RESOURCE_STALLS.ANY",
0548 "SampleAfterValue": "2000000",
0549 "UMask": "0x1"
0550 },
0551 {
0552 "BriefDescription": "FPU control word write stall cycles",
0553 "Counter": "0,1,2,3",
0554 "EventCode": "0xA2",
0555 "EventName": "RESOURCE_STALLS.FPCW",
0556 "SampleAfterValue": "2000000",
0557 "UMask": "0x20"
0558 },
0559 {
0560 "BriefDescription": "Load buffer stall cycles",
0561 "Counter": "0,1,2,3",
0562 "EventCode": "0xA2",
0563 "EventName": "RESOURCE_STALLS.LOAD",
0564 "SampleAfterValue": "2000000",
0565 "UMask": "0x2"
0566 },
0567 {
0568 "BriefDescription": "MXCSR rename stall cycles",
0569 "Counter": "0,1,2,3",
0570 "EventCode": "0xA2",
0571 "EventName": "RESOURCE_STALLS.MXCSR",
0572 "SampleAfterValue": "2000000",
0573 "UMask": "0x40"
0574 },
0575 {
0576 "BriefDescription": "Other Resource related stall cycles",
0577 "Counter": "0,1,2,3",
0578 "EventCode": "0xA2",
0579 "EventName": "RESOURCE_STALLS.OTHER",
0580 "SampleAfterValue": "2000000",
0581 "UMask": "0x80"
0582 },
0583 {
0584 "BriefDescription": "ROB full stall cycles",
0585 "Counter": "0,1,2,3",
0586 "EventCode": "0xA2",
0587 "EventName": "RESOURCE_STALLS.ROB_FULL",
0588 "SampleAfterValue": "2000000",
0589 "UMask": "0x10"
0590 },
0591 {
0592 "BriefDescription": "Reservation Station full stall cycles",
0593 "Counter": "0,1,2,3",
0594 "EventCode": "0xA2",
0595 "EventName": "RESOURCE_STALLS.RS_FULL",
0596 "SampleAfterValue": "2000000",
0597 "UMask": "0x4"
0598 },
0599 {
0600 "BriefDescription": "Store buffer stall cycles",
0601 "Counter": "0,1,2,3",
0602 "EventCode": "0xA2",
0603 "EventName": "RESOURCE_STALLS.STORE",
0604 "SampleAfterValue": "2000000",
0605 "UMask": "0x8"
0606 },
0607 {
0608 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
0609 "Counter": "0,1,2,3",
0610 "EventCode": "0xC7",
0611 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
0612 "PEBS": "1",
0613 "SampleAfterValue": "200000",
0614 "UMask": "0x4"
0615 },
0616 {
0617 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
0618 "Counter": "0,1,2,3",
0619 "EventCode": "0xC7",
0620 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
0621 "PEBS": "1",
0622 "SampleAfterValue": "200000",
0623 "UMask": "0x1"
0624 },
0625 {
0626 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
0627 "Counter": "0,1,2,3",
0628 "EventCode": "0xC7",
0629 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
0630 "PEBS": "1",
0631 "SampleAfterValue": "200000",
0632 "UMask": "0x8"
0633 },
0634 {
0635 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
0636 "Counter": "0,1,2,3",
0637 "EventCode": "0xC7",
0638 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
0639 "PEBS": "1",
0640 "SampleAfterValue": "200000",
0641 "UMask": "0x2"
0642 },
0643 {
0644 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
0645 "Counter": "0,1,2,3",
0646 "EventCode": "0xC7",
0647 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
0648 "PEBS": "1",
0649 "SampleAfterValue": "200000",
0650 "UMask": "0x10"
0651 },
0652 {
0653 "BriefDescription": "Stack pointer instructions decoded",
0654 "Counter": "0,1,2,3",
0655 "EventCode": "0xD1",
0656 "EventName": "UOPS_DECODED.ESP_FOLDING",
0657 "SampleAfterValue": "2000000",
0658 "UMask": "0x4"
0659 },
0660 {
0661 "BriefDescription": "Stack pointer sync operations",
0662 "Counter": "0,1,2,3",
0663 "EventCode": "0xD1",
0664 "EventName": "UOPS_DECODED.ESP_SYNC",
0665 "SampleAfterValue": "2000000",
0666 "UMask": "0x8"
0667 },
0668 {
0669 "BriefDescription": "Uops decoded by Microcode Sequencer",
0670 "Counter": "0,1,2,3",
0671 "CounterMask": "1",
0672 "EventCode": "0xD1",
0673 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
0674 "SampleAfterValue": "2000000",
0675 "UMask": "0x2"
0676 },
0677 {
0678 "BriefDescription": "Cycles no Uops are decoded",
0679 "Counter": "0,1,2,3",
0680 "CounterMask": "1",
0681 "EventCode": "0xD1",
0682 "EventName": "UOPS_DECODED.STALL_CYCLES",
0683 "Invert": "1",
0684 "SampleAfterValue": "2000000",
0685 "UMask": "0x1"
0686 },
0687 {
0688 "AnyThread": "1",
0689 "BriefDescription": "Cycles Uops executed on any port (core count)",
0690 "Counter": "0,1,2,3",
0691 "CounterMask": "1",
0692 "EventCode": "0xB1",
0693 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
0694 "SampleAfterValue": "2000000",
0695 "UMask": "0x3f"
0696 },
0697 {
0698 "AnyThread": "1",
0699 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
0700 "Counter": "0,1,2,3",
0701 "CounterMask": "1",
0702 "EventCode": "0xB1",
0703 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
0704 "SampleAfterValue": "2000000",
0705 "UMask": "0x1f"
0706 },
0707 {
0708 "AnyThread": "1",
0709 "BriefDescription": "Uops executed on any port (core count)",
0710 "Counter": "0,1,2,3",
0711 "CounterMask": "1",
0712 "EdgeDetect": "1",
0713 "EventCode": "0xB1",
0714 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
0715 "Invert": "1",
0716 "SampleAfterValue": "2000000",
0717 "UMask": "0x3f"
0718 },
0719 {
0720 "AnyThread": "1",
0721 "BriefDescription": "Uops executed on ports 0-4 (core count)",
0722 "Counter": "0,1,2,3",
0723 "CounterMask": "1",
0724 "EdgeDetect": "1",
0725 "EventCode": "0xB1",
0726 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
0727 "Invert": "1",
0728 "SampleAfterValue": "2000000",
0729 "UMask": "0x1f"
0730 },
0731 {
0732 "AnyThread": "1",
0733 "BriefDescription": "Cycles no Uops issued on any port (core count)",
0734 "Counter": "0,1,2,3",
0735 "CounterMask": "1",
0736 "EventCode": "0xB1",
0737 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
0738 "Invert": "1",
0739 "SampleAfterValue": "2000000",
0740 "UMask": "0x3f"
0741 },
0742 {
0743 "AnyThread": "1",
0744 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
0745 "Counter": "0,1,2,3",
0746 "CounterMask": "1",
0747 "EventCode": "0xB1",
0748 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
0749 "Invert": "1",
0750 "SampleAfterValue": "2000000",
0751 "UMask": "0x1f"
0752 },
0753 {
0754 "BriefDescription": "Uops executed on port 0",
0755 "Counter": "0,1,2,3",
0756 "EventCode": "0xB1",
0757 "EventName": "UOPS_EXECUTED.PORT0",
0758 "SampleAfterValue": "2000000",
0759 "UMask": "0x1"
0760 },
0761 {
0762 "BriefDescription": "Uops issued on ports 0, 1 or 5",
0763 "Counter": "0,1,2,3",
0764 "EventCode": "0xB1",
0765 "EventName": "UOPS_EXECUTED.PORT015",
0766 "SampleAfterValue": "2000000",
0767 "UMask": "0x40"
0768 },
0769 {
0770 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
0771 "Counter": "0,1,2,3",
0772 "CounterMask": "1",
0773 "EventCode": "0xB1",
0774 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
0775 "Invert": "1",
0776 "SampleAfterValue": "2000000",
0777 "UMask": "0x40"
0778 },
0779 {
0780 "BriefDescription": "Uops executed on port 1",
0781 "Counter": "0,1,2,3",
0782 "EventCode": "0xB1",
0783 "EventName": "UOPS_EXECUTED.PORT1",
0784 "SampleAfterValue": "2000000",
0785 "UMask": "0x2"
0786 },
0787 {
0788 "AnyThread": "1",
0789 "BriefDescription": "Uops issued on ports 2, 3 or 4",
0790 "Counter": "0,1,2,3",
0791 "EventCode": "0xB1",
0792 "EventName": "UOPS_EXECUTED.PORT234_CORE",
0793 "SampleAfterValue": "2000000",
0794 "UMask": "0x80"
0795 },
0796 {
0797 "AnyThread": "1",
0798 "BriefDescription": "Uops executed on port 2 (core count)",
0799 "Counter": "0,1,2,3",
0800 "EventCode": "0xB1",
0801 "EventName": "UOPS_EXECUTED.PORT2_CORE",
0802 "SampleAfterValue": "2000000",
0803 "UMask": "0x4"
0804 },
0805 {
0806 "AnyThread": "1",
0807 "BriefDescription": "Uops executed on port 3 (core count)",
0808 "Counter": "0,1,2,3",
0809 "EventCode": "0xB1",
0810 "EventName": "UOPS_EXECUTED.PORT3_CORE",
0811 "SampleAfterValue": "2000000",
0812 "UMask": "0x8"
0813 },
0814 {
0815 "AnyThread": "1",
0816 "BriefDescription": "Uops executed on port 4 (core count)",
0817 "Counter": "0,1,2,3",
0818 "EventCode": "0xB1",
0819 "EventName": "UOPS_EXECUTED.PORT4_CORE",
0820 "SampleAfterValue": "2000000",
0821 "UMask": "0x10"
0822 },
0823 {
0824 "BriefDescription": "Uops executed on port 5",
0825 "Counter": "0,1,2,3",
0826 "EventCode": "0xB1",
0827 "EventName": "UOPS_EXECUTED.PORT5",
0828 "SampleAfterValue": "2000000",
0829 "UMask": "0x20"
0830 },
0831 {
0832 "BriefDescription": "Uops issued",
0833 "Counter": "0,1,2,3",
0834 "EventCode": "0xE",
0835 "EventName": "UOPS_ISSUED.ANY",
0836 "SampleAfterValue": "2000000",
0837 "UMask": "0x1"
0838 },
0839 {
0840 "AnyThread": "1",
0841 "BriefDescription": "Cycles no Uops were issued on any thread",
0842 "Counter": "0,1,2,3",
0843 "CounterMask": "1",
0844 "EventCode": "0xE",
0845 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
0846 "Invert": "1",
0847 "SampleAfterValue": "2000000",
0848 "UMask": "0x1"
0849 },
0850 {
0851 "AnyThread": "1",
0852 "BriefDescription": "Cycles Uops were issued on either thread",
0853 "Counter": "0,1,2,3",
0854 "CounterMask": "1",
0855 "EventCode": "0xE",
0856 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
0857 "SampleAfterValue": "2000000",
0858 "UMask": "0x1"
0859 },
0860 {
0861 "BriefDescription": "Fused Uops issued",
0862 "Counter": "0,1,2,3",
0863 "EventCode": "0xE",
0864 "EventName": "UOPS_ISSUED.FUSED",
0865 "SampleAfterValue": "2000000",
0866 "UMask": "0x2"
0867 },
0868 {
0869 "BriefDescription": "Cycles no Uops were issued",
0870 "Counter": "0,1,2,3",
0871 "CounterMask": "1",
0872 "EventCode": "0xE",
0873 "EventName": "UOPS_ISSUED.STALL_CYCLES",
0874 "Invert": "1",
0875 "SampleAfterValue": "2000000",
0876 "UMask": "0x1"
0877 },
0878 {
0879 "BriefDescription": "Cycles Uops are being retired",
0880 "Counter": "0,1,2,3",
0881 "CounterMask": "1",
0882 "EventCode": "0xC2",
0883 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
0884 "PEBS": "1",
0885 "SampleAfterValue": "2000000",
0886 "UMask": "0x1"
0887 },
0888 {
0889 "BriefDescription": "Uops retired (Precise Event)",
0890 "Counter": "0,1,2,3",
0891 "EventCode": "0xC2",
0892 "EventName": "UOPS_RETIRED.ANY",
0893 "PEBS": "1",
0894 "SampleAfterValue": "2000000",
0895 "UMask": "0x1"
0896 },
0897 {
0898 "BriefDescription": "Macro-fused Uops retired (Precise Event)",
0899 "Counter": "0,1,2,3",
0900 "EventCode": "0xC2",
0901 "EventName": "UOPS_RETIRED.MACRO_FUSED",
0902 "PEBS": "1",
0903 "SampleAfterValue": "2000000",
0904 "UMask": "0x4"
0905 },
0906 {
0907 "BriefDescription": "Retirement slots used (Precise Event)",
0908 "Counter": "0,1,2,3",
0909 "EventCode": "0xC2",
0910 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
0911 "PEBS": "1",
0912 "SampleAfterValue": "2000000",
0913 "UMask": "0x2"
0914 },
0915 {
0916 "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
0917 "Counter": "0,1,2,3",
0918 "CounterMask": "1",
0919 "EventCode": "0xC2",
0920 "EventName": "UOPS_RETIRED.STALL_CYCLES",
0921 "Invert": "1",
0922 "PEBS": "1",
0923 "SampleAfterValue": "2000000",
0924 "UMask": "0x1"
0925 },
0926 {
0927 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
0928 "Counter": "0,1,2,3",
0929 "CounterMask": "16",
0930 "EventCode": "0xC2",
0931 "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
0932 "Invert": "1",
0933 "PEBS": "1",
0934 "SampleAfterValue": "2000000",
0935 "UMask": "0x1"
0936 },
0937 {
0938 "BriefDescription": "Uop unfusions due to FP exceptions",
0939 "Counter": "0,1,2,3",
0940 "EventCode": "0xDB",
0941 "EventName": "UOP_UNFUSION",
0942 "SampleAfterValue": "2000000",
0943 "UMask": "0x1"
0944 }
0945 ]
