0001 [
0002 {
0003 "BriefDescription": "ES segment renames",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0xD5",
0006 "EventName": "ES_REG_RENAMES",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0x1"
0009 },
0010 {
0011 "BriefDescription": "I/O transactions",
0012 "Counter": "0,1,2,3",
0013 "EventCode": "0x6C",
0014 "EventName": "IO_TRANSACTIONS",
0015 "SampleAfterValue": "2000000",
0016 "UMask": "0x1"
0017 },
0018 {
0019 "BriefDescription": "L1I instruction fetch stall cycles",
0020 "Counter": "0,1,2,3",
0021 "EventCode": "0x80",
0022 "EventName": "L1I.CYCLES_STALLED",
0023 "SampleAfterValue": "2000000",
0024 "UMask": "0x4"
0025 },
0026 {
0027 "BriefDescription": "L1I instruction fetch hits",
0028 "Counter": "0,1,2,3",
0029 "EventCode": "0x80",
0030 "EventName": "L1I.HITS",
0031 "SampleAfterValue": "2000000",
0032 "UMask": "0x1"
0033 },
0034 {
0035 "BriefDescription": "L1I instruction fetch misses",
0036 "Counter": "0,1,2,3",
0037 "EventCode": "0x80",
0038 "EventName": "L1I.MISSES",
0039 "SampleAfterValue": "2000000",
0040 "UMask": "0x2"
0041 },
0042 {
0043 "BriefDescription": "L1I Instruction fetches",
0044 "Counter": "0,1,2,3",
0045 "EventCode": "0x80",
0046 "EventName": "L1I.READS",
0047 "SampleAfterValue": "2000000",
0048 "UMask": "0x3"
0049 },
0050 {
0051 "BriefDescription": "Large ITLB hit",
0052 "Counter": "0,1,2,3",
0053 "EventCode": "0x82",
0054 "EventName": "LARGE_ITLB.HIT",
0055 "SampleAfterValue": "200000",
0056 "UMask": "0x1"
0057 },
0058 {
0059 "BriefDescription": "All loads dispatched",
0060 "Counter": "0,1,2,3",
0061 "EventCode": "0x13",
0062 "EventName": "LOAD_DISPATCH.ANY",
0063 "SampleAfterValue": "2000000",
0064 "UMask": "0x7"
0065 },
0066 {
0067 "BriefDescription": "Loads dispatched from the MOB",
0068 "Counter": "0,1,2,3",
0069 "EventCode": "0x13",
0070 "EventName": "LOAD_DISPATCH.MOB",
0071 "SampleAfterValue": "2000000",
0072 "UMask": "0x4"
0073 },
0074 {
0075 "BriefDescription": "Loads dispatched that bypass the MOB",
0076 "Counter": "0,1,2,3",
0077 "EventCode": "0x13",
0078 "EventName": "LOAD_DISPATCH.RS",
0079 "SampleAfterValue": "2000000",
0080 "UMask": "0x1"
0081 },
0082 {
0083 "BriefDescription": "Loads dispatched from stage 305",
0084 "Counter": "0,1,2,3",
0085 "EventCode": "0x13",
0086 "EventName": "LOAD_DISPATCH.RS_DELAYED",
0087 "SampleAfterValue": "2000000",
0088 "UMask": "0x2"
0089 },
0090 {
0091 "BriefDescription": "False dependencies due to partial address aliasing",
0092 "Counter": "0,1,2,3",
0093 "EventCode": "0x7",
0094 "EventName": "PARTIAL_ADDRESS_ALIAS",
0095 "SampleAfterValue": "200000",
0096 "UMask": "0x1"
0097 },
0098 {
0099 "BriefDescription": "All Store buffer stall cycles",
0100 "Counter": "0,1,2,3",
0101 "EventCode": "0x4",
0102 "EventName": "SB_DRAIN.ANY",
0103 "SampleAfterValue": "200000",
0104 "UMask": "0x7"
0105 },
0106 {
0107 "BriefDescription": "Segment rename stall cycles",
0108 "Counter": "0,1,2,3",
0109 "EventCode": "0xD4",
0110 "EventName": "SEG_RENAME_STALLS",
0111 "SampleAfterValue": "2000000",
0112 "UMask": "0x1"
0113 },
0114 {
0115 "BriefDescription": "Thread responded HIT to snoop",
0116 "Counter": "0,1,2,3",
0117 "EventCode": "0xB8",
0118 "EventName": "SNOOP_RESPONSE.HIT",
0119 "SampleAfterValue": "100000",
0120 "UMask": "0x1"
0121 },
0122 {
0123 "BriefDescription": "Thread responded HITE to snoop",
0124 "Counter": "0,1,2,3",
0125 "EventCode": "0xB8",
0126 "EventName": "SNOOP_RESPONSE.HITE",
0127 "SampleAfterValue": "100000",
0128 "UMask": "0x2"
0129 },
0130 {
0131 "BriefDescription": "Thread responded HITM to snoop",
0132 "Counter": "0,1,2,3",
0133 "EventCode": "0xB8",
0134 "EventName": "SNOOP_RESPONSE.HITM",
0135 "SampleAfterValue": "100000",
0136 "UMask": "0x4"
0137 },
0138 {
0139 "BriefDescription": "Super Queue full stall cycles",
0140 "Counter": "0,1,2,3",
0141 "EventCode": "0xF6",
0142 "EventName": "SQ_FULL_STALL_CYCLES",
0143 "SampleAfterValue": "2000000",
0144 "UMask": "0x1"
0145 }
0146 ]
