0001 [
0002 {
0003 "BriefDescription": "Cycles L1D locked",
0004 "Counter": "0,1",
0005 "EventCode": "0x63",
0006 "EventName": "CACHE_LOCK_CYCLES.L1D",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0x2"
0009 },
0010 {
0011 "BriefDescription": "Cycles L1D and L2 locked",
0012 "Counter": "0,1",
0013 "EventCode": "0x63",
0014 "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
0015 "SampleAfterValue": "2000000",
0016 "UMask": "0x1"
0017 },
0018 {
0019 "BriefDescription": "L1D cache lines replaced in M state",
0020 "Counter": "0,1",
0021 "EventCode": "0x51",
0022 "EventName": "L1D.M_EVICT",
0023 "SampleAfterValue": "2000000",
0024 "UMask": "0x4"
0025 },
0026 {
0027 "BriefDescription": "L1D cache lines allocated in the M state",
0028 "Counter": "0,1",
0029 "EventCode": "0x51",
0030 "EventName": "L1D.M_REPL",
0031 "SampleAfterValue": "2000000",
0032 "UMask": "0x2"
0033 },
0034 {
0035 "BriefDescription": "L1D snoop eviction of cache lines in M state",
0036 "Counter": "0,1",
0037 "EventCode": "0x51",
0038 "EventName": "L1D.M_SNOOP_EVICT",
0039 "SampleAfterValue": "2000000",
0040 "UMask": "0x8"
0041 },
0042 {
0043 "BriefDescription": "L1 data cache lines allocated",
0044 "Counter": "0,1",
0045 "EventCode": "0x51",
0046 "EventName": "L1D.REPL",
0047 "SampleAfterValue": "2000000",
0048 "UMask": "0x1"
0049 },
0050 {
0051 "BriefDescription": "All references to the L1 data cache",
0052 "Counter": "0,1",
0053 "EventCode": "0x43",
0054 "EventName": "L1D_ALL_REF.ANY",
0055 "SampleAfterValue": "2000000",
0056 "UMask": "0x1"
0057 },
0058 {
0059 "BriefDescription": "L1 data cacheable reads and writes",
0060 "Counter": "0,1",
0061 "EventCode": "0x43",
0062 "EventName": "L1D_ALL_REF.CACHEABLE",
0063 "SampleAfterValue": "2000000",
0064 "UMask": "0x2"
0065 },
0066 {
0067 "BriefDescription": "L1 data cache read in E state",
0068 "Counter": "0,1",
0069 "EventCode": "0x40",
0070 "EventName": "L1D_CACHE_LD.E_STATE",
0071 "SampleAfterValue": "2000000",
0072 "UMask": "0x4"
0073 },
0074 {
0075 "BriefDescription": "L1 data cache read in I state (misses)",
0076 "Counter": "0,1",
0077 "EventCode": "0x40",
0078 "EventName": "L1D_CACHE_LD.I_STATE",
0079 "SampleAfterValue": "2000000",
0080 "UMask": "0x1"
0081 },
0082 {
0083 "BriefDescription": "L1 data cache reads",
0084 "Counter": "0,1",
0085 "EventCode": "0x40",
0086 "EventName": "L1D_CACHE_LD.MESI",
0087 "SampleAfterValue": "2000000",
0088 "UMask": "0xf"
0089 },
0090 {
0091 "BriefDescription": "L1 data cache read in M state",
0092 "Counter": "0,1",
0093 "EventCode": "0x40",
0094 "EventName": "L1D_CACHE_LD.M_STATE",
0095 "SampleAfterValue": "2000000",
0096 "UMask": "0x8"
0097 },
0098 {
0099 "BriefDescription": "L1 data cache read in S state",
0100 "Counter": "0,1",
0101 "EventCode": "0x40",
0102 "EventName": "L1D_CACHE_LD.S_STATE",
0103 "SampleAfterValue": "2000000",
0104 "UMask": "0x2"
0105 },
0106 {
0107 "BriefDescription": "L1 data cache load locks in E state",
0108 "Counter": "0,1",
0109 "EventCode": "0x42",
0110 "EventName": "L1D_CACHE_LOCK.E_STATE",
0111 "SampleAfterValue": "2000000",
0112 "UMask": "0x4"
0113 },
0114 {
0115 "BriefDescription": "L1 data cache load lock hits",
0116 "Counter": "0,1",
0117 "EventCode": "0x42",
0118 "EventName": "L1D_CACHE_LOCK.HIT",
0119 "SampleAfterValue": "2000000",
0120 "UMask": "0x1"
0121 },
0122 {
0123 "BriefDescription": "L1 data cache load locks in M state",
0124 "Counter": "0,1",
0125 "EventCode": "0x42",
0126 "EventName": "L1D_CACHE_LOCK.M_STATE",
0127 "SampleAfterValue": "2000000",
0128 "UMask": "0x8"
0129 },
0130 {
0131 "BriefDescription": "L1 data cache load locks in S state",
0132 "Counter": "0,1",
0133 "EventCode": "0x42",
0134 "EventName": "L1D_CACHE_LOCK.S_STATE",
0135 "SampleAfterValue": "2000000",
0136 "UMask": "0x2"
0137 },
0138 {
0139 "BriefDescription": "L1D load lock accepted in fill buffer",
0140 "Counter": "0,1",
0141 "EventCode": "0x53",
0142 "EventName": "L1D_CACHE_LOCK_FB_HIT",
0143 "SampleAfterValue": "2000000",
0144 "UMask": "0x1"
0145 },
0146 {
0147 "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
0148 "Counter": "0,1",
0149 "EventCode": "0x52",
0150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
0151 "SampleAfterValue": "2000000",
0152 "UMask": "0x1"
0153 },
0154 {
0155 "BriefDescription": "L1 data cache stores in E state",
0156 "Counter": "0,1",
0157 "EventCode": "0x41",
0158 "EventName": "L1D_CACHE_ST.E_STATE",
0159 "SampleAfterValue": "2000000",
0160 "UMask": "0x4"
0161 },
0162 {
0163 "BriefDescription": "L1 data cache stores in M state",
0164 "Counter": "0,1",
0165 "EventCode": "0x41",
0166 "EventName": "L1D_CACHE_ST.M_STATE",
0167 "SampleAfterValue": "2000000",
0168 "UMask": "0x8"
0169 },
0170 {
0171 "BriefDescription": "L1 data cache stores in S state",
0172 "Counter": "0,1",
0173 "EventCode": "0x41",
0174 "EventName": "L1D_CACHE_ST.S_STATE",
0175 "SampleAfterValue": "2000000",
0176 "UMask": "0x2"
0177 },
0178 {
0179 "BriefDescription": "L1D hardware prefetch misses",
0180 "Counter": "0,1",
0181 "EventCode": "0x4E",
0182 "EventName": "L1D_PREFETCH.MISS",
0183 "SampleAfterValue": "200000",
0184 "UMask": "0x2"
0185 },
0186 {
0187 "BriefDescription": "L1D hardware prefetch requests",
0188 "Counter": "0,1",
0189 "EventCode": "0x4E",
0190 "EventName": "L1D_PREFETCH.REQUESTS",
0191 "SampleAfterValue": "200000",
0192 "UMask": "0x1"
0193 },
0194 {
0195 "BriefDescription": "L1D hardware prefetch requests triggered",
0196 "Counter": "0,1",
0197 "EventCode": "0x4E",
0198 "EventName": "L1D_PREFETCH.TRIGGERS",
0199 "SampleAfterValue": "200000",
0200 "UMask": "0x4"
0201 },
0202 {
0203 "BriefDescription": "L1 writebacks to L2 in E state",
0204 "Counter": "0,1,2,3",
0205 "EventCode": "0x28",
0206 "EventName": "L1D_WB_L2.E_STATE",
0207 "SampleAfterValue": "100000",
0208 "UMask": "0x4"
0209 },
0210 {
0211 "BriefDescription": "L1 writebacks to L2 in I state (misses)",
0212 "Counter": "0,1,2,3",
0213 "EventCode": "0x28",
0214 "EventName": "L1D_WB_L2.I_STATE",
0215 "SampleAfterValue": "100000",
0216 "UMask": "0x1"
0217 },
0218 {
0219 "BriefDescription": "All L1 writebacks to L2",
0220 "Counter": "0,1,2,3",
0221 "EventCode": "0x28",
0222 "EventName": "L1D_WB_L2.MESI",
0223 "SampleAfterValue": "100000",
0224 "UMask": "0xf"
0225 },
0226 {
0227 "BriefDescription": "L1 writebacks to L2 in M state",
0228 "Counter": "0,1,2,3",
0229 "EventCode": "0x28",
0230 "EventName": "L1D_WB_L2.M_STATE",
0231 "SampleAfterValue": "100000",
0232 "UMask": "0x8"
0233 },
0234 {
0235 "BriefDescription": "L1 writebacks to L2 in S state",
0236 "Counter": "0,1,2,3",
0237 "EventCode": "0x28",
0238 "EventName": "L1D_WB_L2.S_STATE",
0239 "SampleAfterValue": "100000",
0240 "UMask": "0x2"
0241 },
0242 {
0243 "BriefDescription": "All L2 data requests",
0244 "Counter": "0,1,2,3",
0245 "EventCode": "0x26",
0246 "EventName": "L2_DATA_RQSTS.ANY",
0247 "SampleAfterValue": "200000",
0248 "UMask": "0xff"
0249 },
0250 {
0251 "BriefDescription": "L2 data demand loads in E state",
0252 "Counter": "0,1,2,3",
0253 "EventCode": "0x26",
0254 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
0255 "SampleAfterValue": "200000",
0256 "UMask": "0x4"
0257 },
0258 {
0259 "BriefDescription": "L2 data demand loads in I state (misses)",
0260 "Counter": "0,1,2,3",
0261 "EventCode": "0x26",
0262 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
0263 "SampleAfterValue": "200000",
0264 "UMask": "0x1"
0265 },
0266 {
0267 "BriefDescription": "L2 data demand requests",
0268 "Counter": "0,1,2,3",
0269 "EventCode": "0x26",
0270 "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
0271 "SampleAfterValue": "200000",
0272 "UMask": "0xf"
0273 },
0274 {
0275 "BriefDescription": "L2 data demand loads in M state",
0276 "Counter": "0,1,2,3",
0277 "EventCode": "0x26",
0278 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
0279 "SampleAfterValue": "200000",
0280 "UMask": "0x8"
0281 },
0282 {
0283 "BriefDescription": "L2 data demand loads in S state",
0284 "Counter": "0,1,2,3",
0285 "EventCode": "0x26",
0286 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
0287 "SampleAfterValue": "200000",
0288 "UMask": "0x2"
0289 },
0290 {
0291 "BriefDescription": "L2 data prefetches in E state",
0292 "Counter": "0,1,2,3",
0293 "EventCode": "0x26",
0294 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
0295 "SampleAfterValue": "200000",
0296 "UMask": "0x40"
0297 },
0298 {
0299 "BriefDescription": "L2 data prefetches in the I state (misses)",
0300 "Counter": "0,1,2,3",
0301 "EventCode": "0x26",
0302 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
0303 "SampleAfterValue": "200000",
0304 "UMask": "0x10"
0305 },
0306 {
0307 "BriefDescription": "All L2 data prefetches",
0308 "Counter": "0,1,2,3",
0309 "EventCode": "0x26",
0310 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
0311 "SampleAfterValue": "200000",
0312 "UMask": "0xf0"
0313 },
0314 {
0315 "BriefDescription": "L2 data prefetches in M state",
0316 "Counter": "0,1,2,3",
0317 "EventCode": "0x26",
0318 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
0319 "SampleAfterValue": "200000",
0320 "UMask": "0x80"
0321 },
0322 {
0323 "BriefDescription": "L2 data prefetches in the S state",
0324 "Counter": "0,1,2,3",
0325 "EventCode": "0x26",
0326 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
0327 "SampleAfterValue": "200000",
0328 "UMask": "0x20"
0329 },
0330 {
0331 "BriefDescription": "L2 lines alloacated",
0332 "Counter": "0,1,2,3",
0333 "EventCode": "0xF1",
0334 "EventName": "L2_LINES_IN.ANY",
0335 "SampleAfterValue": "100000",
0336 "UMask": "0x7"
0337 },
0338 {
0339 "BriefDescription": "L2 lines allocated in the E state",
0340 "Counter": "0,1,2,3",
0341 "EventCode": "0xF1",
0342 "EventName": "L2_LINES_IN.E_STATE",
0343 "SampleAfterValue": "100000",
0344 "UMask": "0x4"
0345 },
0346 {
0347 "BriefDescription": "L2 lines allocated in the S state",
0348 "Counter": "0,1,2,3",
0349 "EventCode": "0xF1",
0350 "EventName": "L2_LINES_IN.S_STATE",
0351 "SampleAfterValue": "100000",
0352 "UMask": "0x2"
0353 },
0354 {
0355 "BriefDescription": "L2 lines evicted",
0356 "Counter": "0,1,2,3",
0357 "EventCode": "0xF2",
0358 "EventName": "L2_LINES_OUT.ANY",
0359 "SampleAfterValue": "100000",
0360 "UMask": "0xf"
0361 },
0362 {
0363 "BriefDescription": "L2 lines evicted by a demand request",
0364 "Counter": "0,1,2,3",
0365 "EventCode": "0xF2",
0366 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
0367 "SampleAfterValue": "100000",
0368 "UMask": "0x1"
0369 },
0370 {
0371 "BriefDescription": "L2 modified lines evicted by a demand request",
0372 "Counter": "0,1,2,3",
0373 "EventCode": "0xF2",
0374 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
0375 "SampleAfterValue": "100000",
0376 "UMask": "0x2"
0377 },
0378 {
0379 "BriefDescription": "L2 lines evicted by a prefetch request",
0380 "Counter": "0,1,2,3",
0381 "EventCode": "0xF2",
0382 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
0383 "SampleAfterValue": "100000",
0384 "UMask": "0x4"
0385 },
0386 {
0387 "BriefDescription": "L2 modified lines evicted by a prefetch request",
0388 "Counter": "0,1,2,3",
0389 "EventCode": "0xF2",
0390 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
0391 "SampleAfterValue": "100000",
0392 "UMask": "0x8"
0393 },
0394 {
0395 "BriefDescription": "L2 instruction fetches",
0396 "Counter": "0,1,2,3",
0397 "EventCode": "0x24",
0398 "EventName": "L2_RQSTS.IFETCHES",
0399 "SampleAfterValue": "200000",
0400 "UMask": "0x30"
0401 },
0402 {
0403 "BriefDescription": "L2 instruction fetch hits",
0404 "Counter": "0,1,2,3",
0405 "EventCode": "0x24",
0406 "EventName": "L2_RQSTS.IFETCH_HIT",
0407 "SampleAfterValue": "200000",
0408 "UMask": "0x10"
0409 },
0410 {
0411 "BriefDescription": "L2 instruction fetch misses",
0412 "Counter": "0,1,2,3",
0413 "EventCode": "0x24",
0414 "EventName": "L2_RQSTS.IFETCH_MISS",
0415 "SampleAfterValue": "200000",
0416 "UMask": "0x20"
0417 },
0418 {
0419 "BriefDescription": "L2 load hits",
0420 "Counter": "0,1,2,3",
0421 "EventCode": "0x24",
0422 "EventName": "L2_RQSTS.LD_HIT",
0423 "SampleAfterValue": "200000",
0424 "UMask": "0x1"
0425 },
0426 {
0427 "BriefDescription": "L2 load misses",
0428 "Counter": "0,1,2,3",
0429 "EventCode": "0x24",
0430 "EventName": "L2_RQSTS.LD_MISS",
0431 "SampleAfterValue": "200000",
0432 "UMask": "0x2"
0433 },
0434 {
0435 "BriefDescription": "L2 requests",
0436 "Counter": "0,1,2,3",
0437 "EventCode": "0x24",
0438 "EventName": "L2_RQSTS.LOADS",
0439 "SampleAfterValue": "200000",
0440 "UMask": "0x3"
0441 },
0442 {
0443 "BriefDescription": "All L2 misses",
0444 "Counter": "0,1,2,3",
0445 "EventCode": "0x24",
0446 "EventName": "L2_RQSTS.MISS",
0447 "SampleAfterValue": "200000",
0448 "UMask": "0xaa"
0449 },
0450 {
0451 "BriefDescription": "All L2 prefetches",
0452 "Counter": "0,1,2,3",
0453 "EventCode": "0x24",
0454 "EventName": "L2_RQSTS.PREFETCHES",
0455 "SampleAfterValue": "200000",
0456 "UMask": "0xc0"
0457 },
0458 {
0459 "BriefDescription": "L2 prefetch hits",
0460 "Counter": "0,1,2,3",
0461 "EventCode": "0x24",
0462 "EventName": "L2_RQSTS.PREFETCH_HIT",
0463 "SampleAfterValue": "200000",
0464 "UMask": "0x40"
0465 },
0466 {
0467 "BriefDescription": "L2 prefetch misses",
0468 "Counter": "0,1,2,3",
0469 "EventCode": "0x24",
0470 "EventName": "L2_RQSTS.PREFETCH_MISS",
0471 "SampleAfterValue": "200000",
0472 "UMask": "0x80"
0473 },
0474 {
0475 "BriefDescription": "All L2 requests",
0476 "Counter": "0,1,2,3",
0477 "EventCode": "0x24",
0478 "EventName": "L2_RQSTS.REFERENCES",
0479 "SampleAfterValue": "200000",
0480 "UMask": "0xff"
0481 },
0482 {
0483 "BriefDescription": "L2 RFO requests",
0484 "Counter": "0,1,2,3",
0485 "EventCode": "0x24",
0486 "EventName": "L2_RQSTS.RFOS",
0487 "SampleAfterValue": "200000",
0488 "UMask": "0xc"
0489 },
0490 {
0491 "BriefDescription": "L2 RFO hits",
0492 "Counter": "0,1,2,3",
0493 "EventCode": "0x24",
0494 "EventName": "L2_RQSTS.RFO_HIT",
0495 "SampleAfterValue": "200000",
0496 "UMask": "0x4"
0497 },
0498 {
0499 "BriefDescription": "L2 RFO misses",
0500 "Counter": "0,1,2,3",
0501 "EventCode": "0x24",
0502 "EventName": "L2_RQSTS.RFO_MISS",
0503 "SampleAfterValue": "200000",
0504 "UMask": "0x8"
0505 },
0506 {
0507 "BriefDescription": "All L2 transactions",
0508 "Counter": "0,1,2,3",
0509 "EventCode": "0xF0",
0510 "EventName": "L2_TRANSACTIONS.ANY",
0511 "SampleAfterValue": "200000",
0512 "UMask": "0x80"
0513 },
0514 {
0515 "BriefDescription": "L2 fill transactions",
0516 "Counter": "0,1,2,3",
0517 "EventCode": "0xF0",
0518 "EventName": "L2_TRANSACTIONS.FILL",
0519 "SampleAfterValue": "200000",
0520 "UMask": "0x20"
0521 },
0522 {
0523 "BriefDescription": "L2 instruction fetch transactions",
0524 "Counter": "0,1,2,3",
0525 "EventCode": "0xF0",
0526 "EventName": "L2_TRANSACTIONS.IFETCH",
0527 "SampleAfterValue": "200000",
0528 "UMask": "0x4"
0529 },
0530 {
0531 "BriefDescription": "L1D writeback to L2 transactions",
0532 "Counter": "0,1,2,3",
0533 "EventCode": "0xF0",
0534 "EventName": "L2_TRANSACTIONS.L1D_WB",
0535 "SampleAfterValue": "200000",
0536 "UMask": "0x10"
0537 },
0538 {
0539 "BriefDescription": "L2 Load transactions",
0540 "Counter": "0,1,2,3",
0541 "EventCode": "0xF0",
0542 "EventName": "L2_TRANSACTIONS.LOAD",
0543 "SampleAfterValue": "200000",
0544 "UMask": "0x1"
0545 },
0546 {
0547 "BriefDescription": "L2 prefetch transactions",
0548 "Counter": "0,1,2,3",
0549 "EventCode": "0xF0",
0550 "EventName": "L2_TRANSACTIONS.PREFETCH",
0551 "SampleAfterValue": "200000",
0552 "UMask": "0x8"
0553 },
0554 {
0555 "BriefDescription": "L2 RFO transactions",
0556 "Counter": "0,1,2,3",
0557 "EventCode": "0xF0",
0558 "EventName": "L2_TRANSACTIONS.RFO",
0559 "SampleAfterValue": "200000",
0560 "UMask": "0x2"
0561 },
0562 {
0563 "BriefDescription": "L2 writeback to LLC transactions",
0564 "Counter": "0,1,2,3",
0565 "EventCode": "0xF0",
0566 "EventName": "L2_TRANSACTIONS.WB",
0567 "SampleAfterValue": "200000",
0568 "UMask": "0x40"
0569 },
0570 {
0571 "BriefDescription": "L2 demand lock RFOs in E state",
0572 "Counter": "0,1,2,3",
0573 "EventCode": "0x27",
0574 "EventName": "L2_WRITE.LOCK.E_STATE",
0575 "SampleAfterValue": "100000",
0576 "UMask": "0x40"
0577 },
0578 {
0579 "BriefDescription": "All demand L2 lock RFOs that hit the cache",
0580 "Counter": "0,1,2,3",
0581 "EventCode": "0x27",
0582 "EventName": "L2_WRITE.LOCK.HIT",
0583 "SampleAfterValue": "100000",
0584 "UMask": "0xe0"
0585 },
0586 {
0587 "BriefDescription": "L2 demand lock RFOs in I state (misses)",
0588 "Counter": "0,1,2,3",
0589 "EventCode": "0x27",
0590 "EventName": "L2_WRITE.LOCK.I_STATE",
0591 "SampleAfterValue": "100000",
0592 "UMask": "0x10"
0593 },
0594 {
0595 "BriefDescription": "All demand L2 lock RFOs",
0596 "Counter": "0,1,2,3",
0597 "EventCode": "0x27",
0598 "EventName": "L2_WRITE.LOCK.MESI",
0599 "SampleAfterValue": "100000",
0600 "UMask": "0xf0"
0601 },
0602 {
0603 "BriefDescription": "L2 demand lock RFOs in M state",
0604 "Counter": "0,1,2,3",
0605 "EventCode": "0x27",
0606 "EventName": "L2_WRITE.LOCK.M_STATE",
0607 "SampleAfterValue": "100000",
0608 "UMask": "0x80"
0609 },
0610 {
0611 "BriefDescription": "L2 demand lock RFOs in S state",
0612 "Counter": "0,1,2,3",
0613 "EventCode": "0x27",
0614 "EventName": "L2_WRITE.LOCK.S_STATE",
0615 "SampleAfterValue": "100000",
0616 "UMask": "0x20"
0617 },
0618 {
0619 "BriefDescription": "All L2 demand store RFOs that hit the cache",
0620 "Counter": "0,1,2,3",
0621 "EventCode": "0x27",
0622 "EventName": "L2_WRITE.RFO.HIT",
0623 "SampleAfterValue": "100000",
0624 "UMask": "0xe"
0625 },
0626 {
0627 "BriefDescription": "L2 demand store RFOs in I state (misses)",
0628 "Counter": "0,1,2,3",
0629 "EventCode": "0x27",
0630 "EventName": "L2_WRITE.RFO.I_STATE",
0631 "SampleAfterValue": "100000",
0632 "UMask": "0x1"
0633 },
0634 {
0635 "BriefDescription": "All L2 demand store RFOs",
0636 "Counter": "0,1,2,3",
0637 "EventCode": "0x27",
0638 "EventName": "L2_WRITE.RFO.MESI",
0639 "SampleAfterValue": "100000",
0640 "UMask": "0xf"
0641 },
0642 {
0643 "BriefDescription": "L2 demand store RFOs in M state",
0644 "Counter": "0,1,2,3",
0645 "EventCode": "0x27",
0646 "EventName": "L2_WRITE.RFO.M_STATE",
0647 "SampleAfterValue": "100000",
0648 "UMask": "0x8"
0649 },
0650 {
0651 "BriefDescription": "L2 demand store RFOs in S state",
0652 "Counter": "0,1,2,3",
0653 "EventCode": "0x27",
0654 "EventName": "L2_WRITE.RFO.S_STATE",
0655 "SampleAfterValue": "100000",
0656 "UMask": "0x2"
0657 },
0658 {
0659 "BriefDescription": "Longest latency cache miss",
0660 "Counter": "0,1,2,3",
0661 "EventCode": "0x2E",
0662 "EventName": "LONGEST_LAT_CACHE.MISS",
0663 "SampleAfterValue": "100000",
0664 "UMask": "0x41"
0665 },
0666 {
0667 "BriefDescription": "Longest latency cache reference",
0668 "Counter": "0,1,2,3",
0669 "EventCode": "0x2E",
0670 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0671 "SampleAfterValue": "200000",
0672 "UMask": "0x4f"
0673 },
0674 {
0675 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
0676 "Counter": "3",
0677 "EventCode": "0xB",
0678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
0679 "MSRIndex": "0x3F6",
0680 "MSRValue": "0x0",
0681 "PEBS": "2",
0682 "SampleAfterValue": "2000000",
0683 "UMask": "0x10"
0684 },
0685 {
0686 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
0687 "Counter": "3",
0688 "EventCode": "0xB",
0689 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
0690 "MSRIndex": "0x3F6",
0691 "MSRValue": "0x400",
0692 "PEBS": "2",
0693 "SampleAfterValue": "100",
0694 "UMask": "0x10"
0695 },
0696 {
0697 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
0698 "Counter": "3",
0699 "EventCode": "0xB",
0700 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
0701 "MSRIndex": "0x3F6",
0702 "MSRValue": "0x80",
0703 "PEBS": "2",
0704 "SampleAfterValue": "1000",
0705 "UMask": "0x10"
0706 },
0707 {
0708 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
0709 "Counter": "3",
0710 "EventCode": "0xB",
0711 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
0712 "MSRIndex": "0x3F6",
0713 "MSRValue": "0x10",
0714 "PEBS": "2",
0715 "SampleAfterValue": "10000",
0716 "UMask": "0x10"
0717 },
0718 {
0719 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
0720 "Counter": "3",
0721 "EventCode": "0xB",
0722 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
0723 "MSRIndex": "0x3F6",
0724 "MSRValue": "0x4000",
0725 "PEBS": "2",
0726 "SampleAfterValue": "5",
0727 "UMask": "0x10"
0728 },
0729 {
0730 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
0731 "Counter": "3",
0732 "EventCode": "0xB",
0733 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
0734 "MSRIndex": "0x3F6",
0735 "MSRValue": "0x800",
0736 "PEBS": "2",
0737 "SampleAfterValue": "50",
0738 "UMask": "0x10"
0739 },
0740 {
0741 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
0742 "Counter": "3",
0743 "EventCode": "0xB",
0744 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
0745 "MSRIndex": "0x3F6",
0746 "MSRValue": "0x100",
0747 "PEBS": "2",
0748 "SampleAfterValue": "500",
0749 "UMask": "0x10"
0750 },
0751 {
0752 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
0753 "Counter": "3",
0754 "EventCode": "0xB",
0755 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
0756 "MSRIndex": "0x3F6",
0757 "MSRValue": "0x20",
0758 "PEBS": "2",
0759 "SampleAfterValue": "5000",
0760 "UMask": "0x10"
0761 },
0762 {
0763 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
0764 "Counter": "3",
0765 "EventCode": "0xB",
0766 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
0767 "MSRIndex": "0x3F6",
0768 "MSRValue": "0x8000",
0769 "PEBS": "2",
0770 "SampleAfterValue": "3",
0771 "UMask": "0x10"
0772 },
0773 {
0774 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
0775 "Counter": "3",
0776 "EventCode": "0xB",
0777 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
0778 "MSRIndex": "0x3F6",
0779 "MSRValue": "0x4",
0780 "PEBS": "2",
0781 "SampleAfterValue": "50000",
0782 "UMask": "0x10"
0783 },
0784 {
0785 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
0786 "Counter": "3",
0787 "EventCode": "0xB",
0788 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
0789 "MSRIndex": "0x3F6",
0790 "MSRValue": "0x1000",
0791 "PEBS": "2",
0792 "SampleAfterValue": "20",
0793 "UMask": "0x10"
0794 },
0795 {
0796 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
0797 "Counter": "3",
0798 "EventCode": "0xB",
0799 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
0800 "MSRIndex": "0x3F6",
0801 "MSRValue": "0x200",
0802 "PEBS": "2",
0803 "SampleAfterValue": "200",
0804 "UMask": "0x10"
0805 },
0806 {
0807 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
0808 "Counter": "3",
0809 "EventCode": "0xB",
0810 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
0811 "MSRIndex": "0x3F6",
0812 "MSRValue": "0x40",
0813 "PEBS": "2",
0814 "SampleAfterValue": "2000",
0815 "UMask": "0x10"
0816 },
0817 {
0818 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
0819 "Counter": "3",
0820 "EventCode": "0xB",
0821 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
0822 "MSRIndex": "0x3F6",
0823 "MSRValue": "0x8",
0824 "PEBS": "2",
0825 "SampleAfterValue": "20000",
0826 "UMask": "0x10"
0827 },
0828 {
0829 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
0830 "Counter": "3",
0831 "EventCode": "0xB",
0832 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
0833 "MSRIndex": "0x3F6",
0834 "MSRValue": "0x2000",
0835 "PEBS": "2",
0836 "SampleAfterValue": "10",
0837 "UMask": "0x10"
0838 },
0839 {
0840 "BriefDescription": "Instructions retired which contains a load (Precise Event)",
0841 "Counter": "0,1,2,3",
0842 "EventCode": "0xB",
0843 "EventName": "MEM_INST_RETIRED.LOADS",
0844 "PEBS": "1",
0845 "SampleAfterValue": "2000000",
0846 "UMask": "0x1"
0847 },
0848 {
0849 "BriefDescription": "Instructions retired which contains a store (Precise Event)",
0850 "Counter": "0,1,2,3",
0851 "EventCode": "0xB",
0852 "EventName": "MEM_INST_RETIRED.STORES",
0853 "PEBS": "1",
0854 "SampleAfterValue": "2000000",
0855 "UMask": "0x2"
0856 },
0857 {
0858 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
0859 "Counter": "0,1,2,3",
0860 "EventCode": "0xCB",
0861 "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
0862 "PEBS": "1",
0863 "SampleAfterValue": "200000",
0864 "UMask": "0x40"
0865 },
0866 {
0867 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
0868 "Counter": "0,1,2,3",
0869 "EventCode": "0xCB",
0870 "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
0871 "PEBS": "1",
0872 "SampleAfterValue": "2000000",
0873 "UMask": "0x1"
0874 },
0875 {
0876 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
0877 "Counter": "0,1,2,3",
0878 "EventCode": "0xCB",
0879 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
0880 "PEBS": "1",
0881 "SampleAfterValue": "200000",
0882 "UMask": "0x2"
0883 },
0884 {
0885 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
0886 "Counter": "0,1,2,3",
0887 "EventCode": "0xCB",
0888 "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
0889 "PEBS": "1",
0890 "SampleAfterValue": "10000",
0891 "UMask": "0x10"
0892 },
0893 {
0894 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
0895 "Counter": "0,1,2,3",
0896 "EventCode": "0xCB",
0897 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
0898 "PEBS": "1",
0899 "SampleAfterValue": "40000",
0900 "UMask": "0x4"
0901 },
0902 {
0903 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
0904 "Counter": "0,1,2,3",
0905 "EventCode": "0xCB",
0906 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
0907 "PEBS": "1",
0908 "SampleAfterValue": "40000",
0909 "UMask": "0x8"
0910 },
0911 {
0912 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
0913 "Counter": "0,1,2,3",
0914 "EventCode": "0xF",
0915 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
0916 "PEBS": "1",
0917 "SampleAfterValue": "10000",
0918 "UMask": "0x20"
0919 },
0920 {
0921 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
0922 "Counter": "0,1,2,3",
0923 "EventCode": "0xF",
0924 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
0925 "PEBS": "1",
0926 "SampleAfterValue": "40000",
0927 "UMask": "0x2"
0928 },
0929 {
0930 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
0931 "Counter": "0,1,2,3",
0932 "EventCode": "0xF",
0933 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
0934 "PEBS": "1",
0935 "SampleAfterValue": "20000",
0936 "UMask": "0x8"
0937 },
0938 {
0939 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
0940 "Counter": "0,1,2,3",
0941 "EventCode": "0xF",
0942 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
0943 "PEBS": "1",
0944 "SampleAfterValue": "10000",
0945 "UMask": "0x10"
0946 },
0947 {
0948 "BriefDescription": "Load instructions retired IO (Precise Event)",
0949 "Counter": "0,1,2,3",
0950 "EventCode": "0xF",
0951 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
0952 "PEBS": "1",
0953 "SampleAfterValue": "4000",
0954 "UMask": "0x80"
0955 },
0956 {
0957 "BriefDescription": "Offcore L1 data cache writebacks",
0958 "Counter": "0,1,2,3",
0959 "EventCode": "0xB0",
0960 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
0961 "SampleAfterValue": "100000",
0962 "UMask": "0x40"
0963 },
0964 {
0965 "BriefDescription": "Offcore requests blocked due to Super Queue full",
0966 "Counter": "0,1,2,3",
0967 "EventCode": "0xB2",
0968 "EventName": "OFFCORE_REQUESTS_SQ_FULL",
0969 "SampleAfterValue": "100000",
0970 "UMask": "0x1"
0971 },
0972 {
0973 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
0974 "Counter": "2",
0975 "EventCode": "0xB7",
0976 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
0977 "MSRIndex": "0x1A6",
0978 "MSRValue": "0x7F11",
0979 "Offcore": "1",
0980 "SampleAfterValue": "100000",
0981 "UMask": "0x1"
0982 },
0983 {
0984 "BriefDescription": "All offcore data reads",
0985 "Counter": "2",
0986 "EventCode": "0xB7",
0987 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
0988 "MSRIndex": "0x1A6",
0989 "MSRValue": "0xFF11",
0990 "Offcore": "1",
0991 "SampleAfterValue": "100000",
0992 "UMask": "0x1"
0993 },
0994 {
0995 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
0996 "Counter": "2",
0997 "EventCode": "0xB7",
0998 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
0999 "MSRIndex": "0x1A6",
1000 "MSRValue": "0x8011",
1001 "Offcore": "1",
1002 "SampleAfterValue": "100000",
1003 "UMask": "0x1"
1004 },
1005 {
1006 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
1007 "Counter": "2",
1008 "EventCode": "0xB7",
1009 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
1010 "MSRIndex": "0x1A6",
1011 "MSRValue": "0x111",
1012 "Offcore": "1",
1013 "SampleAfterValue": "100000",
1014 "UMask": "0x1"
1015 },
1016 {
1017 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
1018 "Counter": "2",
1019 "EventCode": "0xB7",
1020 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1021 "MSRIndex": "0x1A6",
1022 "MSRValue": "0x211",
1023 "Offcore": "1",
1024 "SampleAfterValue": "100000",
1025 "UMask": "0x1"
1026 },
1027 {
1028 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
1029 "Counter": "2",
1030 "EventCode": "0xB7",
1031 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1032 "MSRIndex": "0x1A6",
1033 "MSRValue": "0x411",
1034 "Offcore": "1",
1035 "SampleAfterValue": "100000",
1036 "UMask": "0x1"
1037 },
1038 {
1039 "BriefDescription": "Offcore data reads satisfied by the LLC",
1040 "Counter": "2",
1041 "EventCode": "0xB7",
1042 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1043 "MSRIndex": "0x1A6",
1044 "MSRValue": "0x711",
1045 "Offcore": "1",
1046 "SampleAfterValue": "100000",
1047 "UMask": "0x1"
1048 },
1049 {
1050 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
1051 "Counter": "2",
1052 "EventCode": "0xB7",
1053 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
1054 "MSRIndex": "0x1A6",
1055 "MSRValue": "0x4711",
1056 "Offcore": "1",
1057 "SampleAfterValue": "100000",
1058 "UMask": "0x1"
1059 },
1060 {
1061 "BriefDescription": "Offcore data reads satisfied by a remote cache",
1062 "Counter": "2",
1063 "EventCode": "0xB7",
1064 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
1065 "MSRIndex": "0x1A6",
1066 "MSRValue": "0x1811",
1067 "Offcore": "1",
1068 "SampleAfterValue": "100000",
1069 "UMask": "0x1"
1070 },
1071 {
1072 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
1073 "Counter": "2",
1074 "EventCode": "0xB7",
1075 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
1076 "MSRIndex": "0x1A6",
1077 "MSRValue": "0x3811",
1078 "Offcore": "1",
1079 "SampleAfterValue": "100000",
1080 "UMask": "0x1"
1081 },
1082 {
1083 "BriefDescription": "Offcore data reads that HIT in a remote cache",
1084 "Counter": "2",
1085 "EventCode": "0xB7",
1086 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
1087 "MSRIndex": "0x1A6",
1088 "MSRValue": "0x1011",
1089 "Offcore": "1",
1090 "SampleAfterValue": "100000",
1091 "UMask": "0x1"
1092 },
1093 {
1094 "BriefDescription": "Offcore data reads that HITM in a remote cache",
1095 "Counter": "2",
1096 "EventCode": "0xB7",
1097 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1098 "MSRIndex": "0x1A6",
1099 "MSRValue": "0x811",
1100 "Offcore": "1",
1101 "SampleAfterValue": "100000",
1102 "UMask": "0x1"
1103 },
1104 {
1105 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
1106 "Counter": "2",
1107 "EventCode": "0xB7",
1108 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1109 "MSRIndex": "0x1A6",
1110 "MSRValue": "0x7F44",
1111 "Offcore": "1",
1112 "SampleAfterValue": "100000",
1113 "UMask": "0x1"
1114 },
1115 {
1116 "BriefDescription": "All offcore code reads",
1117 "Counter": "2",
1118 "EventCode": "0xB7",
1119 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1120 "MSRIndex": "0x1A6",
1121 "MSRValue": "0xFF44",
1122 "Offcore": "1",
1123 "SampleAfterValue": "100000",
1124 "UMask": "0x1"
1125 },
1126 {
1127 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
1128 "Counter": "2",
1129 "EventCode": "0xB7",
1130 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1131 "MSRIndex": "0x1A6",
1132 "MSRValue": "0x8044",
1133 "Offcore": "1",
1134 "SampleAfterValue": "100000",
1135 "UMask": "0x1"
1136 },
1137 {
1138 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
1139 "Counter": "2",
1140 "EventCode": "0xB7",
1141 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1142 "MSRIndex": "0x1A6",
1143 "MSRValue": "0x144",
1144 "Offcore": "1",
1145 "SampleAfterValue": "100000",
1146 "UMask": "0x1"
1147 },
1148 {
1149 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
1150 "Counter": "2",
1151 "EventCode": "0xB7",
1152 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1153 "MSRIndex": "0x1A6",
1154 "MSRValue": "0x244",
1155 "Offcore": "1",
1156 "SampleAfterValue": "100000",
1157 "UMask": "0x1"
1158 },
1159 {
1160 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
1161 "Counter": "2",
1162 "EventCode": "0xB7",
1163 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1164 "MSRIndex": "0x1A6",
1165 "MSRValue": "0x444",
1166 "Offcore": "1",
1167 "SampleAfterValue": "100000",
1168 "UMask": "0x1"
1169 },
1170 {
1171 "BriefDescription": "Offcore code reads satisfied by the LLC",
1172 "Counter": "2",
1173 "EventCode": "0xB7",
1174 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1175 "MSRIndex": "0x1A6",
1176 "MSRValue": "0x744",
1177 "Offcore": "1",
1178 "SampleAfterValue": "100000",
1179 "UMask": "0x1"
1180 },
1181 {
1182 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
1183 "Counter": "2",
1184 "EventCode": "0xB7",
1185 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
1186 "MSRIndex": "0x1A6",
1187 "MSRValue": "0x4744",
1188 "Offcore": "1",
1189 "SampleAfterValue": "100000",
1190 "UMask": "0x1"
1191 },
1192 {
1193 "BriefDescription": "Offcore code reads satisfied by a remote cache",
1194 "Counter": "2",
1195 "EventCode": "0xB7",
1196 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
1197 "MSRIndex": "0x1A6",
1198 "MSRValue": "0x1844",
1199 "Offcore": "1",
1200 "SampleAfterValue": "100000",
1201 "UMask": "0x1"
1202 },
1203 {
1204 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
1205 "Counter": "2",
1206 "EventCode": "0xB7",
1207 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
1208 "MSRIndex": "0x1A6",
1209 "MSRValue": "0x3844",
1210 "Offcore": "1",
1211 "SampleAfterValue": "100000",
1212 "UMask": "0x1"
1213 },
1214 {
1215 "BriefDescription": "Offcore code reads that HIT in a remote cache",
1216 "Counter": "2",
1217 "EventCode": "0xB7",
1218 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
1219 "MSRIndex": "0x1A6",
1220 "MSRValue": "0x1044",
1221 "Offcore": "1",
1222 "SampleAfterValue": "100000",
1223 "UMask": "0x1"
1224 },
1225 {
1226 "BriefDescription": "Offcore code reads that HITM in a remote cache",
1227 "Counter": "2",
1228 "EventCode": "0xB7",
1229 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1230 "MSRIndex": "0x1A6",
1231 "MSRValue": "0x844",
1232 "Offcore": "1",
1233 "SampleAfterValue": "100000",
1234 "UMask": "0x1"
1235 },
1236 {
1237 "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
1238 "Counter": "2",
1239 "EventCode": "0xB7",
1240 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1241 "MSRIndex": "0x1A6",
1242 "MSRValue": "0x7FFF",
1243 "Offcore": "1",
1244 "SampleAfterValue": "100000",
1245 "UMask": "0x1"
1246 },
1247 {
1248 "BriefDescription": "All offcore requests",
1249 "Counter": "2",
1250 "EventCode": "0xB7",
1251 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1252 "MSRIndex": "0x1A6",
1253 "MSRValue": "0xFFFF",
1254 "Offcore": "1",
1255 "SampleAfterValue": "100000",
1256 "UMask": "0x1"
1257 },
1258 {
1259 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
1260 "Counter": "2",
1261 "EventCode": "0xB7",
1262 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1263 "MSRIndex": "0x1A6",
1264 "MSRValue": "0x80FF",
1265 "Offcore": "1",
1266 "SampleAfterValue": "100000",
1267 "UMask": "0x1"
1268 },
1269 {
1270 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
1271 "Counter": "2",
1272 "EventCode": "0xB7",
1273 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1274 "MSRIndex": "0x1A6",
1275 "MSRValue": "0x1FF",
1276 "Offcore": "1",
1277 "SampleAfterValue": "100000",
1278 "UMask": "0x1"
1279 },
1280 {
1281 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
1282 "Counter": "2",
1283 "EventCode": "0xB7",
1284 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1285 "MSRIndex": "0x1A6",
1286 "MSRValue": "0x2FF",
1287 "Offcore": "1",
1288 "SampleAfterValue": "100000",
1289 "UMask": "0x1"
1290 },
1291 {
1292 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
1293 "Counter": "2",
1294 "EventCode": "0xB7",
1295 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1296 "MSRIndex": "0x1A6",
1297 "MSRValue": "0x4FF",
1298 "Offcore": "1",
1299 "SampleAfterValue": "100000",
1300 "UMask": "0x1"
1301 },
1302 {
1303 "BriefDescription": "Offcore requests satisfied by the LLC",
1304 "Counter": "2",
1305 "EventCode": "0xB7",
1306 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1307 "MSRIndex": "0x1A6",
1308 "MSRValue": "0x7FF",
1309 "Offcore": "1",
1310 "SampleAfterValue": "100000",
1311 "UMask": "0x1"
1312 },
1313 {
1314 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
1315 "Counter": "2",
1316 "EventCode": "0xB7",
1317 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
1318 "MSRIndex": "0x1A6",
1319 "MSRValue": "0x47FF",
1320 "Offcore": "1",
1321 "SampleAfterValue": "100000",
1322 "UMask": "0x1"
1323 },
1324 {
1325 "BriefDescription": "Offcore requests satisfied by a remote cache",
1326 "Counter": "2",
1327 "EventCode": "0xB7",
1328 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
1329 "MSRIndex": "0x1A6",
1330 "MSRValue": "0x18FF",
1331 "Offcore": "1",
1332 "SampleAfterValue": "100000",
1333 "UMask": "0x1"
1334 },
1335 {
1336 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
1337 "Counter": "2",
1338 "EventCode": "0xB7",
1339 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
1340 "MSRIndex": "0x1A6",
1341 "MSRValue": "0x38FF",
1342 "Offcore": "1",
1343 "SampleAfterValue": "100000",
1344 "UMask": "0x1"
1345 },
1346 {
1347 "BriefDescription": "Offcore requests that HIT in a remote cache",
1348 "Counter": "2",
1349 "EventCode": "0xB7",
1350 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
1351 "MSRIndex": "0x1A6",
1352 "MSRValue": "0x10FF",
1353 "Offcore": "1",
1354 "SampleAfterValue": "100000",
1355 "UMask": "0x1"
1356 },
1357 {
1358 "BriefDescription": "Offcore requests that HITM in a remote cache",
1359 "Counter": "2",
1360 "EventCode": "0xB7",
1361 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1362 "MSRIndex": "0x1A6",
1363 "MSRValue": "0x8FF",
1364 "Offcore": "1",
1365 "SampleAfterValue": "100000",
1366 "UMask": "0x1"
1367 },
1368 {
1369 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
1370 "Counter": "2",
1371 "EventCode": "0xB7",
1372 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1373 "MSRIndex": "0x1A6",
1374 "MSRValue": "0x7F22",
1375 "Offcore": "1",
1376 "SampleAfterValue": "100000",
1377 "UMask": "0x1"
1378 },
1379 {
1380 "BriefDescription": "All offcore RFO requests",
1381 "Counter": "2",
1382 "EventCode": "0xB7",
1383 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1384 "MSRIndex": "0x1A6",
1385 "MSRValue": "0xFF22",
1386 "Offcore": "1",
1387 "SampleAfterValue": "100000",
1388 "UMask": "0x1"
1389 },
1390 {
1391 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
1392 "Counter": "2",
1393 "EventCode": "0xB7",
1394 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1395 "MSRIndex": "0x1A6",
1396 "MSRValue": "0x8022",
1397 "Offcore": "1",
1398 "SampleAfterValue": "100000",
1399 "UMask": "0x1"
1400 },
1401 {
1402 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
1403 "Counter": "2",
1404 "EventCode": "0xB7",
1405 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1406 "MSRIndex": "0x1A6",
1407 "MSRValue": "0x122",
1408 "Offcore": "1",
1409 "SampleAfterValue": "100000",
1410 "UMask": "0x1"
1411 },
1412 {
1413 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
1414 "Counter": "2",
1415 "EventCode": "0xB7",
1416 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1417 "MSRIndex": "0x1A6",
1418 "MSRValue": "0x222",
1419 "Offcore": "1",
1420 "SampleAfterValue": "100000",
1421 "UMask": "0x1"
1422 },
1423 {
1424 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
1425 "Counter": "2",
1426 "EventCode": "0xB7",
1427 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1428 "MSRIndex": "0x1A6",
1429 "MSRValue": "0x422",
1430 "Offcore": "1",
1431 "SampleAfterValue": "100000",
1432 "UMask": "0x1"
1433 },
1434 {
1435 "BriefDescription": "Offcore RFO requests satisfied by the LLC",
1436 "Counter": "2",
1437 "EventCode": "0xB7",
1438 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1439 "MSRIndex": "0x1A6",
1440 "MSRValue": "0x722",
1441 "Offcore": "1",
1442 "SampleAfterValue": "100000",
1443 "UMask": "0x1"
1444 },
1445 {
1446 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
1447 "Counter": "2",
1448 "EventCode": "0xB7",
1449 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
1450 "MSRIndex": "0x1A6",
1451 "MSRValue": "0x4722",
1452 "Offcore": "1",
1453 "SampleAfterValue": "100000",
1454 "UMask": "0x1"
1455 },
1456 {
1457 "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
1458 "Counter": "2",
1459 "EventCode": "0xB7",
1460 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
1461 "MSRIndex": "0x1A6",
1462 "MSRValue": "0x1822",
1463 "Offcore": "1",
1464 "SampleAfterValue": "100000",
1465 "UMask": "0x1"
1466 },
1467 {
1468 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
1469 "Counter": "2",
1470 "EventCode": "0xB7",
1471 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
1472 "MSRIndex": "0x1A6",
1473 "MSRValue": "0x3822",
1474 "Offcore": "1",
1475 "SampleAfterValue": "100000",
1476 "UMask": "0x1"
1477 },
1478 {
1479 "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
1480 "Counter": "2",
1481 "EventCode": "0xB7",
1482 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
1483 "MSRIndex": "0x1A6",
1484 "MSRValue": "0x1022",
1485 "Offcore": "1",
1486 "SampleAfterValue": "100000",
1487 "UMask": "0x1"
1488 },
1489 {
1490 "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
1491 "Counter": "2",
1492 "EventCode": "0xB7",
1493 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1494 "MSRIndex": "0x1A6",
1495 "MSRValue": "0x822",
1496 "Offcore": "1",
1497 "SampleAfterValue": "100000",
1498 "UMask": "0x1"
1499 },
1500 {
1501 "BriefDescription": "Offcore writebacks to any cache or DRAM.",
1502 "Counter": "2",
1503 "EventCode": "0xB7",
1504 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1505 "MSRIndex": "0x1A6",
1506 "MSRValue": "0x7F08",
1507 "Offcore": "1",
1508 "SampleAfterValue": "100000",
1509 "UMask": "0x1"
1510 },
1511 {
1512 "BriefDescription": "All offcore writebacks",
1513 "Counter": "2",
1514 "EventCode": "0xB7",
1515 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1516 "MSRIndex": "0x1A6",
1517 "MSRValue": "0xFF08",
1518 "Offcore": "1",
1519 "SampleAfterValue": "100000",
1520 "UMask": "0x1"
1521 },
1522 {
1523 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
1524 "Counter": "2",
1525 "EventCode": "0xB7",
1526 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1527 "MSRIndex": "0x1A6",
1528 "MSRValue": "0x8008",
1529 "Offcore": "1",
1530 "SampleAfterValue": "100000",
1531 "UMask": "0x1"
1532 },
1533 {
1534 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
1535 "Counter": "2",
1536 "EventCode": "0xB7",
1537 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1538 "MSRIndex": "0x1A6",
1539 "MSRValue": "0x108",
1540 "Offcore": "1",
1541 "SampleAfterValue": "100000",
1542 "UMask": "0x1"
1543 },
1544 {
1545 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
1546 "Counter": "2",
1547 "EventCode": "0xB7",
1548 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1549 "MSRIndex": "0x1A6",
1550 "MSRValue": "0x408",
1551 "Offcore": "1",
1552 "SampleAfterValue": "100000",
1553 "UMask": "0x1"
1554 },
1555 {
1556 "BriefDescription": "Offcore writebacks to the LLC",
1557 "Counter": "2",
1558 "EventCode": "0xB7",
1559 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1560 "MSRIndex": "0x1A6",
1561 "MSRValue": "0x708",
1562 "Offcore": "1",
1563 "SampleAfterValue": "100000",
1564 "UMask": "0x1"
1565 },
1566 {
1567 "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
1568 "Counter": "2",
1569 "EventCode": "0xB7",
1570 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
1571 "MSRIndex": "0x1A6",
1572 "MSRValue": "0x4708",
1573 "Offcore": "1",
1574 "SampleAfterValue": "100000",
1575 "UMask": "0x1"
1576 },
1577 {
1578 "BriefDescription": "Offcore writebacks to a remote cache",
1579 "Counter": "2",
1580 "EventCode": "0xB7",
1581 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
1582 "MSRIndex": "0x1A6",
1583 "MSRValue": "0x1808",
1584 "Offcore": "1",
1585 "SampleAfterValue": "100000",
1586 "UMask": "0x1"
1587 },
1588 {
1589 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
1590 "Counter": "2",
1591 "EventCode": "0xB7",
1592 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
1593 "MSRIndex": "0x1A6",
1594 "MSRValue": "0x3808",
1595 "Offcore": "1",
1596 "SampleAfterValue": "100000",
1597 "UMask": "0x1"
1598 },
1599 {
1600 "BriefDescription": "Offcore writebacks that HIT in a remote cache",
1601 "Counter": "2",
1602 "EventCode": "0xB7",
1603 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
1604 "MSRIndex": "0x1A6",
1605 "MSRValue": "0x1008",
1606 "Offcore": "1",
1607 "SampleAfterValue": "100000",
1608 "UMask": "0x1"
1609 },
1610 {
1611 "BriefDescription": "Offcore writebacks that HITM in a remote cache",
1612 "Counter": "2",
1613 "EventCode": "0xB7",
1614 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1615 "MSRIndex": "0x1A6",
1616 "MSRValue": "0x808",
1617 "Offcore": "1",
1618 "SampleAfterValue": "100000",
1619 "UMask": "0x1"
1620 },
1621 {
1622 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
1623 "Counter": "2",
1624 "EventCode": "0xB7",
1625 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1626 "MSRIndex": "0x1A6",
1627 "MSRValue": "0x7F77",
1628 "Offcore": "1",
1629 "SampleAfterValue": "100000",
1630 "UMask": "0x1"
1631 },
1632 {
1633 "BriefDescription": "All offcore code or data read requests",
1634 "Counter": "2",
1635 "EventCode": "0xB7",
1636 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1637 "MSRIndex": "0x1A6",
1638 "MSRValue": "0xFF77",
1639 "Offcore": "1",
1640 "SampleAfterValue": "100000",
1641 "UMask": "0x1"
1642 },
1643 {
1644 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
1645 "Counter": "2",
1646 "EventCode": "0xB7",
1647 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1648 "MSRIndex": "0x1A6",
1649 "MSRValue": "0x8077",
1650 "Offcore": "1",
1651 "SampleAfterValue": "100000",
1652 "UMask": "0x1"
1653 },
1654 {
1655 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
1656 "Counter": "2",
1657 "EventCode": "0xB7",
1658 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1659 "MSRIndex": "0x1A6",
1660 "MSRValue": "0x177",
1661 "Offcore": "1",
1662 "SampleAfterValue": "100000",
1663 "UMask": "0x1"
1664 },
1665 {
1666 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
1667 "Counter": "2",
1668 "EventCode": "0xB7",
1669 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1670 "MSRIndex": "0x1A6",
1671 "MSRValue": "0x277",
1672 "Offcore": "1",
1673 "SampleAfterValue": "100000",
1674 "UMask": "0x1"
1675 },
1676 {
1677 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
1678 "Counter": "2",
1679 "EventCode": "0xB7",
1680 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1681 "MSRIndex": "0x1A6",
1682 "MSRValue": "0x477",
1683 "Offcore": "1",
1684 "SampleAfterValue": "100000",
1685 "UMask": "0x1"
1686 },
1687 {
1688 "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
1689 "Counter": "2",
1690 "EventCode": "0xB7",
1691 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1692 "MSRIndex": "0x1A6",
1693 "MSRValue": "0x777",
1694 "Offcore": "1",
1695 "SampleAfterValue": "100000",
1696 "UMask": "0x1"
1697 },
1698 {
1699 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
1700 "Counter": "2",
1701 "EventCode": "0xB7",
1702 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
1703 "MSRIndex": "0x1A6",
1704 "MSRValue": "0x4777",
1705 "Offcore": "1",
1706 "SampleAfterValue": "100000",
1707 "UMask": "0x1"
1708 },
1709 {
1710 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
1711 "Counter": "2",
1712 "EventCode": "0xB7",
1713 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
1714 "MSRIndex": "0x1A6",
1715 "MSRValue": "0x1877",
1716 "Offcore": "1",
1717 "SampleAfterValue": "100000",
1718 "UMask": "0x1"
1719 },
1720 {
1721 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
1722 "Counter": "2",
1723 "EventCode": "0xB7",
1724 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
1725 "MSRIndex": "0x1A6",
1726 "MSRValue": "0x3877",
1727 "Offcore": "1",
1728 "SampleAfterValue": "100000",
1729 "UMask": "0x1"
1730 },
1731 {
1732 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
1733 "Counter": "2",
1734 "EventCode": "0xB7",
1735 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
1736 "MSRIndex": "0x1A6",
1737 "MSRValue": "0x1077",
1738 "Offcore": "1",
1739 "SampleAfterValue": "100000",
1740 "UMask": "0x1"
1741 },
1742 {
1743 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
1744 "Counter": "2",
1745 "EventCode": "0xB7",
1746 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1747 "MSRIndex": "0x1A6",
1748 "MSRValue": "0x877",
1749 "Offcore": "1",
1750 "SampleAfterValue": "100000",
1751 "UMask": "0x1"
1752 },
1753 {
1754 "BriefDescription": "Offcore request = all data, response = any cache_dram",
1755 "Counter": "2",
1756 "EventCode": "0xB7",
1757 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1758 "MSRIndex": "0x1A6",
1759 "MSRValue": "0x7F33",
1760 "Offcore": "1",
1761 "SampleAfterValue": "100000",
1762 "UMask": "0x1"
1763 },
1764 {
1765 "BriefDescription": "Offcore request = all data, response = any location",
1766 "Counter": "2",
1767 "EventCode": "0xB7",
1768 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1769 "MSRIndex": "0x1A6",
1770 "MSRValue": "0xFF33",
1771 "Offcore": "1",
1772 "SampleAfterValue": "100000",
1773 "UMask": "0x1"
1774 },
1775 {
1776 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
1777 "Counter": "2",
1778 "EventCode": "0xB7",
1779 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1780 "MSRIndex": "0x1A6",
1781 "MSRValue": "0x8033",
1782 "Offcore": "1",
1783 "SampleAfterValue": "100000",
1784 "UMask": "0x1"
1785 },
1786 {
1787 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
1788 "Counter": "2",
1789 "EventCode": "0xB7",
1790 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1791 "MSRIndex": "0x1A6",
1792 "MSRValue": "0x133",
1793 "Offcore": "1",
1794 "SampleAfterValue": "100000",
1795 "UMask": "0x1"
1796 },
1797 {
1798 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
1799 "Counter": "2",
1800 "EventCode": "0xB7",
1801 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1802 "MSRIndex": "0x1A6",
1803 "MSRValue": "0x233",
1804 "Offcore": "1",
1805 "SampleAfterValue": "100000",
1806 "UMask": "0x1"
1807 },
1808 {
1809 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
1810 "Counter": "2",
1811 "EventCode": "0xB7",
1812 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1813 "MSRIndex": "0x1A6",
1814 "MSRValue": "0x433",
1815 "Offcore": "1",
1816 "SampleAfterValue": "100000",
1817 "UMask": "0x1"
1818 },
1819 {
1820 "BriefDescription": "Offcore request = all data, response = local cache",
1821 "Counter": "2",
1822 "EventCode": "0xB7",
1823 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1824 "MSRIndex": "0x1A6",
1825 "MSRValue": "0x733",
1826 "Offcore": "1",
1827 "SampleAfterValue": "100000",
1828 "UMask": "0x1"
1829 },
1830 {
1831 "BriefDescription": "Offcore request = all data, response = local cache or dram",
1832 "Counter": "2",
1833 "EventCode": "0xB7",
1834 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
1835 "MSRIndex": "0x1A6",
1836 "MSRValue": "0x4733",
1837 "Offcore": "1",
1838 "SampleAfterValue": "100000",
1839 "UMask": "0x1"
1840 },
1841 {
1842 "BriefDescription": "Offcore request = all data, response = remote cache",
1843 "Counter": "2",
1844 "EventCode": "0xB7",
1845 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
1846 "MSRIndex": "0x1A6",
1847 "MSRValue": "0x1833",
1848 "Offcore": "1",
1849 "SampleAfterValue": "100000",
1850 "UMask": "0x1"
1851 },
1852 {
1853 "BriefDescription": "Offcore request = all data, response = remote cache or dram",
1854 "Counter": "2",
1855 "EventCode": "0xB7",
1856 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
1857 "MSRIndex": "0x1A6",
1858 "MSRValue": "0x3833",
1859 "Offcore": "1",
1860 "SampleAfterValue": "100000",
1861 "UMask": "0x1"
1862 },
1863 {
1864 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
1865 "Counter": "2",
1866 "EventCode": "0xB7",
1867 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
1868 "MSRIndex": "0x1A6",
1869 "MSRValue": "0x1033",
1870 "Offcore": "1",
1871 "SampleAfterValue": "100000",
1872 "UMask": "0x1"
1873 },
1874 {
1875 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
1876 "Counter": "2",
1877 "EventCode": "0xB7",
1878 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1879 "MSRIndex": "0x1A6",
1880 "MSRValue": "0x833",
1881 "Offcore": "1",
1882 "SampleAfterValue": "100000",
1883 "UMask": "0x1"
1884 },
1885 {
1886 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
1887 "Counter": "2",
1888 "EventCode": "0xB7",
1889 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1890 "MSRIndex": "0x1A6",
1891 "MSRValue": "0x7F03",
1892 "Offcore": "1",
1893 "SampleAfterValue": "100000",
1894 "UMask": "0x1"
1895 },
1896 {
1897 "BriefDescription": "All offcore demand data requests",
1898 "Counter": "2",
1899 "EventCode": "0xB7",
1900 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1901 "MSRIndex": "0x1A6",
1902 "MSRValue": "0xFF03",
1903 "Offcore": "1",
1904 "SampleAfterValue": "100000",
1905 "UMask": "0x1"
1906 },
1907 {
1908 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
1909 "Counter": "2",
1910 "EventCode": "0xB7",
1911 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1912 "MSRIndex": "0x1A6",
1913 "MSRValue": "0x8003",
1914 "Offcore": "1",
1915 "SampleAfterValue": "100000",
1916 "UMask": "0x1"
1917 },
1918 {
1919 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
1920 "Counter": "2",
1921 "EventCode": "0xB7",
1922 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1923 "MSRIndex": "0x1A6",
1924 "MSRValue": "0x103",
1925 "Offcore": "1",
1926 "SampleAfterValue": "100000",
1927 "UMask": "0x1"
1928 },
1929 {
1930 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
1931 "Counter": "2",
1932 "EventCode": "0xB7",
1933 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1934 "MSRIndex": "0x1A6",
1935 "MSRValue": "0x203",
1936 "Offcore": "1",
1937 "SampleAfterValue": "100000",
1938 "UMask": "0x1"
1939 },
1940 {
1941 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
1942 "Counter": "2",
1943 "EventCode": "0xB7",
1944 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1945 "MSRIndex": "0x1A6",
1946 "MSRValue": "0x403",
1947 "Offcore": "1",
1948 "SampleAfterValue": "100000",
1949 "UMask": "0x1"
1950 },
1951 {
1952 "BriefDescription": "Offcore demand data requests satisfied by the LLC",
1953 "Counter": "2",
1954 "EventCode": "0xB7",
1955 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1956 "MSRIndex": "0x1A6",
1957 "MSRValue": "0x703",
1958 "Offcore": "1",
1959 "SampleAfterValue": "100000",
1960 "UMask": "0x1"
1961 },
1962 {
1963 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
1964 "Counter": "2",
1965 "EventCode": "0xB7",
1966 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
1967 "MSRIndex": "0x1A6",
1968 "MSRValue": "0x4703",
1969 "Offcore": "1",
1970 "SampleAfterValue": "100000",
1971 "UMask": "0x1"
1972 },
1973 {
1974 "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
1975 "Counter": "2",
1976 "EventCode": "0xB7",
1977 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
1978 "MSRIndex": "0x1A6",
1979 "MSRValue": "0x1803",
1980 "Offcore": "1",
1981 "SampleAfterValue": "100000",
1982 "UMask": "0x1"
1983 },
1984 {
1985 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
1986 "Counter": "2",
1987 "EventCode": "0xB7",
1988 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
1989 "MSRIndex": "0x1A6",
1990 "MSRValue": "0x3803",
1991 "Offcore": "1",
1992 "SampleAfterValue": "100000",
1993 "UMask": "0x1"
1994 },
1995 {
1996 "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
1997 "Counter": "2",
1998 "EventCode": "0xB7",
1999 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
2000 "MSRIndex": "0x1A6",
2001 "MSRValue": "0x1003",
2002 "Offcore": "1",
2003 "SampleAfterValue": "100000",
2004 "UMask": "0x1"
2005 },
2006 {
2007 "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
2008 "Counter": "2",
2009 "EventCode": "0xB7",
2010 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
2011 "MSRIndex": "0x1A6",
2012 "MSRValue": "0x803",
2013 "Offcore": "1",
2014 "SampleAfterValue": "100000",
2015 "UMask": "0x1"
2016 },
2017 {
2018 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
2019 "Counter": "2",
2020 "EventCode": "0xB7",
2021 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
2022 "MSRIndex": "0x1A6",
2023 "MSRValue": "0x7F01",
2024 "Offcore": "1",
2025 "SampleAfterValue": "100000",
2026 "UMask": "0x1"
2027 },
2028 {
2029 "BriefDescription": "All offcore demand data reads",
2030 "Counter": "2",
2031 "EventCode": "0xB7",
2032 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
2033 "MSRIndex": "0x1A6",
2034 "MSRValue": "0xFF01",
2035 "Offcore": "1",
2036 "SampleAfterValue": "100000",
2037 "UMask": "0x1"
2038 },
2039 {
2040 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
2041 "Counter": "2",
2042 "EventCode": "0xB7",
2043 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
2044 "MSRIndex": "0x1A6",
2045 "MSRValue": "0x8001",
2046 "Offcore": "1",
2047 "SampleAfterValue": "100000",
2048 "UMask": "0x1"
2049 },
2050 {
2051 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
2052 "Counter": "2",
2053 "EventCode": "0xB7",
2054 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2055 "MSRIndex": "0x1A6",
2056 "MSRValue": "0x101",
2057 "Offcore": "1",
2058 "SampleAfterValue": "100000",
2059 "UMask": "0x1"
2060 },
2061 {
2062 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
2063 "Counter": "2",
2064 "EventCode": "0xB7",
2065 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2066 "MSRIndex": "0x1A6",
2067 "MSRValue": "0x201",
2068 "Offcore": "1",
2069 "SampleAfterValue": "100000",
2070 "UMask": "0x1"
2071 },
2072 {
2073 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
2074 "Counter": "2",
2075 "EventCode": "0xB7",
2076 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2077 "MSRIndex": "0x1A6",
2078 "MSRValue": "0x401",
2079 "Offcore": "1",
2080 "SampleAfterValue": "100000",
2081 "UMask": "0x1"
2082 },
2083 {
2084 "BriefDescription": "Offcore demand data reads satisfied by the LLC",
2085 "Counter": "2",
2086 "EventCode": "0xB7",
2087 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
2088 "MSRIndex": "0x1A6",
2089 "MSRValue": "0x701",
2090 "Offcore": "1",
2091 "SampleAfterValue": "100000",
2092 "UMask": "0x1"
2093 },
2094 {
2095 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
2096 "Counter": "2",
2097 "EventCode": "0xB7",
2098 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
2099 "MSRIndex": "0x1A6",
2100 "MSRValue": "0x4701",
2101 "Offcore": "1",
2102 "SampleAfterValue": "100000",
2103 "UMask": "0x1"
2104 },
2105 {
2106 "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
2107 "Counter": "2",
2108 "EventCode": "0xB7",
2109 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
2110 "MSRIndex": "0x1A6",
2111 "MSRValue": "0x1801",
2112 "Offcore": "1",
2113 "SampleAfterValue": "100000",
2114 "UMask": "0x1"
2115 },
2116 {
2117 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
2118 "Counter": "2",
2119 "EventCode": "0xB7",
2120 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
2121 "MSRIndex": "0x1A6",
2122 "MSRValue": "0x3801",
2123 "Offcore": "1",
2124 "SampleAfterValue": "100000",
2125 "UMask": "0x1"
2126 },
2127 {
2128 "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
2129 "Counter": "2",
2130 "EventCode": "0xB7",
2131 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
2132 "MSRIndex": "0x1A6",
2133 "MSRValue": "0x1001",
2134 "Offcore": "1",
2135 "SampleAfterValue": "100000",
2136 "UMask": "0x1"
2137 },
2138 {
2139 "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
2140 "Counter": "2",
2141 "EventCode": "0xB7",
2142 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
2143 "MSRIndex": "0x1A6",
2144 "MSRValue": "0x801",
2145 "Offcore": "1",
2146 "SampleAfterValue": "100000",
2147 "UMask": "0x1"
2148 },
2149 {
2150 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
2151 "Counter": "2",
2152 "EventCode": "0xB7",
2153 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
2154 "MSRIndex": "0x1A6",
2155 "MSRValue": "0x7F04",
2156 "Offcore": "1",
2157 "SampleAfterValue": "100000",
2158 "UMask": "0x1"
2159 },
2160 {
2161 "BriefDescription": "All offcore demand code reads",
2162 "Counter": "2",
2163 "EventCode": "0xB7",
2164 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
2165 "MSRIndex": "0x1A6",
2166 "MSRValue": "0xFF04",
2167 "Offcore": "1",
2168 "SampleAfterValue": "100000",
2169 "UMask": "0x1"
2170 },
2171 {
2172 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
2173 "Counter": "2",
2174 "EventCode": "0xB7",
2175 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
2176 "MSRIndex": "0x1A6",
2177 "MSRValue": "0x8004",
2178 "Offcore": "1",
2179 "SampleAfterValue": "100000",
2180 "UMask": "0x1"
2181 },
2182 {
2183 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
2184 "Counter": "2",
2185 "EventCode": "0xB7",
2186 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
2187 "MSRIndex": "0x1A6",
2188 "MSRValue": "0x104",
2189 "Offcore": "1",
2190 "SampleAfterValue": "100000",
2191 "UMask": "0x1"
2192 },
2193 {
2194 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
2195 "Counter": "2",
2196 "EventCode": "0xB7",
2197 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2198 "MSRIndex": "0x1A6",
2199 "MSRValue": "0x204",
2200 "Offcore": "1",
2201 "SampleAfterValue": "100000",
2202 "UMask": "0x1"
2203 },
2204 {
2205 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
2206 "Counter": "2",
2207 "EventCode": "0xB7",
2208 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2209 "MSRIndex": "0x1A6",
2210 "MSRValue": "0x404",
2211 "Offcore": "1",
2212 "SampleAfterValue": "100000",
2213 "UMask": "0x1"
2214 },
2215 {
2216 "BriefDescription": "Offcore demand code reads satisfied by the LLC",
2217 "Counter": "2",
2218 "EventCode": "0xB7",
2219 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2220 "MSRIndex": "0x1A6",
2221 "MSRValue": "0x704",
2222 "Offcore": "1",
2223 "SampleAfterValue": "100000",
2224 "UMask": "0x1"
2225 },
2226 {
2227 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
2228 "Counter": "2",
2229 "EventCode": "0xB7",
2230 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
2231 "MSRIndex": "0x1A6",
2232 "MSRValue": "0x4704",
2233 "Offcore": "1",
2234 "SampleAfterValue": "100000",
2235 "UMask": "0x1"
2236 },
2237 {
2238 "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
2239 "Counter": "2",
2240 "EventCode": "0xB7",
2241 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
2242 "MSRIndex": "0x1A6",
2243 "MSRValue": "0x1804",
2244 "Offcore": "1",
2245 "SampleAfterValue": "100000",
2246 "UMask": "0x1"
2247 },
2248 {
2249 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
2250 "Counter": "2",
2251 "EventCode": "0xB7",
2252 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
2253 "MSRIndex": "0x1A6",
2254 "MSRValue": "0x3804",
2255 "Offcore": "1",
2256 "SampleAfterValue": "100000",
2257 "UMask": "0x1"
2258 },
2259 {
2260 "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
2261 "Counter": "2",
2262 "EventCode": "0xB7",
2263 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
2264 "MSRIndex": "0x1A6",
2265 "MSRValue": "0x1004",
2266 "Offcore": "1",
2267 "SampleAfterValue": "100000",
2268 "UMask": "0x1"
2269 },
2270 {
2271 "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
2272 "Counter": "2",
2273 "EventCode": "0xB7",
2274 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2275 "MSRIndex": "0x1A6",
2276 "MSRValue": "0x804",
2277 "Offcore": "1",
2278 "SampleAfterValue": "100000",
2279 "UMask": "0x1"
2280 },
2281 {
2282 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
2283 "Counter": "2",
2284 "EventCode": "0xB7",
2285 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2286 "MSRIndex": "0x1A6",
2287 "MSRValue": "0x7F02",
2288 "Offcore": "1",
2289 "SampleAfterValue": "100000",
2290 "UMask": "0x1"
2291 },
2292 {
2293 "BriefDescription": "All offcore demand RFO requests",
2294 "Counter": "2",
2295 "EventCode": "0xB7",
2296 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2297 "MSRIndex": "0x1A6",
2298 "MSRValue": "0xFF02",
2299 "Offcore": "1",
2300 "SampleAfterValue": "100000",
2301 "UMask": "0x1"
2302 },
2303 {
2304 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
2305 "Counter": "2",
2306 "EventCode": "0xB7",
2307 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2308 "MSRIndex": "0x1A6",
2309 "MSRValue": "0x8002",
2310 "Offcore": "1",
2311 "SampleAfterValue": "100000",
2312 "UMask": "0x1"
2313 },
2314 {
2315 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
2316 "Counter": "2",
2317 "EventCode": "0xB7",
2318 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2319 "MSRIndex": "0x1A6",
2320 "MSRValue": "0x102",
2321 "Offcore": "1",
2322 "SampleAfterValue": "100000",
2323 "UMask": "0x1"
2324 },
2325 {
2326 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
2327 "Counter": "2",
2328 "EventCode": "0xB7",
2329 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2330 "MSRIndex": "0x1A6",
2331 "MSRValue": "0x202",
2332 "Offcore": "1",
2333 "SampleAfterValue": "100000",
2334 "UMask": "0x1"
2335 },
2336 {
2337 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
2338 "Counter": "2",
2339 "EventCode": "0xB7",
2340 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2341 "MSRIndex": "0x1A6",
2342 "MSRValue": "0x402",
2343 "Offcore": "1",
2344 "SampleAfterValue": "100000",
2345 "UMask": "0x1"
2346 },
2347 {
2348 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
2349 "Counter": "2",
2350 "EventCode": "0xB7",
2351 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2352 "MSRIndex": "0x1A6",
2353 "MSRValue": "0x702",
2354 "Offcore": "1",
2355 "SampleAfterValue": "100000",
2356 "UMask": "0x1"
2357 },
2358 {
2359 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
2360 "Counter": "2",
2361 "EventCode": "0xB7",
2362 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
2363 "MSRIndex": "0x1A6",
2364 "MSRValue": "0x4702",
2365 "Offcore": "1",
2366 "SampleAfterValue": "100000",
2367 "UMask": "0x1"
2368 },
2369 {
2370 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
2371 "Counter": "2",
2372 "EventCode": "0xB7",
2373 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
2374 "MSRIndex": "0x1A6",
2375 "MSRValue": "0x1802",
2376 "Offcore": "1",
2377 "SampleAfterValue": "100000",
2378 "UMask": "0x1"
2379 },
2380 {
2381 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
2382 "Counter": "2",
2383 "EventCode": "0xB7",
2384 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
2385 "MSRIndex": "0x1A6",
2386 "MSRValue": "0x3802",
2387 "Offcore": "1",
2388 "SampleAfterValue": "100000",
2389 "UMask": "0x1"
2390 },
2391 {
2392 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
2393 "Counter": "2",
2394 "EventCode": "0xB7",
2395 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
2396 "MSRIndex": "0x1A6",
2397 "MSRValue": "0x1002",
2398 "Offcore": "1",
2399 "SampleAfterValue": "100000",
2400 "UMask": "0x1"
2401 },
2402 {
2403 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
2404 "Counter": "2",
2405 "EventCode": "0xB7",
2406 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2407 "MSRIndex": "0x1A6",
2408 "MSRValue": "0x802",
2409 "Offcore": "1",
2410 "SampleAfterValue": "100000",
2411 "UMask": "0x1"
2412 },
2413 {
2414 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
2415 "Counter": "2",
2416 "EventCode": "0xB7",
2417 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2418 "MSRIndex": "0x1A6",
2419 "MSRValue": "0x7F80",
2420 "Offcore": "1",
2421 "SampleAfterValue": "100000",
2422 "UMask": "0x1"
2423 },
2424 {
2425 "BriefDescription": "All offcore other requests",
2426 "Counter": "2",
2427 "EventCode": "0xB7",
2428 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2429 "MSRIndex": "0x1A6",
2430 "MSRValue": "0xFF80",
2431 "Offcore": "1",
2432 "SampleAfterValue": "100000",
2433 "UMask": "0x1"
2434 },
2435 {
2436 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
2437 "Counter": "2",
2438 "EventCode": "0xB7",
2439 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2440 "MSRIndex": "0x1A6",
2441 "MSRValue": "0x8080",
2442 "Offcore": "1",
2443 "SampleAfterValue": "100000",
2444 "UMask": "0x1"
2445 },
2446 {
2447 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
2448 "Counter": "2",
2449 "EventCode": "0xB7",
2450 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2451 "MSRIndex": "0x1A6",
2452 "MSRValue": "0x180",
2453 "Offcore": "1",
2454 "SampleAfterValue": "100000",
2455 "UMask": "0x1"
2456 },
2457 {
2458 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
2459 "Counter": "2",
2460 "EventCode": "0xB7",
2461 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2462 "MSRIndex": "0x1A6",
2463 "MSRValue": "0x280",
2464 "Offcore": "1",
2465 "SampleAfterValue": "100000",
2466 "UMask": "0x1"
2467 },
2468 {
2469 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
2470 "Counter": "2",
2471 "EventCode": "0xB7",
2472 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2473 "MSRIndex": "0x1A6",
2474 "MSRValue": "0x480",
2475 "Offcore": "1",
2476 "SampleAfterValue": "100000",
2477 "UMask": "0x1"
2478 },
2479 {
2480 "BriefDescription": "Offcore other requests satisfied by the LLC",
2481 "Counter": "2",
2482 "EventCode": "0xB7",
2483 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2484 "MSRIndex": "0x1A6",
2485 "MSRValue": "0x780",
2486 "Offcore": "1",
2487 "SampleAfterValue": "100000",
2488 "UMask": "0x1"
2489 },
2490 {
2491 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
2492 "Counter": "2",
2493 "EventCode": "0xB7",
2494 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
2495 "MSRIndex": "0x1A6",
2496 "MSRValue": "0x4780",
2497 "Offcore": "1",
2498 "SampleAfterValue": "100000",
2499 "UMask": "0x1"
2500 },
2501 {
2502 "BriefDescription": "Offcore other requests satisfied by a remote cache",
2503 "Counter": "2",
2504 "EventCode": "0xB7",
2505 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
2506 "MSRIndex": "0x1A6",
2507 "MSRValue": "0x1880",
2508 "Offcore": "1",
2509 "SampleAfterValue": "100000",
2510 "UMask": "0x1"
2511 },
2512 {
2513 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
2514 "Counter": "2",
2515 "EventCode": "0xB7",
2516 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
2517 "MSRIndex": "0x1A6",
2518 "MSRValue": "0x3880",
2519 "Offcore": "1",
2520 "SampleAfterValue": "100000",
2521 "UMask": "0x1"
2522 },
2523 {
2524 "BriefDescription": "Offcore other requests that HIT in a remote cache",
2525 "Counter": "2",
2526 "EventCode": "0xB7",
2527 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
2528 "MSRIndex": "0x1A6",
2529 "MSRValue": "0x1080",
2530 "Offcore": "1",
2531 "SampleAfterValue": "100000",
2532 "UMask": "0x1"
2533 },
2534 {
2535 "BriefDescription": "Offcore other requests that HITM in a remote cache",
2536 "Counter": "2",
2537 "EventCode": "0xB7",
2538 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2539 "MSRIndex": "0x1A6",
2540 "MSRValue": "0x880",
2541 "Offcore": "1",
2542 "SampleAfterValue": "100000",
2543 "UMask": "0x1"
2544 },
2545 {
2546 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
2547 "Counter": "2",
2548 "EventCode": "0xB7",
2549 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2550 "MSRIndex": "0x1A6",
2551 "MSRValue": "0x7F30",
2552 "Offcore": "1",
2553 "SampleAfterValue": "100000",
2554 "UMask": "0x1"
2555 },
2556 {
2557 "BriefDescription": "All offcore prefetch data requests",
2558 "Counter": "2",
2559 "EventCode": "0xB7",
2560 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2561 "MSRIndex": "0x1A6",
2562 "MSRValue": "0xFF30",
2563 "Offcore": "1",
2564 "SampleAfterValue": "100000",
2565 "UMask": "0x1"
2566 },
2567 {
2568 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
2569 "Counter": "2",
2570 "EventCode": "0xB7",
2571 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2572 "MSRIndex": "0x1A6",
2573 "MSRValue": "0x8030",
2574 "Offcore": "1",
2575 "SampleAfterValue": "100000",
2576 "UMask": "0x1"
2577 },
2578 {
2579 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
2580 "Counter": "2",
2581 "EventCode": "0xB7",
2582 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2583 "MSRIndex": "0x1A6",
2584 "MSRValue": "0x130",
2585 "Offcore": "1",
2586 "SampleAfterValue": "100000",
2587 "UMask": "0x1"
2588 },
2589 {
2590 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
2591 "Counter": "2",
2592 "EventCode": "0xB7",
2593 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2594 "MSRIndex": "0x1A6",
2595 "MSRValue": "0x230",
2596 "Offcore": "1",
2597 "SampleAfterValue": "100000",
2598 "UMask": "0x1"
2599 },
2600 {
2601 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
2602 "Counter": "2",
2603 "EventCode": "0xB7",
2604 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2605 "MSRIndex": "0x1A6",
2606 "MSRValue": "0x430",
2607 "Offcore": "1",
2608 "SampleAfterValue": "100000",
2609 "UMask": "0x1"
2610 },
2611 {
2612 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
2613 "Counter": "2",
2614 "EventCode": "0xB7",
2615 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2616 "MSRIndex": "0x1A6",
2617 "MSRValue": "0x730",
2618 "Offcore": "1",
2619 "SampleAfterValue": "100000",
2620 "UMask": "0x1"
2621 },
2622 {
2623 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
2624 "Counter": "2",
2625 "EventCode": "0xB7",
2626 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
2627 "MSRIndex": "0x1A6",
2628 "MSRValue": "0x4730",
2629 "Offcore": "1",
2630 "SampleAfterValue": "100000",
2631 "UMask": "0x1"
2632 },
2633 {
2634 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
2635 "Counter": "2",
2636 "EventCode": "0xB7",
2637 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
2638 "MSRIndex": "0x1A6",
2639 "MSRValue": "0x1830",
2640 "Offcore": "1",
2641 "SampleAfterValue": "100000",
2642 "UMask": "0x1"
2643 },
2644 {
2645 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
2646 "Counter": "2",
2647 "EventCode": "0xB7",
2648 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
2649 "MSRIndex": "0x1A6",
2650 "MSRValue": "0x3830",
2651 "Offcore": "1",
2652 "SampleAfterValue": "100000",
2653 "UMask": "0x1"
2654 },
2655 {
2656 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
2657 "Counter": "2",
2658 "EventCode": "0xB7",
2659 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
2660 "MSRIndex": "0x1A6",
2661 "MSRValue": "0x1030",
2662 "Offcore": "1",
2663 "SampleAfterValue": "100000",
2664 "UMask": "0x1"
2665 },
2666 {
2667 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
2668 "Counter": "2",
2669 "EventCode": "0xB7",
2670 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2671 "MSRIndex": "0x1A6",
2672 "MSRValue": "0x830",
2673 "Offcore": "1",
2674 "SampleAfterValue": "100000",
2675 "UMask": "0x1"
2676 },
2677 {
2678 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
2679 "Counter": "2",
2680 "EventCode": "0xB7",
2681 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2682 "MSRIndex": "0x1A6",
2683 "MSRValue": "0x7F10",
2684 "Offcore": "1",
2685 "SampleAfterValue": "100000",
2686 "UMask": "0x1"
2687 },
2688 {
2689 "BriefDescription": "All offcore prefetch data reads",
2690 "Counter": "2",
2691 "EventCode": "0xB7",
2692 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2693 "MSRIndex": "0x1A6",
2694 "MSRValue": "0xFF10",
2695 "Offcore": "1",
2696 "SampleAfterValue": "100000",
2697 "UMask": "0x1"
2698 },
2699 {
2700 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
2701 "Counter": "2",
2702 "EventCode": "0xB7",
2703 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2704 "MSRIndex": "0x1A6",
2705 "MSRValue": "0x8010",
2706 "Offcore": "1",
2707 "SampleAfterValue": "100000",
2708 "UMask": "0x1"
2709 },
2710 {
2711 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
2712 "Counter": "2",
2713 "EventCode": "0xB7",
2714 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2715 "MSRIndex": "0x1A6",
2716 "MSRValue": "0x110",
2717 "Offcore": "1",
2718 "SampleAfterValue": "100000",
2719 "UMask": "0x1"
2720 },
2721 {
2722 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
2723 "Counter": "2",
2724 "EventCode": "0xB7",
2725 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2726 "MSRIndex": "0x1A6",
2727 "MSRValue": "0x210",
2728 "Offcore": "1",
2729 "SampleAfterValue": "100000",
2730 "UMask": "0x1"
2731 },
2732 {
2733 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
2734 "Counter": "2",
2735 "EventCode": "0xB7",
2736 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2737 "MSRIndex": "0x1A6",
2738 "MSRValue": "0x410",
2739 "Offcore": "1",
2740 "SampleAfterValue": "100000",
2741 "UMask": "0x1"
2742 },
2743 {
2744 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
2745 "Counter": "2",
2746 "EventCode": "0xB7",
2747 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2748 "MSRIndex": "0x1A6",
2749 "MSRValue": "0x710",
2750 "Offcore": "1",
2751 "SampleAfterValue": "100000",
2752 "UMask": "0x1"
2753 },
2754 {
2755 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
2756 "Counter": "2",
2757 "EventCode": "0xB7",
2758 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
2759 "MSRIndex": "0x1A6",
2760 "MSRValue": "0x4710",
2761 "Offcore": "1",
2762 "SampleAfterValue": "100000",
2763 "UMask": "0x1"
2764 },
2765 {
2766 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
2767 "Counter": "2",
2768 "EventCode": "0xB7",
2769 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
2770 "MSRIndex": "0x1A6",
2771 "MSRValue": "0x1810",
2772 "Offcore": "1",
2773 "SampleAfterValue": "100000",
2774 "UMask": "0x1"
2775 },
2776 {
2777 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
2778 "Counter": "2",
2779 "EventCode": "0xB7",
2780 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
2781 "MSRIndex": "0x1A6",
2782 "MSRValue": "0x3810",
2783 "Offcore": "1",
2784 "SampleAfterValue": "100000",
2785 "UMask": "0x1"
2786 },
2787 {
2788 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
2789 "Counter": "2",
2790 "EventCode": "0xB7",
2791 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
2792 "MSRIndex": "0x1A6",
2793 "MSRValue": "0x1010",
2794 "Offcore": "1",
2795 "SampleAfterValue": "100000",
2796 "UMask": "0x1"
2797 },
2798 {
2799 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
2800 "Counter": "2",
2801 "EventCode": "0xB7",
2802 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2803 "MSRIndex": "0x1A6",
2804 "MSRValue": "0x810",
2805 "Offcore": "1",
2806 "SampleAfterValue": "100000",
2807 "UMask": "0x1"
2808 },
2809 {
2810 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
2811 "Counter": "2",
2812 "EventCode": "0xB7",
2813 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2814 "MSRIndex": "0x1A6",
2815 "MSRValue": "0x7F40",
2816 "Offcore": "1",
2817 "SampleAfterValue": "100000",
2818 "UMask": "0x1"
2819 },
2820 {
2821 "BriefDescription": "All offcore prefetch code reads",
2822 "Counter": "2",
2823 "EventCode": "0xB7",
2824 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2825 "MSRIndex": "0x1A6",
2826 "MSRValue": "0xFF40",
2827 "Offcore": "1",
2828 "SampleAfterValue": "100000",
2829 "UMask": "0x1"
2830 },
2831 {
2832 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
2833 "Counter": "2",
2834 "EventCode": "0xB7",
2835 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2836 "MSRIndex": "0x1A6",
2837 "MSRValue": "0x8040",
2838 "Offcore": "1",
2839 "SampleAfterValue": "100000",
2840 "UMask": "0x1"
2841 },
2842 {
2843 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
2844 "Counter": "2",
2845 "EventCode": "0xB7",
2846 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2847 "MSRIndex": "0x1A6",
2848 "MSRValue": "0x140",
2849 "Offcore": "1",
2850 "SampleAfterValue": "100000",
2851 "UMask": "0x1"
2852 },
2853 {
2854 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
2855 "Counter": "2",
2856 "EventCode": "0xB7",
2857 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2858 "MSRIndex": "0x1A6",
2859 "MSRValue": "0x240",
2860 "Offcore": "1",
2861 "SampleAfterValue": "100000",
2862 "UMask": "0x1"
2863 },
2864 {
2865 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
2866 "Counter": "2",
2867 "EventCode": "0xB7",
2868 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2869 "MSRIndex": "0x1A6",
2870 "MSRValue": "0x440",
2871 "Offcore": "1",
2872 "SampleAfterValue": "100000",
2873 "UMask": "0x1"
2874 },
2875 {
2876 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
2877 "Counter": "2",
2878 "EventCode": "0xB7",
2879 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2880 "MSRIndex": "0x1A6",
2881 "MSRValue": "0x740",
2882 "Offcore": "1",
2883 "SampleAfterValue": "100000",
2884 "UMask": "0x1"
2885 },
2886 {
2887 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
2888 "Counter": "2",
2889 "EventCode": "0xB7",
2890 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
2891 "MSRIndex": "0x1A6",
2892 "MSRValue": "0x4740",
2893 "Offcore": "1",
2894 "SampleAfterValue": "100000",
2895 "UMask": "0x1"
2896 },
2897 {
2898 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
2899 "Counter": "2",
2900 "EventCode": "0xB7",
2901 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
2902 "MSRIndex": "0x1A6",
2903 "MSRValue": "0x1840",
2904 "Offcore": "1",
2905 "SampleAfterValue": "100000",
2906 "UMask": "0x1"
2907 },
2908 {
2909 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
2910 "Counter": "2",
2911 "EventCode": "0xB7",
2912 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
2913 "MSRIndex": "0x1A6",
2914 "MSRValue": "0x3840",
2915 "Offcore": "1",
2916 "SampleAfterValue": "100000",
2917 "UMask": "0x1"
2918 },
2919 {
2920 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
2921 "Counter": "2",
2922 "EventCode": "0xB7",
2923 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
2924 "MSRIndex": "0x1A6",
2925 "MSRValue": "0x1040",
2926 "Offcore": "1",
2927 "SampleAfterValue": "100000",
2928 "UMask": "0x1"
2929 },
2930 {
2931 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
2932 "Counter": "2",
2933 "EventCode": "0xB7",
2934 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2935 "MSRIndex": "0x1A6",
2936 "MSRValue": "0x840",
2937 "Offcore": "1",
2938 "SampleAfterValue": "100000",
2939 "UMask": "0x1"
2940 },
2941 {
2942 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
2943 "Counter": "2",
2944 "EventCode": "0xB7",
2945 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2946 "MSRIndex": "0x1A6",
2947 "MSRValue": "0x7F20",
2948 "Offcore": "1",
2949 "SampleAfterValue": "100000",
2950 "UMask": "0x1"
2951 },
2952 {
2953 "BriefDescription": "All offcore prefetch RFO requests",
2954 "Counter": "2",
2955 "EventCode": "0xB7",
2956 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2957 "MSRIndex": "0x1A6",
2958 "MSRValue": "0xFF20",
2959 "Offcore": "1",
2960 "SampleAfterValue": "100000",
2961 "UMask": "0x1"
2962 },
2963 {
2964 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
2965 "Counter": "2",
2966 "EventCode": "0xB7",
2967 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2968 "MSRIndex": "0x1A6",
2969 "MSRValue": "0x8020",
2970 "Offcore": "1",
2971 "SampleAfterValue": "100000",
2972 "UMask": "0x1"
2973 },
2974 {
2975 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
2976 "Counter": "2",
2977 "EventCode": "0xB7",
2978 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2979 "MSRIndex": "0x1A6",
2980 "MSRValue": "0x120",
2981 "Offcore": "1",
2982 "SampleAfterValue": "100000",
2983 "UMask": "0x1"
2984 },
2985 {
2986 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
2987 "Counter": "2",
2988 "EventCode": "0xB7",
2989 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2990 "MSRIndex": "0x1A6",
2991 "MSRValue": "0x220",
2992 "Offcore": "1",
2993 "SampleAfterValue": "100000",
2994 "UMask": "0x1"
2995 },
2996 {
2997 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
2998 "Counter": "2",
2999 "EventCode": "0xB7",
3000 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
3001 "MSRIndex": "0x1A6",
3002 "MSRValue": "0x420",
3003 "Offcore": "1",
3004 "SampleAfterValue": "100000",
3005 "UMask": "0x1"
3006 },
3007 {
3008 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
3009 "Counter": "2",
3010 "EventCode": "0xB7",
3011 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
3012 "MSRIndex": "0x1A6",
3013 "MSRValue": "0x720",
3014 "Offcore": "1",
3015 "SampleAfterValue": "100000",
3016 "UMask": "0x1"
3017 },
3018 {
3019 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
3020 "Counter": "2",
3021 "EventCode": "0xB7",
3022 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
3023 "MSRIndex": "0x1A6",
3024 "MSRValue": "0x4720",
3025 "Offcore": "1",
3026 "SampleAfterValue": "100000",
3027 "UMask": "0x1"
3028 },
3029 {
3030 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
3031 "Counter": "2",
3032 "EventCode": "0xB7",
3033 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
3034 "MSRIndex": "0x1A6",
3035 "MSRValue": "0x1820",
3036 "Offcore": "1",
3037 "SampleAfterValue": "100000",
3038 "UMask": "0x1"
3039 },
3040 {
3041 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
3042 "Counter": "2",
3043 "EventCode": "0xB7",
3044 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
3045 "MSRIndex": "0x1A6",
3046 "MSRValue": "0x3820",
3047 "Offcore": "1",
3048 "SampleAfterValue": "100000",
3049 "UMask": "0x1"
3050 },
3051 {
3052 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
3053 "Counter": "2",
3054 "EventCode": "0xB7",
3055 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
3056 "MSRIndex": "0x1A6",
3057 "MSRValue": "0x1020",
3058 "Offcore": "1",
3059 "SampleAfterValue": "100000",
3060 "UMask": "0x1"
3061 },
3062 {
3063 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
3064 "Counter": "2",
3065 "EventCode": "0xB7",
3066 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
3067 "MSRIndex": "0x1A6",
3068 "MSRValue": "0x820",
3069 "Offcore": "1",
3070 "SampleAfterValue": "100000",
3071 "UMask": "0x1"
3072 },
3073 {
3074 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
3075 "Counter": "2",
3076 "EventCode": "0xB7",
3077 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
3078 "MSRIndex": "0x1A6",
3079 "MSRValue": "0x7F70",
3080 "Offcore": "1",
3081 "SampleAfterValue": "100000",
3082 "UMask": "0x1"
3083 },
3084 {
3085 "BriefDescription": "All offcore prefetch requests",
3086 "Counter": "2",
3087 "EventCode": "0xB7",
3088 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
3089 "MSRIndex": "0x1A6",
3090 "MSRValue": "0xFF70",
3091 "Offcore": "1",
3092 "SampleAfterValue": "100000",
3093 "UMask": "0x1"
3094 },
3095 {
3096 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
3097 "Counter": "2",
3098 "EventCode": "0xB7",
3099 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
3100 "MSRIndex": "0x1A6",
3101 "MSRValue": "0x8070",
3102 "Offcore": "1",
3103 "SampleAfterValue": "100000",
3104 "UMask": "0x1"
3105 },
3106 {
3107 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
3108 "Counter": "2",
3109 "EventCode": "0xB7",
3110 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
3111 "MSRIndex": "0x1A6",
3112 "MSRValue": "0x170",
3113 "Offcore": "1",
3114 "SampleAfterValue": "100000",
3115 "UMask": "0x1"
3116 },
3117 {
3118 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
3119 "Counter": "2",
3120 "EventCode": "0xB7",
3121 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
3122 "MSRIndex": "0x1A6",
3123 "MSRValue": "0x270",
3124 "Offcore": "1",
3125 "SampleAfterValue": "100000",
3126 "UMask": "0x1"
3127 },
3128 {
3129 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
3130 "Counter": "2",
3131 "EventCode": "0xB7",
3132 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
3133 "MSRIndex": "0x1A6",
3134 "MSRValue": "0x470",
3135 "Offcore": "1",
3136 "SampleAfterValue": "100000",
3137 "UMask": "0x1"
3138 },
3139 {
3140 "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
3141 "Counter": "2",
3142 "EventCode": "0xB7",
3143 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
3144 "MSRIndex": "0x1A6",
3145 "MSRValue": "0x770",
3146 "Offcore": "1",
3147 "SampleAfterValue": "100000",
3148 "UMask": "0x1"
3149 },
3150 {
3151 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
3152 "Counter": "2",
3153 "EventCode": "0xB7",
3154 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
3155 "MSRIndex": "0x1A6",
3156 "MSRValue": "0x4770",
3157 "Offcore": "1",
3158 "SampleAfterValue": "100000",
3159 "UMask": "0x1"
3160 },
3161 {
3162 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
3163 "Counter": "2",
3164 "EventCode": "0xB7",
3165 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
3166 "MSRIndex": "0x1A6",
3167 "MSRValue": "0x1870",
3168 "Offcore": "1",
3169 "SampleAfterValue": "100000",
3170 "UMask": "0x1"
3171 },
3172 {
3173 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
3174 "Counter": "2",
3175 "EventCode": "0xB7",
3176 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
3177 "MSRIndex": "0x1A6",
3178 "MSRValue": "0x3870",
3179 "Offcore": "1",
3180 "SampleAfterValue": "100000",
3181 "UMask": "0x1"
3182 },
3183 {
3184 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
3185 "Counter": "2",
3186 "EventCode": "0xB7",
3187 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
3188 "MSRIndex": "0x1A6",
3189 "MSRValue": "0x1070",
3190 "Offcore": "1",
3191 "SampleAfterValue": "100000",
3192 "UMask": "0x1"
3193 },
3194 {
3195 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
3196 "Counter": "2",
3197 "EventCode": "0xB7",
3198 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
3199 "MSRIndex": "0x1A6",
3200 "MSRValue": "0x870",
3201 "Offcore": "1",
3202 "SampleAfterValue": "100000",
3203 "UMask": "0x1"
3204 },
3205 {
3206 "BriefDescription": "Super Queue lock splits across a cache line",
3207 "Counter": "0,1,2,3",
3208 "EventCode": "0xF4",
3209 "EventName": "SQ_MISC.SPLIT_LOCK",
3210 "SampleAfterValue": "2000000",
3211 "UMask": "0x10"
3212 },
3213 {
3214 "BriefDescription": "Loads delayed with at-Retirement block code",
3215 "Counter": "0,1,2,3",
3216 "EventCode": "0x6",
3217 "EventName": "STORE_BLOCKS.AT_RET",
3218 "SampleAfterValue": "200000",
3219 "UMask": "0x4"
3220 },
3221 {
3222 "BriefDescription": "Cacheable loads delayed with L1D block code",
3223 "Counter": "0,1,2,3",
3224 "EventCode": "0x6",
3225 "EventName": "STORE_BLOCKS.L1D_BLOCK",
3226 "SampleAfterValue": "200000",
3227 "UMask": "0x8"
3228 }
3229 ]
