0001 [
0002 {
0003 "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x85",
0007 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0008 "PEBScounters": "0,1,2,3,4,5,6,7",
0009 "SampleAfterValue": "200003",
0010 "UMask": "0xe",
0011 "Unit": "cpu_atom"
0012 },
0013 {
0014 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3",
0017 "EventCode": "0x12",
0018 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0019 "PEBScounters": "0,1,2,3",
0020 "SampleAfterValue": "100003",
0021 "UMask": "0xe",
0022 "Unit": "cpu_core"
0023 },
0024 {
0025 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "0,1,2,3",
0028 "EventCode": "0x13",
0029 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
0030 "PEBScounters": "0,1,2,3",
0031 "SampleAfterValue": "100003",
0032 "UMask": "0xe",
0033 "Unit": "cpu_core"
0034 },
0035 {
0036 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
0037 "CollectPEBSRecord": "2",
0038 "Counter": "0,1,2,3",
0039 "EventCode": "0x11",
0040 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0041 "PEBScounters": "0,1,2,3",
0042 "SampleAfterValue": "100003",
0043 "UMask": "0xe",
0044 "Unit": "cpu_core"
0045 }
0046 ]
