0001 [
0002 {
0003 "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xc4",
0007 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
0008 "PEBS": "1",
0009 "PEBScounters": "0,1,2,3,4,5,6,7",
0010 "SampleAfterValue": "200003",
0011 "Unit": "cpu_atom"
0012 },
0013 {
0014 "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0xc5",
0018 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
0019 "PEBS": "1",
0020 "PEBScounters": "0,1,2,3,4,5,6,7",
0021 "SampleAfterValue": "200003",
0022 "Unit": "cpu_atom"
0023 },
0024 {
0025 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "33",
0028 "EventName": "CPU_CLK_UNHALTED.CORE",
0029 "PEBScounters": "33",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x2",
0032 "Unit": "cpu_atom"
0033 },
0034 {
0035 "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
0036 "CollectPEBSRecord": "2",
0037 "Counter": "0,1,2,3,4,5,6,7",
0038 "EventCode": "0x3c",
0039 "EventName": "CPU_CLK_UNHALTED.CORE_P",
0040 "PEBScounters": "0,1,2,3,4,5,6,7",
0041 "SampleAfterValue": "2000003",
0042 "Unit": "cpu_atom"
0043 },
0044 {
0045 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
0046 "CollectPEBSRecord": "2",
0047 "Counter": "34",
0048 "EventName": "CPU_CLK_UNHALTED.REF_TSC",
0049 "PEBScounters": "34",
0050 "SampleAfterValue": "2000003",
0051 "UMask": "0x3",
0052 "Unit": "cpu_atom"
0053 },
0054 {
0055 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
0056 "CollectPEBSRecord": "2",
0057 "Counter": "33",
0058 "EventName": "CPU_CLK_UNHALTED.THREAD",
0059 "PEBScounters": "33",
0060 "SampleAfterValue": "2000003",
0061 "UMask": "0x2",
0062 "Unit": "cpu_atom"
0063 },
0064 {
0065 "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
0066 "CollectPEBSRecord": "2",
0067 "Counter": "0,1,2,3,4,5,6,7",
0068 "EventCode": "0x3c",
0069 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
0070 "PEBScounters": "0,1,2,3,4,5,6,7",
0071 "SampleAfterValue": "2000003",
0072 "Unit": "cpu_atom"
0073 },
0074 {
0075 "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
0076 "CollectPEBSRecord": "2",
0077 "Counter": "32",
0078 "EventName": "INST_RETIRED.ANY",
0079 "PEBS": "1",
0080 "PEBScounters": "32",
0081 "SampleAfterValue": "2000003",
0082 "UMask": "0x1",
0083 "Unit": "cpu_atom"
0084 },
0085 {
0086 "BriefDescription": "Counts the number of instructions retired",
0087 "CollectPEBSRecord": "2",
0088 "Counter": "0,1,2,3,4,5,6,7",
0089 "EventCode": "0xc0",
0090 "EventName": "INST_RETIRED.ANY_P",
0091 "PEBS": "1",
0092 "PEBScounters": "0,1,2,3,4,5,6,7",
0093 "SampleAfterValue": "2000003",
0094 "Unit": "cpu_atom"
0095 },
0096 {
0097 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
0098 "CollectPEBSRecord": "2",
0099 "Counter": "0,1,2,3,4,5,6,7",
0100 "EventCode": "0x73",
0101 "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
0102 "PEBScounters": "0,1,2,3,4,5,6,7",
0103 "SampleAfterValue": "1000003",
0104 "Unit": "cpu_atom"
0105 },
0106 {
0107 "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
0108 "CollectPEBSRecord": "2",
0109 "Counter": "0,1,2,3,4,5,6,7",
0110 "EventCode": "0x74",
0111 "EventName": "TOPDOWN_BE_BOUND.ALL",
0112 "PEBScounters": "0,1,2,3,4,5,6,7",
0113 "SampleAfterValue": "1000003",
0114 "Unit": "cpu_atom"
0115 },
0116 {
0117 "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
0118 "CollectPEBSRecord": "2",
0119 "Counter": "0,1,2,3,4,5,6,7",
0120 "EventCode": "0x71",
0121 "EventName": "TOPDOWN_FE_BOUND.ALL",
0122 "PEBScounters": "0,1,2,3,4,5,6,7",
0123 "SampleAfterValue": "1000003",
0124 "Unit": "cpu_atom"
0125 },
0126 {
0127 "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
0128 "CollectPEBSRecord": "2",
0129 "Counter": "0,1,2,3,4,5,6,7",
0130 "EventCode": "0x72",
0131 "EventName": "TOPDOWN_RETIRING.ALL",
0132 "PEBS": "1",
0133 "PEBScounters": "0,1,2,3,4,5,6,7",
0134 "SampleAfterValue": "1000003",
0135 "Unit": "cpu_atom"
0136 },
0137 {
0138 "BriefDescription": "All branch instructions retired.",
0139 "CollectPEBSRecord": "2",
0140 "Counter": "0,1,2,3,4,5,6,7",
0141 "EventCode": "0xc4",
0142 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
0143 "PEBS": "1",
0144 "PEBScounters": "0,1,2,3,4,5,6,7",
0145 "SampleAfterValue": "400009",
0146 "Unit": "cpu_core"
0147 },
0148 {
0149 "BriefDescription": "All mispredicted branch instructions retired.",
0150 "CollectPEBSRecord": "2",
0151 "Counter": "0,1,2,3,4,5,6,7",
0152 "EventCode": "0xc5",
0153 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
0154 "PEBS": "1",
0155 "PEBScounters": "0,1,2,3,4,5,6,7",
0156 "SampleAfterValue": "400009",
0157 "Unit": "cpu_core"
0158 },
0159 {
0160 "BriefDescription": "Reference cycles when the core is not in halt state.",
0161 "CollectPEBSRecord": "2",
0162 "Counter": "34",
0163 "EventName": "CPU_CLK_UNHALTED.REF_TSC",
0164 "PEBScounters": "34",
0165 "SampleAfterValue": "2000003",
0166 "UMask": "0x3",
0167 "Unit": "cpu_core"
0168 },
0169 {
0170 "BriefDescription": "Reference cycles when the core is not in halt state.",
0171 "CollectPEBSRecord": "2",
0172 "Counter": "0,1,2,3,4,5,6,7",
0173 "EventCode": "0x3c",
0174 "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
0175 "PEBScounters": "0,1,2,3,4,5,6,7",
0176 "SampleAfterValue": "2000003",
0177 "UMask": "0x1",
0178 "Unit": "cpu_core"
0179 },
0180 {
0181 "BriefDescription": "Core cycles when the thread is not in halt state",
0182 "CollectPEBSRecord": "2",
0183 "Counter": "33",
0184 "EventName": "CPU_CLK_UNHALTED.THREAD",
0185 "PEBScounters": "33",
0186 "SampleAfterValue": "2000003",
0187 "UMask": "0x2",
0188 "Unit": "cpu_core"
0189 },
0190 {
0191 "BriefDescription": "Thread cycles when thread is not in halt state",
0192 "CollectPEBSRecord": "2",
0193 "Counter": "0,1,2,3,4,5,6,7",
0194 "EventCode": "0x3c",
0195 "EventName": "CPU_CLK_UNHALTED.THREAD_P",
0196 "PEBScounters": "0,1,2,3,4,5,6,7",
0197 "SampleAfterValue": "2000003",
0198 "Unit": "cpu_core"
0199 },
0200 {
0201 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
0202 "CollectPEBSRecord": "2",
0203 "Counter": "32",
0204 "EventName": "INST_RETIRED.ANY",
0205 "PEBS": "1",
0206 "PEBScounters": "32",
0207 "SampleAfterValue": "2000003",
0208 "UMask": "0x1",
0209 "Unit": "cpu_core"
0210 },
0211 {
0212 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
0213 "CollectPEBSRecord": "2",
0214 "Counter": "0,1,2,3,4,5,6,7",
0215 "EventCode": "0xc0",
0216 "EventName": "INST_RETIRED.ANY_P",
0217 "PEBS": "1",
0218 "PEBScounters": "1,2,3,4,5,6,7",
0219 "SampleAfterValue": "2000003",
0220 "Unit": "cpu_core"
0221 },
0222 {
0223 "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
0224 "CollectPEBSRecord": "2",
0225 "Counter": "0,1,2,3",
0226 "EventCode": "0x03",
0227 "EventName": "LD_BLOCKS.STORE_FORWARD",
0228 "PEBScounters": "0,1,2,3",
0229 "SampleAfterValue": "100003",
0230 "UMask": "0x82",
0231 "Unit": "cpu_core"
0232 },
0233 {
0234 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
0235 "CollectPEBSRecord": "2",
0236 "Counter": "35",
0237 "EventName": "TOPDOWN.SLOTS",
0238 "PEBScounters": "35",
0239 "SampleAfterValue": "10000003",
0240 "UMask": "0x4",
0241 "Unit": "cpu_core"
0242 },
0243 {
0244 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
0245 "CollectPEBSRecord": "2",
0246 "Counter": "0,1,2,3,4,5,6,7",
0247 "EventCode": "0xa4",
0248 "EventName": "TOPDOWN.SLOTS_P",
0249 "PEBScounters": "0,1,2,3,4,5,6,7",
0250 "SampleAfterValue": "10000003",
0251 "UMask": "0x1",
0252 "Unit": "cpu_core"
0253 }
0254 ]
