0001 [
0002 {
0003 "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
0004 "Counter": "0,1,2,3,4,5,6,7",
0005 "EventCode": "0xB7",
0006 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
0007 "MSRIndex": "0x1a6,0x1a7",
0008 "MSRValue": "0x3FBFC00001",
0009 "SampleAfterValue": "100003",
0010 "UMask": "0x1",
0011 "Unit": "cpu_atom"
0012 },
0013 {
0014 "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
0015 "Counter": "0,1,2,3,4,5,6,7",
0016 "EventCode": "0xB7",
0017 "EventName": "OCR.DEMAND_RFO.L3_MISS",
0018 "MSRIndex": "0x1a6,0x1a7",
0019 "MSRValue": "0x3FBFC00002",
0020 "SampleAfterValue": "100003",
0021 "UMask": "0x1",
0022 "Unit": "cpu_atom"
0023 },
0024 {
0025 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "1,2,3,4,5,6,7",
0028 "Data_LA": "1",
0029 "EventCode": "0xcd",
0030 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0031 "MSRIndex": "0x3F6",
0032 "MSRValue": "0x80",
0033 "PEBS": "2",
0034 "PEBScounters": "1,2,3,4,5,6,7",
0035 "SampleAfterValue": "1009",
0036 "TakenAlone": "1",
0037 "UMask": "0x1",
0038 "Unit": "cpu_core"
0039 },
0040 {
0041 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
0042 "CollectPEBSRecord": "2",
0043 "Counter": "1,2,3,4,5,6,7",
0044 "Data_LA": "1",
0045 "EventCode": "0xcd",
0046 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0047 "MSRIndex": "0x3F6",
0048 "MSRValue": "0x10",
0049 "PEBS": "2",
0050 "PEBScounters": "1,2,3,4,5,6,7",
0051 "SampleAfterValue": "20011",
0052 "TakenAlone": "1",
0053 "UMask": "0x1",
0054 "Unit": "cpu_core"
0055 },
0056 {
0057 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
0058 "CollectPEBSRecord": "2",
0059 "Counter": "1,2,3,4,5,6,7",
0060 "Data_LA": "1",
0061 "EventCode": "0xcd",
0062 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0063 "MSRIndex": "0x3F6",
0064 "MSRValue": "0x100",
0065 "PEBS": "2",
0066 "PEBScounters": "1,2,3,4,5,6,7",
0067 "SampleAfterValue": "503",
0068 "TakenAlone": "1",
0069 "UMask": "0x1",
0070 "Unit": "cpu_core"
0071 },
0072 {
0073 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
0074 "CollectPEBSRecord": "2",
0075 "Counter": "1,2,3,4,5,6,7",
0076 "Data_LA": "1",
0077 "EventCode": "0xcd",
0078 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0079 "MSRIndex": "0x3F6",
0080 "MSRValue": "0x20",
0081 "PEBS": "2",
0082 "PEBScounters": "1,2,3,4,5,6,7",
0083 "SampleAfterValue": "100007",
0084 "TakenAlone": "1",
0085 "UMask": "0x1",
0086 "Unit": "cpu_core"
0087 },
0088 {
0089 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
0090 "CollectPEBSRecord": "2",
0091 "Counter": "1,2,3,4,5,6,7",
0092 "Data_LA": "1",
0093 "EventCode": "0xcd",
0094 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0095 "MSRIndex": "0x3F6",
0096 "MSRValue": "0x4",
0097 "PEBS": "2",
0098 "PEBScounters": "1,2,3,4,5,6,7",
0099 "SampleAfterValue": "100003",
0100 "TakenAlone": "1",
0101 "UMask": "0x1",
0102 "Unit": "cpu_core"
0103 },
0104 {
0105 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
0106 "CollectPEBSRecord": "2",
0107 "Counter": "1,2,3,4,5,6,7",
0108 "Data_LA": "1",
0109 "EventCode": "0xcd",
0110 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0111 "MSRIndex": "0x3F6",
0112 "MSRValue": "0x200",
0113 "PEBS": "2",
0114 "PEBScounters": "1,2,3,4,5,6,7",
0115 "SampleAfterValue": "101",
0116 "TakenAlone": "1",
0117 "UMask": "0x1",
0118 "Unit": "cpu_core"
0119 },
0120 {
0121 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
0122 "CollectPEBSRecord": "2",
0123 "Counter": "1,2,3,4,5,6,7",
0124 "Data_LA": "1",
0125 "EventCode": "0xcd",
0126 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0127 "MSRIndex": "0x3F6",
0128 "MSRValue": "0x40",
0129 "PEBS": "2",
0130 "PEBScounters": "1,2,3,4,5,6,7",
0131 "SampleAfterValue": "2003",
0132 "TakenAlone": "1",
0133 "UMask": "0x1",
0134 "Unit": "cpu_core"
0135 },
0136 {
0137 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
0138 "CollectPEBSRecord": "2",
0139 "Counter": "1,2,3,4,5,6,7",
0140 "Data_LA": "1",
0141 "EventCode": "0xcd",
0142 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0143 "MSRIndex": "0x3F6",
0144 "MSRValue": "0x8",
0145 "PEBS": "2",
0146 "PEBScounters": "1,2,3,4,5,6,7",
0147 "SampleAfterValue": "50021",
0148 "TakenAlone": "1",
0149 "UMask": "0x1",
0150 "Unit": "cpu_core"
0151 },
0152 {
0153 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
0154 "CollectPEBSRecord": "2",
0155 "Data_LA": "1",
0156 "EventCode": "0xcd",
0157 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
0158 "PEBS": "2",
0159 "SampleAfterValue": "1000003",
0160 "UMask": "0x2",
0161 "Unit": "cpu_core"
0162 },
0163 {
0164 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
0165 "Counter": "0,1,2,3,4,5,6,7",
0166 "EventCode": "0x2A,0x2B",
0167 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
0168 "MSRIndex": "0x1a6,0x1a7",
0169 "MSRValue": "0x3FBFC00001",
0170 "SampleAfterValue": "100003",
0171 "UMask": "0x1",
0172 "Unit": "cpu_core"
0173 },
0174 {
0175 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
0176 "Counter": "0,1,2,3,4,5,6,7",
0177 "EventCode": "0x2A,0x2B",
0178 "EventName": "OCR.DEMAND_RFO.L3_MISS",
0179 "MSRIndex": "0x1a6,0x1a7",
0180 "MSRValue": "0x3FBFC00002",
0181 "SampleAfterValue": "100003",
0182 "UMask": "0x1",
0183 "Unit": "cpu_core"
0184 }
0185 ]
