0001 [
0002 {
0003 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x2e",
0007 "EventName": "LONGEST_LAT_CACHE.MISS",
0008 "PEBScounters": "0,1,2,3,4,5,6,7",
0009 "SampleAfterValue": "200003",
0010 "UMask": "0x41",
0011 "Unit": "cpu_atom"
0012 },
0013 {
0014 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0x2e",
0018 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0019 "PEBScounters": "0,1,2,3,4,5,6,7",
0020 "SampleAfterValue": "200003",
0021 "UMask": "0x4f",
0022 "Unit": "cpu_atom"
0023 },
0024 {
0025 "BriefDescription": "Counts the number of load ops retired.",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "0,1,2,3,4,5,6,7",
0028 "Data_LA": "1",
0029 "EventCode": "0xd0",
0030 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
0031 "PEBS": "1",
0032 "PEBScounters": "0,1,2,3,4,5,6,7",
0033 "SampleAfterValue": "200003",
0034 "UMask": "0x81",
0035 "Unit": "cpu_atom"
0036 },
0037 {
0038 "BriefDescription": "Counts the number of store ops retired.",
0039 "CollectPEBSRecord": "2",
0040 "Counter": "0,1,2,3,4,5,6,7",
0041 "Data_LA": "1",
0042 "EventCode": "0xd0",
0043 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
0044 "PEBS": "1",
0045 "PEBScounters": "0,1,2,3,4,5,6,7",
0046 "SampleAfterValue": "200003",
0047 "UMask": "0x82",
0048 "Unit": "cpu_atom"
0049 },
0050 {
0051 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0052 "CollectPEBSRecord": "3",
0053 "Counter": "0,1,2,3,4,5,6,7",
0054 "Data_LA": "1",
0055 "EventCode": "0xd0",
0056 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
0057 "MSRIndex": "0x3F6",
0058 "MSRValue": "0x80",
0059 "PEBS": "2",
0060 "PEBScounters": "0,1,2,3,4,5,6,7",
0061 "SampleAfterValue": "1000003",
0062 "TakenAlone": "1",
0063 "UMask": "0x5",
0064 "Unit": "cpu_atom"
0065 },
0066 {
0067 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0068 "CollectPEBSRecord": "3",
0069 "Counter": "0,1,2,3,4,5,6,7",
0070 "Data_LA": "1",
0071 "EventCode": "0xd0",
0072 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
0073 "MSRIndex": "0x3F6",
0074 "MSRValue": "0x10",
0075 "PEBS": "2",
0076 "PEBScounters": "0,1,2,3,4,5,6,7",
0077 "SampleAfterValue": "1000003",
0078 "TakenAlone": "1",
0079 "UMask": "0x5",
0080 "Unit": "cpu_atom"
0081 },
0082 {
0083 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0084 "CollectPEBSRecord": "3",
0085 "Counter": "0,1,2,3,4,5,6,7",
0086 "Data_LA": "1",
0087 "EventCode": "0xd0",
0088 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
0089 "MSRIndex": "0x3F6",
0090 "MSRValue": "0x100",
0091 "PEBS": "2",
0092 "PEBScounters": "0,1,2,3,4,5,6,7",
0093 "SampleAfterValue": "1000003",
0094 "TakenAlone": "1",
0095 "UMask": "0x5",
0096 "Unit": "cpu_atom"
0097 },
0098 {
0099 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0100 "CollectPEBSRecord": "3",
0101 "Counter": "0,1,2,3,4,5,6,7",
0102 "Data_LA": "1",
0103 "EventCode": "0xd0",
0104 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
0105 "MSRIndex": "0x3F6",
0106 "MSRValue": "0x20",
0107 "PEBS": "2",
0108 "PEBScounters": "0,1,2,3,4,5,6,7",
0109 "SampleAfterValue": "1000003",
0110 "TakenAlone": "1",
0111 "UMask": "0x5",
0112 "Unit": "cpu_atom"
0113 },
0114 {
0115 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0116 "CollectPEBSRecord": "3",
0117 "Counter": "0,1,2,3,4,5,6,7",
0118 "Data_LA": "1",
0119 "EventCode": "0xd0",
0120 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
0121 "MSRIndex": "0x3F6",
0122 "MSRValue": "0x4",
0123 "PEBS": "2",
0124 "PEBScounters": "0,1,2,3,4,5,6,7",
0125 "SampleAfterValue": "1000003",
0126 "TakenAlone": "1",
0127 "UMask": "0x5",
0128 "Unit": "cpu_atom"
0129 },
0130 {
0131 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0132 "CollectPEBSRecord": "3",
0133 "Counter": "0,1,2,3,4,5,6,7",
0134 "Data_LA": "1",
0135 "EventCode": "0xd0",
0136 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
0137 "MSRIndex": "0x3F6",
0138 "MSRValue": "0x200",
0139 "PEBS": "2",
0140 "PEBScounters": "0,1,2,3,4,5,6,7",
0141 "SampleAfterValue": "1000003",
0142 "TakenAlone": "1",
0143 "UMask": "0x5",
0144 "Unit": "cpu_atom"
0145 },
0146 {
0147 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0148 "CollectPEBSRecord": "3",
0149 "Counter": "0,1,2,3,4,5,6,7",
0150 "Data_LA": "1",
0151 "EventCode": "0xd0",
0152 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
0153 "MSRIndex": "0x3F6",
0154 "MSRValue": "0x40",
0155 "PEBS": "2",
0156 "PEBScounters": "0,1,2,3,4,5,6,7",
0157 "SampleAfterValue": "1000003",
0158 "TakenAlone": "1",
0159 "UMask": "0x5",
0160 "Unit": "cpu_atom"
0161 },
0162 {
0163 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
0164 "CollectPEBSRecord": "3",
0165 "Counter": "0,1,2,3,4,5,6,7",
0166 "Data_LA": "1",
0167 "EventCode": "0xd0",
0168 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
0169 "MSRIndex": "0x3F6",
0170 "MSRValue": "0x8",
0171 "PEBS": "2",
0172 "PEBScounters": "0,1,2,3,4,5,6,7",
0173 "SampleAfterValue": "1000003",
0174 "TakenAlone": "1",
0175 "UMask": "0x5",
0176 "Unit": "cpu_atom"
0177 },
0178 {
0179 "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
0180 "CollectPEBSRecord": "3",
0181 "Counter": "0,1,2,3,4,5,6,7",
0182 "Data_LA": "1",
0183 "EventCode": "0xd0",
0184 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
0185 "PEBS": "2",
0186 "PEBScounters": "0,1,2,3,4,5,6,7",
0187 "SampleAfterValue": "1000003",
0188 "UMask": "0x6",
0189 "Unit": "cpu_atom"
0190 },
0191 {
0192 "BriefDescription": "L2 code requests",
0193 "CollectPEBSRecord": "2",
0194 "Counter": "0,1,2,3",
0195 "EventCode": "0x24",
0196 "EventName": "L2_RQSTS.ALL_CODE_RD",
0197 "PEBScounters": "0,1,2,3",
0198 "SampleAfterValue": "200003",
0199 "UMask": "0xe4",
0200 "Unit": "cpu_core"
0201 },
0202 {
0203 "BriefDescription": "Demand Data Read access L2 cache",
0204 "CollectPEBSRecord": "2",
0205 "Counter": "0,1,2,3",
0206 "EventCode": "0x24",
0207 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
0208 "PEBScounters": "0,1,2,3",
0209 "SampleAfterValue": "200003",
0210 "UMask": "0xe1",
0211 "Unit": "cpu_core"
0212 },
0213 {
0214 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
0215 "CollectPEBSRecord": "2",
0216 "Counter": "0,1,2,3,4,5,6,7",
0217 "EventCode": "0x2e",
0218 "EventName": "LONGEST_LAT_CACHE.MISS",
0219 "PEBScounters": "0,1,2,3,4,5,6,7",
0220 "SampleAfterValue": "100003",
0221 "UMask": "0x41",
0222 "Unit": "cpu_core"
0223 },
0224 {
0225 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
0226 "CollectPEBSRecord": "2",
0227 "Counter": "0,1,2,3,4,5,6,7",
0228 "EventCode": "0x2e",
0229 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0230 "PEBScounters": "0,1,2,3,4,5,6,7",
0231 "SampleAfterValue": "100003",
0232 "UMask": "0x4f",
0233 "Unit": "cpu_core"
0234 },
0235 {
0236 "BriefDescription": "Retired load instructions.",
0237 "CollectPEBSRecord": "2",
0238 "Counter": "0,1,2,3",
0239 "Data_LA": "1",
0240 "EventCode": "0xd0",
0241 "EventName": "MEM_INST_RETIRED.ALL_LOADS",
0242 "PEBS": "1",
0243 "PEBScounters": "0,1,2,3",
0244 "SampleAfterValue": "1000003",
0245 "UMask": "0x81",
0246 "Unit": "cpu_core"
0247 },
0248 {
0249 "BriefDescription": "Retired store instructions.",
0250 "CollectPEBSRecord": "2",
0251 "Counter": "0,1,2,3",
0252 "Data_LA": "1",
0253 "EventCode": "0xd0",
0254 "EventName": "MEM_INST_RETIRED.ALL_STORES",
0255 "L1_Hit_Indication": "1",
0256 "PEBS": "1",
0257 "PEBScounters": "0,1,2,3",
0258 "SampleAfterValue": "1000003",
0259 "UMask": "0x82",
0260 "Unit": "cpu_core"
0261 }
0262 ]
