0001 [
0002 {
0003 "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x5C",
0007 "EventName": "CPL_CYCLES.RING0",
0008 "SampleAfterValue": "2000003",
0009 "UMask": "0x1"
0010 },
0011 {
0012 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
0013 "Counter": "0,1,2,3",
0014 "CounterHTOff": "0,1,2,3,4,5,6,7",
0015 "CounterMask": "1",
0016 "EdgeDetect": "1",
0017 "EventCode": "0x5C",
0018 "EventName": "CPL_CYCLES.RING0_TRANS",
0019 "SampleAfterValue": "100007",
0020 "UMask": "0x1"
0021 },
0022 {
0023 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
0024 "Counter": "0,1,2,3",
0025 "CounterHTOff": "0,1,2,3,4,5,6,7",
0026 "EventCode": "0x5C",
0027 "EventName": "CPL_CYCLES.RING123",
0028 "SampleAfterValue": "2000003",
0029 "UMask": "0x2"
0030 },
0031 {
0032 "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
0033 "Counter": "0,1,2,3",
0034 "CounterHTOff": "0,1,2,3,4,5,6,7",
0035 "EventCode": "0x4E",
0036 "EventName": "HW_PRE_REQ.DL1_MISS",
0037 "SampleAfterValue": "2000003",
0038 "UMask": "0x2"
0039 },
0040 {
0041 "BriefDescription": "Valid instructions written to IQ per cycle.",
0042 "Counter": "0,1,2,3",
0043 "CounterHTOff": "0,1,2,3,4,5,6,7",
0044 "EventCode": "0x17",
0045 "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
0046 "SampleAfterValue": "2000003",
0047 "UMask": "0x1"
0048 },
0049 {
0050 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
0051 "Counter": "0,1,2,3",
0052 "CounterHTOff": "0,1,2,3,4,5,6,7",
0053 "EventCode": "0x63",
0054 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
0055 "SampleAfterValue": "2000003",
0056 "UMask": "0x1"
0057 }
0058 ]
