0001 [
0002 {
0003 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xC3",
0007 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0008 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.",
0009 "SampleAfterValue": "100003",
0010 "UMask": "0x2"
0011 },
0012 {
0013 "BriefDescription": "Loads with latency value being above 128.",
0014 "Counter": "3",
0015 "CounterHTOff": "3",
0016 "EventCode": "0xCD",
0017 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0018 "MSRIndex": "0x3F6",
0019 "MSRValue": "0x80",
0020 "PEBS": "2",
0021 "SampleAfterValue": "1009",
0022 "TakenAlone": "1",
0023 "UMask": "0x1"
0024 },
0025 {
0026 "BriefDescription": "Loads with latency value being above 16.",
0027 "Counter": "3",
0028 "CounterHTOff": "3",
0029 "EventCode": "0xCD",
0030 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0031 "MSRIndex": "0x3F6",
0032 "MSRValue": "0x10",
0033 "PEBS": "2",
0034 "SampleAfterValue": "20011",
0035 "TakenAlone": "1",
0036 "UMask": "0x1"
0037 },
0038 {
0039 "BriefDescription": "Loads with latency value being above 256.",
0040 "Counter": "3",
0041 "CounterHTOff": "3",
0042 "EventCode": "0xCD",
0043 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0044 "MSRIndex": "0x3F6",
0045 "MSRValue": "0x100",
0046 "PEBS": "2",
0047 "SampleAfterValue": "503",
0048 "TakenAlone": "1",
0049 "UMask": "0x1"
0050 },
0051 {
0052 "BriefDescription": "Loads with latency value being above 32.",
0053 "Counter": "3",
0054 "CounterHTOff": "3",
0055 "EventCode": "0xCD",
0056 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0057 "MSRIndex": "0x3F6",
0058 "MSRValue": "0x20",
0059 "PEBS": "2",
0060 "SampleAfterValue": "100007",
0061 "TakenAlone": "1",
0062 "UMask": "0x1"
0063 },
0064 {
0065 "BriefDescription": "Loads with latency value being above 4 .",
0066 "Counter": "3",
0067 "CounterHTOff": "3",
0068 "EventCode": "0xCD",
0069 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0070 "MSRIndex": "0x3F6",
0071 "MSRValue": "0x4",
0072 "PEBS": "2",
0073 "SampleAfterValue": "100003",
0074 "TakenAlone": "1",
0075 "UMask": "0x1"
0076 },
0077 {
0078 "BriefDescription": "Loads with latency value being above 512.",
0079 "Counter": "3",
0080 "CounterHTOff": "3",
0081 "EventCode": "0xCD",
0082 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0083 "MSRIndex": "0x3F6",
0084 "MSRValue": "0x200",
0085 "PEBS": "2",
0086 "SampleAfterValue": "101",
0087 "TakenAlone": "1",
0088 "UMask": "0x1"
0089 },
0090 {
0091 "BriefDescription": "Loads with latency value being above 64.",
0092 "Counter": "3",
0093 "CounterHTOff": "3",
0094 "EventCode": "0xCD",
0095 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0096 "MSRIndex": "0x3F6",
0097 "MSRValue": "0x40",
0098 "PEBS": "2",
0099 "SampleAfterValue": "2003",
0100 "TakenAlone": "1",
0101 "UMask": "0x1"
0102 },
0103 {
0104 "BriefDescription": "Loads with latency value being above 8.",
0105 "Counter": "3",
0106 "CounterHTOff": "3",
0107 "EventCode": "0xCD",
0108 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0109 "MSRIndex": "0x3F6",
0110 "MSRValue": "0x8",
0111 "PEBS": "2",
0112 "SampleAfterValue": "50021",
0113 "TakenAlone": "1",
0114 "UMask": "0x1"
0115 },
0116 {
0117 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
0118 "Counter": "3",
0119 "CounterHTOff": "3",
0120 "EventCode": "0xCD",
0121 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
0122 "PEBS": "2",
0123 "PRECISE_STORE": "1",
0124 "SampleAfterValue": "2000003",
0125 "TakenAlone": "1",
0126 "UMask": "0x2"
0127 },
0128 {
0129 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
0130 "Counter": "0,1,2,3",
0131 "CounterHTOff": "0,1,2,3,4,5,6,7",
0132 "EventCode": "0x05",
0133 "EventName": "MISALIGN_MEM_REF.LOADS",
0134 "SampleAfterValue": "2000003",
0135 "UMask": "0x1"
0136 },
0137 {
0138 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
0139 "Counter": "0,1,2,3",
0140 "CounterHTOff": "0,1,2,3,4,5,6,7",
0141 "EventCode": "0x05",
0142 "EventName": "MISALIGN_MEM_REF.STORES",
0143 "SampleAfterValue": "2000003",
0144 "UMask": "0x2"
0145 },
0146 {
0147 "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
0148 "Counter": "0,1,2,3",
0149 "CounterHTOff": "0,1,2,3",
0150 "EventCode": "0xB7, 0xBB",
0151 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
0152 "MSRIndex": "0x1a6,0x1a7",
0153 "MSRValue": "0x3FFFC20077",
0154 "Offcore": "1",
0155 "SampleAfterValue": "100003",
0156 "UMask": "0x1"
0157 },
0158 {
0159 "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
0160 "Counter": "0,1,2,3",
0161 "CounterHTOff": "0,1,2,3",
0162 "EventCode": "0xB7, 0xBB",
0163 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
0164 "MSRIndex": "0x1a6,0x1a7",
0165 "MSRValue": "0x600400077",
0166 "Offcore": "1",
0167 "SampleAfterValue": "100003",
0168 "UMask": "0x1"
0169 },
0170 {
0171 "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
0172 "Counter": "0,1,2,3",
0173 "CounterHTOff": "0,1,2,3",
0174 "EventCode": "0xB7, 0xBB",
0175 "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
0176 "MSRIndex": "0x1a6,0x1a7",
0177 "MSRValue": "0x187FC20077",
0178 "Offcore": "1",
0179 "SampleAfterValue": "100003",
0180 "UMask": "0x1"
0181 },
0182 {
0183 "BriefDescription": "Counts all demand code reads that miss the LLC",
0184 "Counter": "0,1,2,3",
0185 "CounterHTOff": "0,1,2,3",
0186 "EventCode": "0xB7, 0xBB",
0187 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
0188 "MSRIndex": "0x1a6,0x1a7",
0189 "MSRValue": "0x3fffc20004",
0190 "Offcore": "1",
0191 "SampleAfterValue": "100003",
0192 "UMask": "0x1"
0193 },
0194 {
0195 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
0196 "Counter": "0,1,2,3",
0197 "CounterHTOff": "0,1,2,3",
0198 "EventCode": "0xB7, 0xBB",
0199 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
0200 "MSRIndex": "0x1a6,0x1a7",
0201 "MSRValue": "0x600400004",
0202 "Offcore": "1",
0203 "SampleAfterValue": "100003",
0204 "UMask": "0x1"
0205 },
0206 {
0207 "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
0208 "Counter": "0,1,2,3",
0209 "CounterHTOff": "0,1,2,3",
0210 "EventCode": "0xB7, 0xBB",
0211 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
0212 "MSRIndex": "0x1a6,0x1a7",
0213 "MSRValue": "0x67f800004",
0214 "Offcore": "1",
0215 "SampleAfterValue": "100003",
0216 "UMask": "0x1"
0217 },
0218 {
0219 "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
0220 "Counter": "0,1,2,3",
0221 "CounterHTOff": "0,1,2,3",
0222 "EventCode": "0xB7, 0xBB",
0223 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
0224 "MSRIndex": "0x1a6,0x1a7",
0225 "MSRValue": "0x107fc00004",
0226 "Offcore": "1",
0227 "SampleAfterValue": "100003",
0228 "UMask": "0x1"
0229 },
0230 {
0231 "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
0232 "Counter": "0,1,2,3",
0233 "CounterHTOff": "0,1,2,3",
0234 "EventCode": "0xB7, 0xBB",
0235 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
0236 "MSRIndex": "0x1a6,0x1a7",
0237 "MSRValue": "0x87f820004",
0238 "Offcore": "1",
0239 "SampleAfterValue": "100003",
0240 "UMask": "0x1"
0241 },
0242 {
0243 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
0244 "Counter": "0,1,2,3",
0245 "CounterHTOff": "0,1,2,3",
0246 "EventCode": "0xB7, 0xBB",
0247 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
0248 "MSRIndex": "0x1a6,0x1a7",
0249 "MSRValue": "0x67fc00001",
0250 "Offcore": "1",
0251 "SampleAfterValue": "100003",
0252 "UMask": "0x1"
0253 },
0254 {
0255 "BriefDescription": "Counts demand data reads that miss in the LLC",
0256 "Counter": "0,1,2,3",
0257 "CounterHTOff": "0,1,2,3",
0258 "EventCode": "0xB7, 0xBB",
0259 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
0260 "MSRIndex": "0x1a6,0x1a7",
0261 "MSRValue": "0x3fffc20001",
0262 "Offcore": "1",
0263 "SampleAfterValue": "100003",
0264 "UMask": "0x1"
0265 },
0266 {
0267 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
0268 "Counter": "0,1,2,3",
0269 "CounterHTOff": "0,1,2,3",
0270 "EventCode": "0xB7, 0xBB",
0271 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
0272 "MSRIndex": "0x1a6,0x1a7",
0273 "MSRValue": "0x600400001",
0274 "Offcore": "1",
0275 "SampleAfterValue": "100003",
0276 "UMask": "0x1"
0277 },
0278 {
0279 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
0280 "Counter": "0,1,2,3",
0281 "CounterHTOff": "0,1,2,3",
0282 "EventCode": "0xB7, 0xBB",
0283 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
0284 "MSRIndex": "0x1a6,0x1a7",
0285 "MSRValue": "0x67f800001",
0286 "Offcore": "1",
0287 "SampleAfterValue": "100003",
0288 "UMask": "0x1"
0289 },
0290 {
0291 "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
0292 "Counter": "0,1,2,3",
0293 "CounterHTOff": "0,1,2,3",
0294 "EventCode": "0xB7, 0xBB",
0295 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
0296 "MSRIndex": "0x1a6,0x1a7",
0297 "MSRValue": "0x107fc00001",
0298 "Offcore": "1",
0299 "SampleAfterValue": "100003",
0300 "UMask": "0x1"
0301 },
0302 {
0303 "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
0304 "Counter": "0,1,2,3",
0305 "CounterHTOff": "0,1,2,3",
0306 "EventCode": "0xB7, 0xBB",
0307 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
0308 "MSRIndex": "0x1a6,0x1a7",
0309 "MSRValue": "0x87f820001",
0310 "Offcore": "1",
0311 "SampleAfterValue": "100003",
0312 "UMask": "0x1"
0313 },
0314 {
0315 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
0316 "Counter": "0,1,2,3",
0317 "CounterHTOff": "0,1,2,3",
0318 "EventCode": "0xB7, 0xBB",
0319 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
0320 "MSRIndex": "0x1a6,0x1a7",
0321 "MSRValue": "0x3fffc20040",
0322 "Offcore": "1",
0323 "SampleAfterValue": "100003",
0324 "UMask": "0x1"
0325 },
0326 {
0327 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
0328 "Counter": "0,1,2,3",
0329 "CounterHTOff": "0,1,2,3",
0330 "EventCode": "0xB7, 0xBB",
0331 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
0332 "MSRIndex": "0x1a6,0x1a7",
0333 "MSRValue": "0x67fc00010",
0334 "Offcore": "1",
0335 "SampleAfterValue": "100003",
0336 "UMask": "0x1"
0337 },
0338 {
0339 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
0340 "Counter": "0,1,2,3",
0341 "CounterHTOff": "0,1,2,3",
0342 "EventCode": "0xB7, 0xBB",
0343 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
0344 "MSRIndex": "0x1a6,0x1a7",
0345 "MSRValue": "0x3fffc20010",
0346 "Offcore": "1",
0347 "SampleAfterValue": "100003",
0348 "UMask": "0x1"
0349 },
0350 {
0351 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
0352 "Counter": "0,1,2,3",
0353 "CounterHTOff": "0,1,2,3",
0354 "EventCode": "0xB7, 0xBB",
0355 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
0356 "MSRIndex": "0x1a6,0x1a7",
0357 "MSRValue": "0x600400010",
0358 "Offcore": "1",
0359 "SampleAfterValue": "100003",
0360 "UMask": "0x1"
0361 },
0362 {
0363 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
0364 "Counter": "0,1,2,3",
0365 "CounterHTOff": "0,1,2,3",
0366 "EventCode": "0xB7, 0xBB",
0367 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
0368 "MSRIndex": "0x1a6,0x1a7",
0369 "MSRValue": "0x67f800010",
0370 "Offcore": "1",
0371 "SampleAfterValue": "100003",
0372 "UMask": "0x1"
0373 },
0374 {
0375 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
0376 "Counter": "0,1,2,3",
0377 "CounterHTOff": "0,1,2,3",
0378 "EventCode": "0xB7, 0xBB",
0379 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
0380 "MSRIndex": "0x1a6,0x1a7",
0381 "MSRValue": "0x107fc00010",
0382 "Offcore": "1",
0383 "SampleAfterValue": "100003",
0384 "UMask": "0x1"
0385 },
0386 {
0387 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
0388 "Counter": "0,1,2,3",
0389 "CounterHTOff": "0,1,2,3",
0390 "EventCode": "0xB7, 0xBB",
0391 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
0392 "MSRIndex": "0x1a6,0x1a7",
0393 "MSRValue": "0x87f820010",
0394 "Offcore": "1",
0395 "SampleAfterValue": "100003",
0396 "UMask": "0x1"
0397 },
0398 {
0399 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
0400 "Counter": "0,1,2,3",
0401 "CounterHTOff": "0,1,2,3",
0402 "EventCode": "0xB7, 0xBB",
0403 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
0404 "MSRIndex": "0x1a6,0x1a7",
0405 "MSRValue": "0x3fffc20200",
0406 "Offcore": "1",
0407 "SampleAfterValue": "100003",
0408 "UMask": "0x1"
0409 },
0410 {
0411 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
0412 "Counter": "0,1,2,3",
0413 "CounterHTOff": "0,1,2,3",
0414 "EventCode": "0xB7, 0xBB",
0415 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
0416 "MSRIndex": "0x1a6,0x1a7",
0417 "MSRValue": "0x3fffc20080",
0418 "Offcore": "1",
0419 "SampleAfterValue": "100003",
0420 "UMask": "0x1"
0421 }
0422 ]
