0001 [
0002 {
0003 "BriefDescription": "L1D data line replacements",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x51",
0007 "EventName": "L1D.REPLACEMENT",
0008 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
0009 "SampleAfterValue": "2000003",
0010 "UMask": "0x1"
0011 },
0012 {
0013 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "CounterMask": "1",
0017 "EventCode": "0x48",
0018 "EventName": "L1D_PEND_MISS.FB_FULL",
0019 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
0020 "SampleAfterValue": "2000003",
0021 "UMask": "0x2"
0022 },
0023 {
0024 "BriefDescription": "L1D miss oustandings duration in cycles",
0025 "Counter": "2",
0026 "CounterHTOff": "2",
0027 "EventCode": "0x48",
0028 "EventName": "L1D_PEND_MISS.PENDING",
0029 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x1"
0032 },
0033 {
0034 "BriefDescription": "Cycles with L1D load Misses outstanding.",
0035 "Counter": "2",
0036 "CounterHTOff": "2",
0037 "CounterMask": "1",
0038 "EventCode": "0x48",
0039 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
0040 "SampleAfterValue": "2000003",
0041 "UMask": "0x1"
0042 },
0043 {
0044 "AnyThread": "1",
0045 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
0046 "Counter": "2",
0047 "CounterHTOff": "2",
0048 "CounterMask": "1",
0049 "EventCode": "0x48",
0050 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
0051 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
0052 "SampleAfterValue": "2000003",
0053 "UMask": "0x1"
0054 },
0055 {
0056 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
0057 "Counter": "0,1,2,3",
0058 "CounterHTOff": "0,1,2,3,4,5,6,7",
0059 "EventCode": "0x28",
0060 "EventName": "L2_L1D_WB_RQSTS.ALL",
0061 "SampleAfterValue": "200003",
0062 "UMask": "0xf"
0063 },
0064 {
0065 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
0066 "Counter": "0,1,2,3",
0067 "CounterHTOff": "0,1,2,3,4,5,6,7",
0068 "EventCode": "0x28",
0069 "EventName": "L2_L1D_WB_RQSTS.HIT_E",
0070 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
0071 "SampleAfterValue": "200003",
0072 "UMask": "0x4"
0073 },
0074 {
0075 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
0076 "Counter": "0,1,2,3",
0077 "CounterHTOff": "0,1,2,3,4,5,6,7",
0078 "EventCode": "0x28",
0079 "EventName": "L2_L1D_WB_RQSTS.HIT_M",
0080 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
0081 "SampleAfterValue": "200003",
0082 "UMask": "0x8"
0083 },
0084 {
0085 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
0086 "Counter": "0,1,2,3",
0087 "CounterHTOff": "0,1,2,3,4,5,6,7",
0088 "EventCode": "0x28",
0089 "EventName": "L2_L1D_WB_RQSTS.MISS",
0090 "PublicDescription": "Not rejected writebacks that missed LLC.",
0091 "SampleAfterValue": "200003",
0092 "UMask": "0x1"
0093 },
0094 {
0095 "BriefDescription": "L2 cache lines filling L2",
0096 "Counter": "0,1,2,3",
0097 "CounterHTOff": "0,1,2,3,4,5,6,7",
0098 "EventCode": "0xF1",
0099 "EventName": "L2_LINES_IN.ALL",
0100 "PublicDescription": "L2 cache lines filling L2.",
0101 "SampleAfterValue": "100003",
0102 "UMask": "0x7"
0103 },
0104 {
0105 "BriefDescription": "L2 cache lines in E state filling L2",
0106 "Counter": "0,1,2,3",
0107 "CounterHTOff": "0,1,2,3,4,5,6,7",
0108 "EventCode": "0xF1",
0109 "EventName": "L2_LINES_IN.E",
0110 "PublicDescription": "L2 cache lines in E state filling L2.",
0111 "SampleAfterValue": "100003",
0112 "UMask": "0x4"
0113 },
0114 {
0115 "BriefDescription": "L2 cache lines in I state filling L2",
0116 "Counter": "0,1,2,3",
0117 "CounterHTOff": "0,1,2,3,4,5,6,7",
0118 "EventCode": "0xF1",
0119 "EventName": "L2_LINES_IN.I",
0120 "PublicDescription": "L2 cache lines in I state filling L2.",
0121 "SampleAfterValue": "100003",
0122 "UMask": "0x1"
0123 },
0124 {
0125 "BriefDescription": "L2 cache lines in S state filling L2",
0126 "Counter": "0,1,2,3",
0127 "CounterHTOff": "0,1,2,3,4,5,6,7",
0128 "EventCode": "0xF1",
0129 "EventName": "L2_LINES_IN.S",
0130 "PublicDescription": "L2 cache lines in S state filling L2.",
0131 "SampleAfterValue": "100003",
0132 "UMask": "0x2"
0133 },
0134 {
0135 "BriefDescription": "Clean L2 cache lines evicted by demand",
0136 "Counter": "0,1,2,3",
0137 "CounterHTOff": "0,1,2,3,4,5,6,7",
0138 "EventCode": "0xF2",
0139 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
0140 "PublicDescription": "Clean L2 cache lines evicted by demand.",
0141 "SampleAfterValue": "100003",
0142 "UMask": "0x1"
0143 },
0144 {
0145 "BriefDescription": "Dirty L2 cache lines evicted by demand",
0146 "Counter": "0,1,2,3",
0147 "CounterHTOff": "0,1,2,3,4,5,6,7",
0148 "EventCode": "0xF2",
0149 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
0150 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
0151 "SampleAfterValue": "100003",
0152 "UMask": "0x2"
0153 },
0154 {
0155 "BriefDescription": "Dirty L2 cache lines filling the L2",
0156 "Counter": "0,1,2,3",
0157 "CounterHTOff": "0,1,2,3,4,5,6,7",
0158 "EventCode": "0xF2",
0159 "EventName": "L2_LINES_OUT.DIRTY_ALL",
0160 "PublicDescription": "Dirty L2 cache lines filling the L2.",
0161 "SampleAfterValue": "100003",
0162 "UMask": "0xa"
0163 },
0164 {
0165 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
0166 "Counter": "0,1,2,3",
0167 "CounterHTOff": "0,1,2,3,4,5,6,7",
0168 "EventCode": "0xF2",
0169 "EventName": "L2_LINES_OUT.PF_CLEAN",
0170 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
0171 "SampleAfterValue": "100003",
0172 "UMask": "0x4"
0173 },
0174 {
0175 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
0176 "Counter": "0,1,2,3",
0177 "CounterHTOff": "0,1,2,3,4,5,6,7",
0178 "EventCode": "0xF2",
0179 "EventName": "L2_LINES_OUT.PF_DIRTY",
0180 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
0181 "SampleAfterValue": "100003",
0182 "UMask": "0x8"
0183 },
0184 {
0185 "BriefDescription": "L2 code requests",
0186 "Counter": "0,1,2,3",
0187 "CounterHTOff": "0,1,2,3,4,5,6,7",
0188 "EventCode": "0x24",
0189 "EventName": "L2_RQSTS.ALL_CODE_RD",
0190 "PublicDescription": "Counts all L2 code requests.",
0191 "SampleAfterValue": "200003",
0192 "UMask": "0x30"
0193 },
0194 {
0195 "BriefDescription": "Demand Data Read requests",
0196 "Counter": "0,1,2,3",
0197 "CounterHTOff": "0,1,2,3,4,5,6,7",
0198 "EventCode": "0x24",
0199 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
0200 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
0201 "SampleAfterValue": "200003",
0202 "UMask": "0x3"
0203 },
0204 {
0205 "BriefDescription": "Requests from L2 hardware prefetchers",
0206 "Counter": "0,1,2,3",
0207 "CounterHTOff": "0,1,2,3,4,5,6,7",
0208 "EventCode": "0x24",
0209 "EventName": "L2_RQSTS.ALL_PF",
0210 "PublicDescription": "Counts all L2 HW prefetcher requests.",
0211 "SampleAfterValue": "200003",
0212 "UMask": "0xc0"
0213 },
0214 {
0215 "BriefDescription": "RFO requests to L2 cache",
0216 "Counter": "0,1,2,3",
0217 "CounterHTOff": "0,1,2,3,4,5,6,7",
0218 "EventCode": "0x24",
0219 "EventName": "L2_RQSTS.ALL_RFO",
0220 "PublicDescription": "Counts all L2 store RFO requests.",
0221 "SampleAfterValue": "200003",
0222 "UMask": "0xc"
0223 },
0224 {
0225 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
0226 "Counter": "0,1,2,3",
0227 "CounterHTOff": "0,1,2,3,4,5,6,7",
0228 "EventCode": "0x24",
0229 "EventName": "L2_RQSTS.CODE_RD_HIT",
0230 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
0231 "SampleAfterValue": "200003",
0232 "UMask": "0x10"
0233 },
0234 {
0235 "BriefDescription": "L2 cache misses when fetching instructions",
0236 "Counter": "0,1,2,3",
0237 "CounterHTOff": "0,1,2,3,4,5,6,7",
0238 "EventCode": "0x24",
0239 "EventName": "L2_RQSTS.CODE_RD_MISS",
0240 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
0241 "SampleAfterValue": "200003",
0242 "UMask": "0x20"
0243 },
0244 {
0245 "BriefDescription": "Demand Data Read requests that hit L2 cache",
0246 "Counter": "0,1,2,3",
0247 "CounterHTOff": "0,1,2,3,4,5,6,7",
0248 "EventCode": "0x24",
0249 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
0250 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
0251 "SampleAfterValue": "200003",
0252 "UMask": "0x1"
0253 },
0254 {
0255 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
0256 "Counter": "0,1,2,3",
0257 "CounterHTOff": "0,1,2,3,4,5,6,7",
0258 "EventCode": "0x24",
0259 "EventName": "L2_RQSTS.PF_HIT",
0260 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
0261 "SampleAfterValue": "200003",
0262 "UMask": "0x40"
0263 },
0264 {
0265 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
0266 "Counter": "0,1,2,3",
0267 "CounterHTOff": "0,1,2,3,4,5,6,7",
0268 "EventCode": "0x24",
0269 "EventName": "L2_RQSTS.PF_MISS",
0270 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
0271 "SampleAfterValue": "200003",
0272 "UMask": "0x80"
0273 },
0274 {
0275 "BriefDescription": "RFO requests that hit L2 cache",
0276 "Counter": "0,1,2,3",
0277 "CounterHTOff": "0,1,2,3,4,5,6,7",
0278 "EventCode": "0x24",
0279 "EventName": "L2_RQSTS.RFO_HIT",
0280 "PublicDescription": "RFO requests that hit L2 cache.",
0281 "SampleAfterValue": "200003",
0282 "UMask": "0x4"
0283 },
0284 {
0285 "BriefDescription": "RFO requests that miss L2 cache",
0286 "Counter": "0,1,2,3",
0287 "CounterHTOff": "0,1,2,3,4,5,6,7",
0288 "EventCode": "0x24",
0289 "EventName": "L2_RQSTS.RFO_MISS",
0290 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
0291 "SampleAfterValue": "200003",
0292 "UMask": "0x8"
0293 },
0294 {
0295 "BriefDescription": "RFOs that access cache lines in any state",
0296 "Counter": "0,1,2,3",
0297 "CounterHTOff": "0,1,2,3,4,5,6,7",
0298 "EventCode": "0x27",
0299 "EventName": "L2_STORE_LOCK_RQSTS.ALL",
0300 "PublicDescription": "RFOs that access cache lines in any state.",
0301 "SampleAfterValue": "200003",
0302 "UMask": "0xf"
0303 },
0304 {
0305 "BriefDescription": "RFOs that hit cache lines in M state",
0306 "Counter": "0,1,2,3",
0307 "CounterHTOff": "0,1,2,3,4,5,6,7",
0308 "EventCode": "0x27",
0309 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
0310 "PublicDescription": "RFOs that hit cache lines in M state.",
0311 "SampleAfterValue": "200003",
0312 "UMask": "0x8"
0313 },
0314 {
0315 "BriefDescription": "RFOs that miss cache lines",
0316 "Counter": "0,1,2,3",
0317 "CounterHTOff": "0,1,2,3,4,5,6,7",
0318 "EventCode": "0x27",
0319 "EventName": "L2_STORE_LOCK_RQSTS.MISS",
0320 "PublicDescription": "RFOs that miss cache lines.",
0321 "SampleAfterValue": "200003",
0322 "UMask": "0x1"
0323 },
0324 {
0325 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
0326 "Counter": "0,1,2,3",
0327 "CounterHTOff": "0,1,2,3,4,5,6,7",
0328 "EventCode": "0xF0",
0329 "EventName": "L2_TRANS.ALL_PF",
0330 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
0331 "SampleAfterValue": "200003",
0332 "UMask": "0x8"
0333 },
0334 {
0335 "BriefDescription": "Transactions accessing L2 pipe",
0336 "Counter": "0,1,2,3",
0337 "CounterHTOff": "0,1,2,3,4,5,6,7",
0338 "EventCode": "0xF0",
0339 "EventName": "L2_TRANS.ALL_REQUESTS",
0340 "PublicDescription": "Transactions accessing L2 pipe.",
0341 "SampleAfterValue": "200003",
0342 "UMask": "0x80"
0343 },
0344 {
0345 "BriefDescription": "L2 cache accesses when fetching instructions",
0346 "Counter": "0,1,2,3",
0347 "CounterHTOff": "0,1,2,3,4,5,6,7",
0348 "EventCode": "0xF0",
0349 "EventName": "L2_TRANS.CODE_RD",
0350 "PublicDescription": "L2 cache accesses when fetching instructions.",
0351 "SampleAfterValue": "200003",
0352 "UMask": "0x4"
0353 },
0354 {
0355 "BriefDescription": "Demand Data Read requests that access L2 cache",
0356 "Counter": "0,1,2,3",
0357 "CounterHTOff": "0,1,2,3,4,5,6,7",
0358 "EventCode": "0xF0",
0359 "EventName": "L2_TRANS.DEMAND_DATA_RD",
0360 "PublicDescription": "Demand Data Read requests that access L2 cache.",
0361 "SampleAfterValue": "200003",
0362 "UMask": "0x1"
0363 },
0364 {
0365 "BriefDescription": "L1D writebacks that access L2 cache",
0366 "Counter": "0,1,2,3",
0367 "CounterHTOff": "0,1,2,3,4,5,6,7",
0368 "EventCode": "0xF0",
0369 "EventName": "L2_TRANS.L1D_WB",
0370 "PublicDescription": "L1D writebacks that access L2 cache.",
0371 "SampleAfterValue": "200003",
0372 "UMask": "0x10"
0373 },
0374 {
0375 "BriefDescription": "L2 fill requests that access L2 cache",
0376 "Counter": "0,1,2,3",
0377 "CounterHTOff": "0,1,2,3,4,5,6,7",
0378 "EventCode": "0xF0",
0379 "EventName": "L2_TRANS.L2_FILL",
0380 "PublicDescription": "L2 fill requests that access L2 cache.",
0381 "SampleAfterValue": "200003",
0382 "UMask": "0x20"
0383 },
0384 {
0385 "BriefDescription": "L2 writebacks that access L2 cache",
0386 "Counter": "0,1,2,3",
0387 "CounterHTOff": "0,1,2,3,4,5,6,7",
0388 "EventCode": "0xF0",
0389 "EventName": "L2_TRANS.L2_WB",
0390 "PublicDescription": "L2 writebacks that access L2 cache.",
0391 "SampleAfterValue": "200003",
0392 "UMask": "0x40"
0393 },
0394 {
0395 "BriefDescription": "RFO requests that access L2 cache",
0396 "Counter": "0,1,2,3",
0397 "CounterHTOff": "0,1,2,3,4,5,6,7",
0398 "EventCode": "0xF0",
0399 "EventName": "L2_TRANS.RFO",
0400 "PublicDescription": "RFO requests that access L2 cache.",
0401 "SampleAfterValue": "200003",
0402 "UMask": "0x2"
0403 },
0404 {
0405 "BriefDescription": "Cycles when L1D is locked",
0406 "Counter": "0,1,2,3",
0407 "CounterHTOff": "0,1,2,3,4,5,6,7",
0408 "EventCode": "0x63",
0409 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
0410 "PublicDescription": "Cycles in which the L1D is locked.",
0411 "SampleAfterValue": "2000003",
0412 "UMask": "0x2"
0413 },
0414 {
0415 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
0416 "Counter": "0,1,2,3",
0417 "CounterHTOff": "0,1,2,3,4,5,6,7",
0418 "EventCode": "0x2E",
0419 "EventName": "LONGEST_LAT_CACHE.MISS",
0420 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
0421 "SampleAfterValue": "100003",
0422 "UMask": "0x41"
0423 },
0424 {
0425 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
0426 "Counter": "0,1,2,3",
0427 "CounterHTOff": "0,1,2,3,4,5,6,7",
0428 "EventCode": "0x2E",
0429 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0430 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
0431 "SampleAfterValue": "100003",
0432 "UMask": "0x4f"
0433 },
0434 {
0435 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
0436 "Counter": "0,1,2,3",
0437 "CounterHTOff": "0,1,2,3",
0438 "EventCode": "0xD2",
0439 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
0440 "PEBS": "1",
0441 "SampleAfterValue": "20011",
0442 "UMask": "0x2"
0443 },
0444 {
0445 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
0446 "Counter": "0,1,2,3",
0447 "CounterHTOff": "0,1,2,3",
0448 "EventCode": "0xD2",
0449 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
0450 "PEBS": "1",
0451 "SampleAfterValue": "20011",
0452 "UMask": "0x4"
0453 },
0454 {
0455 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
0456 "Counter": "0,1,2,3",
0457 "CounterHTOff": "0,1,2,3",
0458 "EventCode": "0xD2",
0459 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
0460 "PEBS": "1",
0461 "SampleAfterValue": "20011",
0462 "UMask": "0x1"
0463 },
0464 {
0465 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
0466 "Counter": "0,1,2,3",
0467 "CounterHTOff": "0,1,2,3",
0468 "EventCode": "0xD2",
0469 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
0470 "PEBS": "1",
0471 "SampleAfterValue": "100003",
0472 "UMask": "0x8"
0473 },
0474 {
0475 "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
0476 "Counter": "0,1,2,3",
0477 "CounterHTOff": "0,1,2,3",
0478 "EventCode": "0xD3",
0479 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
0480 "SampleAfterValue": "100007",
0481 "UMask": "0x3"
0482 },
0483 {
0484 "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
0485 "Counter": "0,1,2,3",
0486 "CounterHTOff": "0,1,2,3",
0487 "EventCode": "0xD3",
0488 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
0489 "SampleAfterValue": "100007",
0490 "UMask": "0xc"
0491 },
0492 {
0493 "BriefDescription": "Data forwarded from remote cache.",
0494 "Counter": "0,1,2,3",
0495 "CounterHTOff": "0,1,2,3",
0496 "EventCode": "0xD3",
0497 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
0498 "SampleAfterValue": "100007",
0499 "UMask": "0x20"
0500 },
0501 {
0502 "BriefDescription": "Remote cache HITM.",
0503 "Counter": "0,1,2,3",
0504 "CounterHTOff": "0,1,2,3",
0505 "EventCode": "0xD3",
0506 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
0507 "SampleAfterValue": "100007",
0508 "UMask": "0x10"
0509 },
0510 {
0511 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
0512 "Counter": "0,1,2,3",
0513 "CounterHTOff": "0,1,2,3",
0514 "EventCode": "0xD1",
0515 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
0516 "PEBS": "1",
0517 "SampleAfterValue": "100003",
0518 "UMask": "0x40"
0519 },
0520 {
0521 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
0522 "Counter": "0,1,2,3",
0523 "CounterHTOff": "0,1,2,3",
0524 "EventCode": "0xD1",
0525 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
0526 "PEBS": "1",
0527 "SampleAfterValue": "2000003",
0528 "UMask": "0x1"
0529 },
0530 {
0531 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
0532 "Counter": "0,1,2,3",
0533 "CounterHTOff": "0,1,2,3",
0534 "EventCode": "0xD1",
0535 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
0536 "PEBS": "1",
0537 "SampleAfterValue": "100003",
0538 "UMask": "0x8"
0539 },
0540 {
0541 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
0542 "Counter": "0,1,2,3",
0543 "CounterHTOff": "0,1,2,3",
0544 "EventCode": "0xD1",
0545 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
0546 "PEBS": "1",
0547 "SampleAfterValue": "100003",
0548 "UMask": "0x2"
0549 },
0550 {
0551 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
0552 "Counter": "0,1,2,3",
0553 "CounterHTOff": "0,1,2,3",
0554 "EventCode": "0xD1",
0555 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
0556 "PEBS": "1",
0557 "SampleAfterValue": "50021",
0558 "UMask": "0x10"
0559 },
0560 {
0561 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
0562 "Counter": "0,1,2,3",
0563 "CounterHTOff": "0,1,2,3",
0564 "EventCode": "0xD1",
0565 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
0566 "PEBS": "1",
0567 "SampleAfterValue": "50021",
0568 "UMask": "0x4"
0569 },
0570 {
0571 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
0572 "Counter": "0,1,2,3",
0573 "CounterHTOff": "0,1,2,3",
0574 "EventCode": "0xD1",
0575 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
0576 "PEBS": "1",
0577 "SampleAfterValue": "100007",
0578 "UMask": "0x20"
0579 },
0580 {
0581 "BriefDescription": "All retired load uops. (Precise Event)",
0582 "Counter": "0,1,2,3",
0583 "CounterHTOff": "0,1,2,3",
0584 "EventCode": "0xD0",
0585 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
0586 "PEBS": "1",
0587 "SampleAfterValue": "2000003",
0588 "UMask": "0x81"
0589 },
0590 {
0591 "BriefDescription": "All retired store uops. (Precise Event)",
0592 "Counter": "0,1,2,3",
0593 "CounterHTOff": "0,1,2,3",
0594 "EventCode": "0xD0",
0595 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
0596 "PEBS": "1",
0597 "SampleAfterValue": "2000003",
0598 "UMask": "0x82"
0599 },
0600 {
0601 "BriefDescription": "Retired load uops with locked access. (Precise Event)",
0602 "Counter": "0,1,2,3",
0603 "CounterHTOff": "0,1,2,3",
0604 "EventCode": "0xD0",
0605 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
0606 "PEBS": "1",
0607 "SampleAfterValue": "100007",
0608 "UMask": "0x21"
0609 },
0610 {
0611 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
0612 "Counter": "0,1,2,3",
0613 "CounterHTOff": "0,1,2,3",
0614 "EventCode": "0xD0",
0615 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
0616 "PEBS": "1",
0617 "SampleAfterValue": "100003",
0618 "UMask": "0x41"
0619 },
0620 {
0621 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
0622 "Counter": "0,1,2,3",
0623 "CounterHTOff": "0,1,2,3",
0624 "EventCode": "0xD0",
0625 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
0626 "PEBS": "1",
0627 "SampleAfterValue": "100003",
0628 "UMask": "0x42"
0629 },
0630 {
0631 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
0632 "Counter": "0,1,2,3",
0633 "CounterHTOff": "0,1,2,3",
0634 "EventCode": "0xD0",
0635 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
0636 "PEBS": "1",
0637 "SampleAfterValue": "100003",
0638 "UMask": "0x11"
0639 },
0640 {
0641 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
0642 "Counter": "0,1,2,3",
0643 "CounterHTOff": "0,1,2,3",
0644 "EventCode": "0xD0",
0645 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
0646 "PEBS": "1",
0647 "SampleAfterValue": "100003",
0648 "UMask": "0x12"
0649 },
0650 {
0651 "BriefDescription": "Demand and prefetch data reads",
0652 "Counter": "0,1,2,3",
0653 "CounterHTOff": "0,1,2,3,4,5,6,7",
0654 "EventCode": "0xB0",
0655 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
0656 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
0657 "SampleAfterValue": "100003",
0658 "UMask": "0x8"
0659 },
0660 {
0661 "BriefDescription": "Cacheable and noncachaeble code read requests",
0662 "Counter": "0,1,2,3",
0663 "CounterHTOff": "0,1,2,3,4,5,6,7",
0664 "EventCode": "0xB0",
0665 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
0666 "PublicDescription": "Demand code read requests sent to uncore.",
0667 "SampleAfterValue": "100003",
0668 "UMask": "0x2"
0669 },
0670 {
0671 "BriefDescription": "Demand Data Read requests sent to uncore",
0672 "Counter": "0,1,2,3",
0673 "CounterHTOff": "0,1,2,3,4,5,6,7",
0674 "EventCode": "0xB0",
0675 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
0676 "PublicDescription": "Demand data read requests sent to uncore.",
0677 "SampleAfterValue": "100003",
0678 "UMask": "0x1"
0679 },
0680 {
0681 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
0682 "Counter": "0,1,2,3",
0683 "CounterHTOff": "0,1,2,3,4,5,6,7",
0684 "EventCode": "0xB0",
0685 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
0686 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
0687 "SampleAfterValue": "100003",
0688 "UMask": "0x4"
0689 },
0690 {
0691 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
0692 "Counter": "0,1,2,3",
0693 "CounterHTOff": "0,1,2,3,4,5,6,7",
0694 "EventCode": "0xB2",
0695 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
0696 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
0697 "SampleAfterValue": "2000003",
0698 "UMask": "0x1"
0699 },
0700 {
0701 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
0702 "Counter": "0,1,2,3",
0703 "CounterHTOff": "0,1,2,3,4,5,6,7",
0704 "EventCode": "0x60",
0705 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
0706 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0707 "SampleAfterValue": "2000003",
0708 "UMask": "0x8"
0709 },
0710 {
0711 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
0712 "Counter": "0,1,2,3",
0713 "CounterHTOff": "0,1,2,3,4,5,6,7",
0714 "CounterMask": "1",
0715 "EventCode": "0x60",
0716 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
0717 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
0718 "SampleAfterValue": "2000003",
0719 "UMask": "0x8"
0720 },
0721 {
0722 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
0723 "Counter": "0,1,2,3",
0724 "CounterHTOff": "0,1,2,3,4,5,6,7",
0725 "CounterMask": "1",
0726 "EventCode": "0x60",
0727 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
0728 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
0729 "SampleAfterValue": "2000003",
0730 "UMask": "0x2"
0731 },
0732 {
0733 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
0734 "Counter": "0,1,2,3",
0735 "CounterHTOff": "0,1,2,3,4,5,6,7",
0736 "CounterMask": "1",
0737 "EventCode": "0x60",
0738 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
0739 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
0740 "SampleAfterValue": "2000003",
0741 "UMask": "0x1"
0742 },
0743 {
0744 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
0745 "Counter": "0,1,2,3",
0746 "CounterHTOff": "0,1,2,3,4,5,6,7",
0747 "CounterMask": "1",
0748 "EventCode": "0x60",
0749 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
0750 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
0751 "SampleAfterValue": "2000003",
0752 "UMask": "0x4"
0753 },
0754 {
0755 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
0756 "Counter": "0,1,2,3",
0757 "CounterHTOff": "0,1,2,3,4,5,6,7",
0758 "EventCode": "0x60",
0759 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
0760 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0761 "SampleAfterValue": "2000003",
0762 "UMask": "0x2"
0763 },
0764 {
0765 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
0766 "Counter": "0,1,2,3",
0767 "CounterHTOff": "0,1,2,3,4,5,6,7",
0768 "EventCode": "0x60",
0769 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
0770 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0771 "SampleAfterValue": "2000003",
0772 "UMask": "0x1"
0773 },
0774 {
0775 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
0776 "Counter": "0,1,2,3",
0777 "CounterHTOff": "0,1,2,3,4,5,6,7",
0778 "CounterMask": "6",
0779 "EventCode": "0x60",
0780 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
0781 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
0782 "SampleAfterValue": "2000003",
0783 "UMask": "0x1"
0784 },
0785 {
0786 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
0787 "Counter": "0,1,2,3",
0788 "CounterHTOff": "0,1,2,3,4,5,6,7",
0789 "EventCode": "0x60",
0790 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
0791 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0792 "SampleAfterValue": "2000003",
0793 "UMask": "0x4"
0794 },
0795 {
0796 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0797 "Counter": "0,1,2,3",
0798 "CounterHTOff": "0,1,2,3",
0799 "EventCode": "0xB7, 0xBB",
0800 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
0801 "MSRIndex": "0x1a6,0x1a7",
0802 "MSRValue": "0x10003c0091",
0803 "Offcore": "1",
0804 "SampleAfterValue": "100003",
0805 "UMask": "0x1"
0806 },
0807 {
0808 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0809 "Counter": "0,1,2,3",
0810 "CounterHTOff": "0,1,2,3",
0811 "EventCode": "0xB7, 0xBB",
0812 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
0813 "MSRIndex": "0x1a6,0x1a7",
0814 "MSRValue": "0x4003c0091",
0815 "Offcore": "1",
0816 "SampleAfterValue": "100003",
0817 "UMask": "0x1"
0818 },
0819 {
0820 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
0821 "Counter": "0,1,2,3",
0822 "CounterHTOff": "0,1,2,3",
0823 "EventCode": "0xB7, 0xBB",
0824 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
0825 "MSRIndex": "0x1a6,0x1a7",
0826 "MSRValue": "0x1003c0091",
0827 "Offcore": "1",
0828 "SampleAfterValue": "100003",
0829 "UMask": "0x1"
0830 },
0831 {
0832 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
0833 "Counter": "0,1,2,3",
0834 "CounterHTOff": "0,1,2,3",
0835 "EventCode": "0xB7, 0xBB",
0836 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
0837 "MSRIndex": "0x1a6,0x1a7",
0838 "MSRValue": "0x2003c0091",
0839 "Offcore": "1",
0840 "SampleAfterValue": "100003",
0841 "UMask": "0x1"
0842 },
0843 {
0844 "BriefDescription": "Counts all prefetch data reads that hit the LLC",
0845 "Counter": "0,1,2,3",
0846 "CounterHTOff": "0,1,2,3",
0847 "EventCode": "0xB7, 0xBB",
0848 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
0849 "MSRIndex": "0x1a6,0x1a7",
0850 "MSRValue": "0x3f803c0090",
0851 "Offcore": "1",
0852 "SampleAfterValue": "100003",
0853 "UMask": "0x1"
0854 },
0855 {
0856 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0857 "Counter": "0,1,2,3",
0858 "CounterHTOff": "0,1,2,3",
0859 "EventCode": "0xB7, 0xBB",
0860 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
0861 "MSRIndex": "0x1a6,0x1a7",
0862 "MSRValue": "0x10003c0090",
0863 "Offcore": "1",
0864 "SampleAfterValue": "100003",
0865 "UMask": "0x1"
0866 },
0867 {
0868 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0869 "Counter": "0,1,2,3",
0870 "CounterHTOff": "0,1,2,3",
0871 "EventCode": "0xB7, 0xBB",
0872 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
0873 "MSRIndex": "0x1a6,0x1a7",
0874 "MSRValue": "0x4003c0090",
0875 "Offcore": "1",
0876 "SampleAfterValue": "100003",
0877 "UMask": "0x1"
0878 },
0879 {
0880 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
0881 "Counter": "0,1,2,3",
0882 "CounterHTOff": "0,1,2,3",
0883 "EventCode": "0xB7, 0xBB",
0884 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
0885 "MSRIndex": "0x1a6,0x1a7",
0886 "MSRValue": "0x1003c0090",
0887 "Offcore": "1",
0888 "SampleAfterValue": "100003",
0889 "UMask": "0x1"
0890 },
0891 {
0892 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
0893 "Counter": "0,1,2,3",
0894 "CounterHTOff": "0,1,2,3",
0895 "EventCode": "0xB7, 0xBB",
0896 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
0897 "MSRIndex": "0x1a6,0x1a7",
0898 "MSRValue": "0x2003c0090",
0899 "Offcore": "1",
0900 "SampleAfterValue": "100003",
0901 "UMask": "0x1"
0902 },
0903 {
0904 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
0905 "Counter": "0,1,2,3",
0906 "CounterHTOff": "0,1,2,3",
0907 "EventCode": "0xB7, 0xBB",
0908 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
0909 "MSRIndex": "0x1a6,0x1a7",
0910 "MSRValue": "0x3f803c03f7",
0911 "Offcore": "1",
0912 "SampleAfterValue": "100003",
0913 "UMask": "0x1"
0914 },
0915 {
0916 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0917 "Counter": "0,1,2,3",
0918 "CounterHTOff": "0,1,2,3",
0919 "EventCode": "0xB7, 0xBB",
0920 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
0921 "MSRIndex": "0x1a6,0x1a7",
0922 "MSRValue": "0x10003c03f7",
0923 "Offcore": "1",
0924 "SampleAfterValue": "100003",
0925 "UMask": "0x1"
0926 },
0927 {
0928 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0929 "Counter": "0,1,2,3",
0930 "CounterHTOff": "0,1,2,3",
0931 "EventCode": "0xB7, 0xBB",
0932 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
0933 "MSRIndex": "0x1a6,0x1a7",
0934 "MSRValue": "0x4003c03f7",
0935 "Offcore": "1",
0936 "SampleAfterValue": "100003",
0937 "UMask": "0x1"
0938 },
0939 {
0940 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
0941 "Counter": "0,1,2,3",
0942 "CounterHTOff": "0,1,2,3",
0943 "EventCode": "0xB7, 0xBB",
0944 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
0945 "MSRIndex": "0x1a6,0x1a7",
0946 "MSRValue": "0x1003c03f7",
0947 "Offcore": "1",
0948 "SampleAfterValue": "100003",
0949 "UMask": "0x1"
0950 },
0951 {
0952 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
0953 "Counter": "0,1,2,3",
0954 "CounterHTOff": "0,1,2,3",
0955 "EventCode": "0xB7, 0xBB",
0956 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
0957 "MSRIndex": "0x1a6,0x1a7",
0958 "MSRValue": "0x2003c03f7",
0959 "Offcore": "1",
0960 "SampleAfterValue": "100003",
0961 "UMask": "0x1"
0962 },
0963 {
0964 "BriefDescription": "Counts all writebacks from the core to the LLC",
0965 "Counter": "0,1,2,3",
0966 "CounterHTOff": "0,1,2,3",
0967 "EventCode": "0xB7, 0xBB",
0968 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
0969 "MSRIndex": "0x1a6,0x1a7",
0970 "MSRValue": "0x10008",
0971 "Offcore": "1",
0972 "SampleAfterValue": "100003",
0973 "UMask": "0x1"
0974 },
0975 {
0976 "BriefDescription": "Counts all demand code reads that hit in the LLC",
0977 "Counter": "0,1,2,3",
0978 "CounterHTOff": "0,1,2,3",
0979 "EventCode": "0xB7, 0xBB",
0980 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
0981 "MSRIndex": "0x1a6,0x1a7",
0982 "MSRValue": "0x3f803c0004",
0983 "Offcore": "1",
0984 "SampleAfterValue": "100003",
0985 "UMask": "0x1"
0986 },
0987 {
0988 "BriefDescription": "Counts all demand data reads that hit in the LLC",
0989 "Counter": "0,1,2,3",
0990 "CounterHTOff": "0,1,2,3",
0991 "EventCode": "0xB7, 0xBB",
0992 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
0993 "MSRIndex": "0x1a6,0x1a7",
0994 "MSRValue": "0x3f803c0001",
0995 "Offcore": "1",
0996 "SampleAfterValue": "100003",
0997 "UMask": "0x1"
0998 },
0999 {
1000 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1001 "Counter": "0,1,2,3",
1002 "CounterHTOff": "0,1,2,3",
1003 "EventCode": "0xB7, 0xBB",
1004 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1005 "MSRIndex": "0x1a6,0x1a7",
1006 "MSRValue": "0x10003c0001",
1007 "Offcore": "1",
1008 "SampleAfterValue": "100003",
1009 "UMask": "0x1"
1010 },
1011 {
1012 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1013 "Counter": "0,1,2,3",
1014 "CounterHTOff": "0,1,2,3",
1015 "EventCode": "0xB7, 0xBB",
1016 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1017 "MSRIndex": "0x1a6,0x1a7",
1018 "MSRValue": "0x4003c0001",
1019 "Offcore": "1",
1020 "SampleAfterValue": "100003",
1021 "UMask": "0x1"
1022 },
1023 {
1024 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1025 "Counter": "0,1,2,3",
1026 "CounterHTOff": "0,1,2,3",
1027 "EventCode": "0xB7, 0xBB",
1028 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1029 "MSRIndex": "0x1a6,0x1a7",
1030 "MSRValue": "0x1003c0001",
1031 "Offcore": "1",
1032 "SampleAfterValue": "100003",
1033 "UMask": "0x1"
1034 },
1035 {
1036 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
1037 "Counter": "0,1,2,3",
1038 "CounterHTOff": "0,1,2,3",
1039 "EventCode": "0xB7, 0xBB",
1040 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
1041 "MSRIndex": "0x1a6,0x1a7",
1042 "MSRValue": "0x2003c0001",
1043 "Offcore": "1",
1044 "SampleAfterValue": "100003",
1045 "UMask": "0x1"
1046 },
1047 {
1048 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1049 "Counter": "0,1,2,3",
1050 "CounterHTOff": "0,1,2,3",
1051 "EventCode": "0xB7, 0xBB",
1052 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
1053 "MSRIndex": "0x1a6,0x1a7",
1054 "MSRValue": "0x10003c0002",
1055 "Offcore": "1",
1056 "SampleAfterValue": "100003",
1057 "UMask": "0x1"
1058 },
1059 {
1060 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
1061 "Counter": "0,1,2,3",
1062 "CounterHTOff": "0,1,2,3",
1063 "EventCode": "0xB7, 0xBB",
1064 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
1065 "MSRIndex": "0x1a6,0x1a7",
1066 "MSRValue": "0x803c8000",
1067 "Offcore": "1",
1068 "SampleAfterValue": "100003",
1069 "UMask": "0x1"
1070 },
1071 {
1072 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
1073 "Counter": "0,1,2,3",
1074 "CounterHTOff": "0,1,2,3",
1075 "EventCode": "0xB7, 0xBB",
1076 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
1077 "MSRIndex": "0x1a6,0x1a7",
1078 "MSRValue": "0x23ffc08000",
1079 "Offcore": "1",
1080 "SampleAfterValue": "100003",
1081 "UMask": "0x1"
1082 },
1083 {
1084 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
1085 "Counter": "0,1,2,3",
1086 "CounterHTOff": "0,1,2,3",
1087 "EventCode": "0xB7, 0xBB",
1088 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
1089 "MSRIndex": "0x1a6,0x1a7",
1090 "MSRValue": "0x3f803c0040",
1091 "Offcore": "1",
1092 "SampleAfterValue": "100003",
1093 "UMask": "0x1"
1094 },
1095 {
1096 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
1097 "Counter": "0,1,2,3",
1098 "CounterHTOff": "0,1,2,3",
1099 "EventCode": "0xB7, 0xBB",
1100 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
1101 "MSRIndex": "0x1a6,0x1a7",
1102 "MSRValue": "0x3f803c0010",
1103 "Offcore": "1",
1104 "SampleAfterValue": "100003",
1105 "UMask": "0x1"
1106 },
1107 {
1108 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1109 "Counter": "0,1,2,3",
1110 "CounterHTOff": "0,1,2,3",
1111 "EventCode": "0xB7, 0xBB",
1112 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1113 "MSRIndex": "0x1a6,0x1a7",
1114 "MSRValue": "0x10003c0010",
1115 "Offcore": "1",
1116 "SampleAfterValue": "100003",
1117 "UMask": "0x1"
1118 },
1119 {
1120 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1121 "Counter": "0,1,2,3",
1122 "CounterHTOff": "0,1,2,3",
1123 "EventCode": "0xB7, 0xBB",
1124 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1125 "MSRIndex": "0x1a6,0x1a7",
1126 "MSRValue": "0x4003c0010",
1127 "Offcore": "1",
1128 "SampleAfterValue": "100003",
1129 "UMask": "0x1"
1130 },
1131 {
1132 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1133 "Counter": "0,1,2,3",
1134 "CounterHTOff": "0,1,2,3",
1135 "EventCode": "0xB7, 0xBB",
1136 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1137 "MSRIndex": "0x1a6,0x1a7",
1138 "MSRValue": "0x1003c0010",
1139 "Offcore": "1",
1140 "SampleAfterValue": "100003",
1141 "UMask": "0x1"
1142 },
1143 {
1144 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1145 "Counter": "0,1,2,3",
1146 "CounterHTOff": "0,1,2,3",
1147 "EventCode": "0xB7, 0xBB",
1148 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
1149 "MSRIndex": "0x1a6,0x1a7",
1150 "MSRValue": "0x2003c0010",
1151 "Offcore": "1",
1152 "SampleAfterValue": "100003",
1153 "UMask": "0x1"
1154 },
1155 {
1156 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
1157 "Counter": "0,1,2,3",
1158 "CounterHTOff": "0,1,2,3",
1159 "EventCode": "0xB7, 0xBB",
1160 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
1161 "MSRIndex": "0x1a6,0x1a7",
1162 "MSRValue": "0x3f803c0200",
1163 "Offcore": "1",
1164 "SampleAfterValue": "100003",
1165 "UMask": "0x1"
1166 },
1167 {
1168 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
1169 "Counter": "0,1,2,3",
1170 "CounterHTOff": "0,1,2,3",
1171 "EventCode": "0xB7, 0xBB",
1172 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
1173 "MSRIndex": "0x1a6,0x1a7",
1174 "MSRValue": "0x3f803c0080",
1175 "Offcore": "1",
1176 "SampleAfterValue": "100003",
1177 "UMask": "0x1"
1178 },
1179 {
1180 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1181 "Counter": "0,1,2,3",
1182 "CounterHTOff": "0,1,2,3",
1183 "EventCode": "0xB7, 0xBB",
1184 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1185 "MSRIndex": "0x1a6,0x1a7",
1186 "MSRValue": "0x10003c0080",
1187 "Offcore": "1",
1188 "SampleAfterValue": "100003",
1189 "UMask": "0x1"
1190 },
1191 {
1192 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1193 "Counter": "0,1,2,3",
1194 "CounterHTOff": "0,1,2,3",
1195 "EventCode": "0xB7, 0xBB",
1196 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1197 "MSRIndex": "0x1a6,0x1a7",
1198 "MSRValue": "0x4003c0080",
1199 "Offcore": "1",
1200 "SampleAfterValue": "100003",
1201 "UMask": "0x1"
1202 },
1203 {
1204 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1205 "Counter": "0,1,2,3",
1206 "CounterHTOff": "0,1,2,3",
1207 "EventCode": "0xB7, 0xBB",
1208 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1209 "MSRIndex": "0x1a6,0x1a7",
1210 "MSRValue": "0x1003c0080",
1211 "Offcore": "1",
1212 "SampleAfterValue": "100003",
1213 "UMask": "0x1"
1214 },
1215 {
1216 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1217 "Counter": "0,1,2,3",
1218 "CounterHTOff": "0,1,2,3",
1219 "EventCode": "0xB7, 0xBB",
1220 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
1221 "MSRIndex": "0x1a6,0x1a7",
1222 "MSRValue": "0x2003c0080",
1223 "Offcore": "1",
1224 "SampleAfterValue": "100003",
1225 "UMask": "0x1"
1226 },
1227 {
1228 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
1229 "Counter": "0,1,2,3",
1230 "CounterHTOff": "0,1,2,3",
1231 "EventCode": "0xB7, 0xBB",
1232 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1233 "MSRIndex": "0x1a6,0x1a7",
1234 "MSRValue": "0x10400",
1235 "Offcore": "1",
1236 "SampleAfterValue": "100003",
1237 "UMask": "0x1"
1238 },
1239 {
1240 "BriefDescription": "Counts non-temporal stores",
1241 "Counter": "0,1,2,3",
1242 "CounterHTOff": "0,1,2,3",
1243 "EventCode": "0xB7, 0xBB",
1244 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1245 "MSRIndex": "0x1a6,0x1a7",
1246 "MSRValue": "0x10800",
1247 "Offcore": "1",
1248 "SampleAfterValue": "100003",
1249 "UMask": "0x1"
1250 },
1251 {
1252 "BriefDescription": "Split locks in SQ",
1253 "Counter": "0,1,2,3",
1254 "CounterHTOff": "0,1,2,3,4,5,6,7",
1255 "EventCode": "0xF4",
1256 "EventName": "SQ_MISC.SPLIT_LOCK",
1257 "SampleAfterValue": "100003",
1258 "UMask": "0x10"
1259 }
1260 ]
