0001 [
0002 {
0003 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xC3",
0007 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0008 "SampleAfterValue": "100003",
0009 "UMask": "0x2"
0010 },
0011 {
0012 "BriefDescription": "Loads with latency value being above 128",
0013 "Counter": "3",
0014 "CounterHTOff": "3",
0015 "EventCode": "0xCD",
0016 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0017 "MSRIndex": "0x3F6",
0018 "MSRValue": "0x80",
0019 "PEBS": "2",
0020 "PublicDescription": "Loads with latency value being above 128.",
0021 "SampleAfterValue": "1009",
0022 "TakenAlone": "1",
0023 "UMask": "0x1"
0024 },
0025 {
0026 "BriefDescription": "Loads with latency value being above 16",
0027 "Counter": "3",
0028 "CounterHTOff": "3",
0029 "EventCode": "0xCD",
0030 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0031 "MSRIndex": "0x3F6",
0032 "MSRValue": "0x10",
0033 "PEBS": "2",
0034 "PublicDescription": "Loads with latency value being above 16.",
0035 "SampleAfterValue": "20011",
0036 "TakenAlone": "1",
0037 "UMask": "0x1"
0038 },
0039 {
0040 "BriefDescription": "Loads with latency value being above 256",
0041 "Counter": "3",
0042 "CounterHTOff": "3",
0043 "EventCode": "0xCD",
0044 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0045 "MSRIndex": "0x3F6",
0046 "MSRValue": "0x100",
0047 "PEBS": "2",
0048 "PublicDescription": "Loads with latency value being above 256.",
0049 "SampleAfterValue": "503",
0050 "TakenAlone": "1",
0051 "UMask": "0x1"
0052 },
0053 {
0054 "BriefDescription": "Loads with latency value being above 32",
0055 "Counter": "3",
0056 "CounterHTOff": "3",
0057 "EventCode": "0xCD",
0058 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0059 "MSRIndex": "0x3F6",
0060 "MSRValue": "0x20",
0061 "PEBS": "2",
0062 "PublicDescription": "Loads with latency value being above 32.",
0063 "SampleAfterValue": "100007",
0064 "TakenAlone": "1",
0065 "UMask": "0x1"
0066 },
0067 {
0068 "BriefDescription": "Loads with latency value being above 4",
0069 "Counter": "3",
0070 "CounterHTOff": "3",
0071 "EventCode": "0xCD",
0072 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0073 "MSRIndex": "0x3F6",
0074 "MSRValue": "0x4",
0075 "PEBS": "2",
0076 "PublicDescription": "Loads with latency value being above 4.",
0077 "SampleAfterValue": "100003",
0078 "TakenAlone": "1",
0079 "UMask": "0x1"
0080 },
0081 {
0082 "BriefDescription": "Loads with latency value being above 512",
0083 "Counter": "3",
0084 "CounterHTOff": "3",
0085 "EventCode": "0xCD",
0086 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0087 "MSRIndex": "0x3F6",
0088 "MSRValue": "0x200",
0089 "PEBS": "2",
0090 "PublicDescription": "Loads with latency value being above 512.",
0091 "SampleAfterValue": "101",
0092 "TakenAlone": "1",
0093 "UMask": "0x1"
0094 },
0095 {
0096 "BriefDescription": "Loads with latency value being above 64",
0097 "Counter": "3",
0098 "CounterHTOff": "3",
0099 "EventCode": "0xCD",
0100 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0101 "MSRIndex": "0x3F6",
0102 "MSRValue": "0x40",
0103 "PEBS": "2",
0104 "PublicDescription": "Loads with latency value being above 64.",
0105 "SampleAfterValue": "2003",
0106 "TakenAlone": "1",
0107 "UMask": "0x1"
0108 },
0109 {
0110 "BriefDescription": "Loads with latency value being above 8",
0111 "Counter": "3",
0112 "CounterHTOff": "3",
0113 "EventCode": "0xCD",
0114 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0115 "MSRIndex": "0x3F6",
0116 "MSRValue": "0x8",
0117 "PEBS": "2",
0118 "PublicDescription": "Loads with latency value being above 8.",
0119 "SampleAfterValue": "50021",
0120 "TakenAlone": "1",
0121 "UMask": "0x1"
0122 },
0123 {
0124 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
0125 "Counter": "3",
0126 "CounterHTOff": "3",
0127 "EventCode": "0xCD",
0128 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
0129 "PEBS": "2",
0130 "PRECISE_STORE": "1",
0131 "SampleAfterValue": "2000003",
0132 "TakenAlone": "1",
0133 "UMask": "0x2"
0134 },
0135 {
0136 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
0137 "Counter": "0,1,2,3",
0138 "CounterHTOff": "0,1,2,3,4,5,6,7",
0139 "EventCode": "0x05",
0140 "EventName": "MISALIGN_MEM_REF.LOADS",
0141 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
0142 "SampleAfterValue": "2000003",
0143 "UMask": "0x1"
0144 },
0145 {
0146 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
0147 "Counter": "0,1,2,3",
0148 "CounterHTOff": "0,1,2,3,4,5,6,7",
0149 "EventCode": "0x05",
0150 "EventName": "MISALIGN_MEM_REF.STORES",
0151 "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
0152 "SampleAfterValue": "2000003",
0153 "UMask": "0x2"
0154 },
0155 {
0156 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
0157 "Counter": "0,1,2,3",
0158 "CounterHTOff": "0,1,2,3",
0159 "EventCode": "0xB7, 0xBB",
0160 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
0161 "MSRIndex": "0x1a6,0x1a7",
0162 "MSRValue": "0x300400244",
0163 "Offcore": "1",
0164 "SampleAfterValue": "100003",
0165 "UMask": "0x1"
0166 },
0167 {
0168 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
0169 "Counter": "0,1,2,3",
0170 "CounterHTOff": "0,1,2,3",
0171 "EventCode": "0xB7, 0xBB",
0172 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
0173 "MSRIndex": "0x1a6,0x1a7",
0174 "MSRValue": "0x300400091",
0175 "Offcore": "1",
0176 "SampleAfterValue": "100003",
0177 "UMask": "0x1"
0178 },
0179 {
0180 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
0181 "Counter": "0,1,2,3",
0182 "CounterHTOff": "0,1,2,3",
0183 "EventCode": "0xB7, 0xBB",
0184 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
0185 "MSRIndex": "0x1a6,0x1a7",
0186 "MSRValue": "0x3004003f7",
0187 "Offcore": "1",
0188 "SampleAfterValue": "100003",
0189 "UMask": "0x1"
0190 },
0191 {
0192 "BriefDescription": "Counts LLC replacements",
0193 "Counter": "0,1,2,3",
0194 "CounterHTOff": "0,1,2,3",
0195 "EventCode": "0xB7, 0xBB",
0196 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
0197 "MSRIndex": "0x1a6,0x1a7",
0198 "MSRValue": "0x6004001b3",
0199 "Offcore": "1",
0200 "SampleAfterValue": "100003",
0201 "UMask": "0x1"
0202 },
0203 {
0204 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
0205 "Counter": "0,1,2,3",
0206 "CounterHTOff": "0,1,2,3",
0207 "EventCode": "0xB7, 0xBB",
0208 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
0209 "MSRIndex": "0x1a6,0x1a7",
0210 "MSRValue": "0x300400004",
0211 "Offcore": "1",
0212 "SampleAfterValue": "100003",
0213 "UMask": "0x1"
0214 },
0215 {
0216 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
0217 "Counter": "0,1,2,3",
0218 "CounterHTOff": "0,1,2,3",
0219 "EventCode": "0xB7, 0xBB",
0220 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
0221 "MSRIndex": "0x1a6,0x1a7",
0222 "MSRValue": "0x300400001",
0223 "Offcore": "1",
0224 "SampleAfterValue": "100003",
0225 "UMask": "0x1"
0226 },
0227 {
0228 "BriefDescription": "Number of any page walk that had a miss in LLC.",
0229 "Counter": "0,1,2,3",
0230 "CounterHTOff": "0,1,2,3,4,5,6,7",
0231 "EventCode": "0xBE",
0232 "EventName": "PAGE_WALKS.LLC_MISS",
0233 "SampleAfterValue": "100003",
0234 "UMask": "0x1"
0235 }
0236 ]
