0001 [
0002 {
0003 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xE6",
0007 "EventName": "BACLEARS.ANY",
0008 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
0009 "SampleAfterValue": "100003",
0010 "UMask": "0x1f"
0011 },
0012 {
0013 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "EventCode": "0xAB",
0017 "EventName": "DSB2MITE_SWITCHES.COUNT",
0018 "PublicDescription": "Number of DSB to MITE switches.",
0019 "SampleAfterValue": "2000003",
0020 "UMask": "0x1"
0021 },
0022 {
0023 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
0024 "Counter": "0,1,2,3",
0025 "CounterHTOff": "0,1,2,3,4,5,6,7",
0026 "EventCode": "0xAB",
0027 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
0028 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
0029 "SampleAfterValue": "2000003",
0030 "UMask": "0x2"
0031 },
0032 {
0033 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
0034 "Counter": "0,1,2,3",
0035 "CounterHTOff": "0,1,2,3,4,5,6,7",
0036 "EventCode": "0xAC",
0037 "EventName": "DSB_FILL.EXCEED_DSB_LINES",
0038 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
0039 "SampleAfterValue": "2000003",
0040 "UMask": "0x8"
0041 },
0042 {
0043 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
0044 "Counter": "0,1,2,3",
0045 "CounterHTOff": "0,1,2,3,4,5,6,7",
0046 "EventCode": "0x80",
0047 "EventName": "ICACHE.HIT",
0048 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
0049 "SampleAfterValue": "2000003",
0050 "UMask": "0x1"
0051 },
0052 {
0053 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
0054 "Counter": "0,1,2,3",
0055 "CounterHTOff": "0,1,2,3,4,5,6,7",
0056 "EventCode": "0x80",
0057 "EventName": "ICACHE.IFETCH_STALL",
0058 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
0059 "SampleAfterValue": "2000003",
0060 "UMask": "0x4"
0061 },
0062 {
0063 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
0064 "Counter": "0,1,2,3",
0065 "CounterHTOff": "0,1,2,3,4,5,6,7",
0066 "EventCode": "0x80",
0067 "EventName": "ICACHE.MISSES",
0068 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
0069 "SampleAfterValue": "200003",
0070 "UMask": "0x2"
0071 },
0072 {
0073 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
0074 "Counter": "0,1,2,3",
0075 "CounterHTOff": "0,1,2,3,4,5,6,7",
0076 "CounterMask": "4",
0077 "EventCode": "0x79",
0078 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
0079 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
0080 "SampleAfterValue": "2000003",
0081 "UMask": "0x18"
0082 },
0083 {
0084 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
0085 "Counter": "0,1,2,3",
0086 "CounterHTOff": "0,1,2,3,4,5,6,7",
0087 "CounterMask": "1",
0088 "EventCode": "0x79",
0089 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
0090 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
0091 "SampleAfterValue": "2000003",
0092 "UMask": "0x18"
0093 },
0094 {
0095 "BriefDescription": "Cycles MITE is delivering 4 Uops",
0096 "Counter": "0,1,2,3",
0097 "CounterHTOff": "0,1,2,3,4,5,6,7",
0098 "CounterMask": "4",
0099 "EventCode": "0x79",
0100 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
0101 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
0102 "SampleAfterValue": "2000003",
0103 "UMask": "0x24"
0104 },
0105 {
0106 "BriefDescription": "Cycles MITE is delivering any Uop",
0107 "Counter": "0,1,2,3",
0108 "CounterHTOff": "0,1,2,3,4,5,6,7",
0109 "CounterMask": "1",
0110 "EventCode": "0x79",
0111 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
0112 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
0113 "SampleAfterValue": "2000003",
0114 "UMask": "0x24"
0115 },
0116 {
0117 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
0118 "Counter": "0,1,2,3",
0119 "CounterHTOff": "0,1,2,3,4,5,6,7",
0120 "CounterMask": "1",
0121 "EventCode": "0x79",
0122 "EventName": "IDQ.DSB_CYCLES",
0123 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
0124 "SampleAfterValue": "2000003",
0125 "UMask": "0x8"
0126 },
0127 {
0128 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
0129 "Counter": "0,1,2,3",
0130 "CounterHTOff": "0,1,2,3,4,5,6,7",
0131 "EventCode": "0x79",
0132 "EventName": "IDQ.DSB_UOPS",
0133 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
0134 "SampleAfterValue": "2000003",
0135 "UMask": "0x8"
0136 },
0137 {
0138 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
0139 "Counter": "0,1,2,3",
0140 "CounterHTOff": "0,1,2,3",
0141 "EventCode": "0x79",
0142 "EventName": "IDQ.EMPTY",
0143 "PublicDescription": "Counts cycles the IDQ is empty.",
0144 "SampleAfterValue": "2000003",
0145 "UMask": "0x2"
0146 },
0147 {
0148 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
0149 "Counter": "0,1,2,3",
0150 "CounterHTOff": "0,1,2,3,4,5,6,7",
0151 "EventCode": "0x79",
0152 "EventName": "IDQ.MITE_ALL_UOPS",
0153 "PublicDescription": "Number of uops delivered to IDQ from any path.",
0154 "SampleAfterValue": "2000003",
0155 "UMask": "0x3c"
0156 },
0157 {
0158 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
0159 "Counter": "0,1,2,3",
0160 "CounterHTOff": "0,1,2,3,4,5,6,7",
0161 "CounterMask": "1",
0162 "EventCode": "0x79",
0163 "EventName": "IDQ.MITE_CYCLES",
0164 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
0165 "SampleAfterValue": "2000003",
0166 "UMask": "0x4"
0167 },
0168 {
0169 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
0170 "Counter": "0,1,2,3",
0171 "CounterHTOff": "0,1,2,3,4,5,6,7",
0172 "EventCode": "0x79",
0173 "EventName": "IDQ.MITE_UOPS",
0174 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
0175 "SampleAfterValue": "2000003",
0176 "UMask": "0x4"
0177 },
0178 {
0179 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
0180 "Counter": "0,1,2,3",
0181 "CounterHTOff": "0,1,2,3,4,5,6,7",
0182 "CounterMask": "1",
0183 "EventCode": "0x79",
0184 "EventName": "IDQ.MS_CYCLES",
0185 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
0186 "SampleAfterValue": "2000003",
0187 "UMask": "0x30"
0188 },
0189 {
0190 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
0191 "Counter": "0,1,2,3",
0192 "CounterHTOff": "0,1,2,3,4,5,6,7",
0193 "CounterMask": "1",
0194 "EventCode": "0x79",
0195 "EventName": "IDQ.MS_DSB_CYCLES",
0196 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
0197 "SampleAfterValue": "2000003",
0198 "UMask": "0x10"
0199 },
0200 {
0201 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
0202 "Counter": "0,1,2,3",
0203 "CounterHTOff": "0,1,2,3,4,5,6,7",
0204 "CounterMask": "1",
0205 "EdgeDetect": "1",
0206 "EventCode": "0x79",
0207 "EventName": "IDQ.MS_DSB_OCCUR",
0208 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
0209 "SampleAfterValue": "2000003",
0210 "UMask": "0x10"
0211 },
0212 {
0213 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
0214 "Counter": "0,1,2,3",
0215 "CounterHTOff": "0,1,2,3,4,5,6,7",
0216 "EventCode": "0x79",
0217 "EventName": "IDQ.MS_DSB_UOPS",
0218 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
0219 "SampleAfterValue": "2000003",
0220 "UMask": "0x10"
0221 },
0222 {
0223 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
0224 "Counter": "0,1,2,3",
0225 "CounterHTOff": "0,1,2,3,4,5,6,7",
0226 "EventCode": "0x79",
0227 "EventName": "IDQ.MS_MITE_UOPS",
0228 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
0229 "SampleAfterValue": "2000003",
0230 "UMask": "0x20"
0231 },
0232 {
0233 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
0234 "Counter": "0,1,2,3",
0235 "CounterHTOff": "0,1,2,3,4,5,6,7",
0236 "CounterMask": "1",
0237 "EdgeDetect": "1",
0238 "EventCode": "0x79",
0239 "EventName": "IDQ.MS_SWITCHES",
0240 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
0241 "SampleAfterValue": "2000003",
0242 "UMask": "0x30"
0243 },
0244 {
0245 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
0246 "Counter": "0,1,2,3",
0247 "CounterHTOff": "0,1,2,3,4,5,6,7",
0248 "EventCode": "0x79",
0249 "EventName": "IDQ.MS_UOPS",
0250 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
0251 "SampleAfterValue": "2000003",
0252 "UMask": "0x30"
0253 },
0254 {
0255 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
0256 "Counter": "0,1,2,3",
0257 "CounterHTOff": "0,1,2,3",
0258 "EventCode": "0x9C",
0259 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
0260 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
0261 "SampleAfterValue": "2000003",
0262 "UMask": "0x1"
0263 },
0264 {
0265 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
0266 "Counter": "0,1,2,3",
0267 "CounterHTOff": "0,1,2,3",
0268 "CounterMask": "4",
0269 "EventCode": "0x9C",
0270 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
0271 "SampleAfterValue": "2000003",
0272 "UMask": "0x1"
0273 },
0274 {
0275 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
0276 "Counter": "0,1,2,3",
0277 "CounterHTOff": "0,1,2,3",
0278 "CounterMask": "1",
0279 "EventCode": "0x9C",
0280 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
0281 "Invert": "1",
0282 "SampleAfterValue": "2000003",
0283 "UMask": "0x1"
0284 },
0285 {
0286 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
0287 "Counter": "0,1,2,3",
0288 "CounterHTOff": "0,1,2,3",
0289 "CounterMask": "3",
0290 "EventCode": "0x9C",
0291 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
0292 "SampleAfterValue": "2000003",
0293 "UMask": "0x1"
0294 },
0295 {
0296 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
0297 "Counter": "0,1,2,3",
0298 "CounterHTOff": "0,1,2,3",
0299 "CounterMask": "2",
0300 "EventCode": "0x9C",
0301 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
0302 "SampleAfterValue": "2000003",
0303 "UMask": "0x1"
0304 },
0305 {
0306 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
0307 "Counter": "0,1,2,3",
0308 "CounterHTOff": "0,1,2,3",
0309 "CounterMask": "1",
0310 "EventCode": "0x9C",
0311 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
0312 "SampleAfterValue": "2000003",
0313 "UMask": "0x1"
0314 }
0315 ]
