0001 [
0002 {
0003 "BriefDescription": "Counts all microcode FP assists.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xc1",
0007 "EventName": "ASSISTS.FP",
0008 "PEBScounters": "0,1,2,3,4,5,6,7",
0009 "PublicDescription": "Counts all microcode Floating Point assists.",
0010 "SampleAfterValue": "100003",
0011 "Speculative": "1",
0012 "UMask": "0x2"
0013 },
0014 {
0015 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5,6,7",
0018 "EventCode": "0xc7",
0019 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
0020 "PEBScounters": "0,1,2,3,4,5,6,7",
0021 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0022 "SampleAfterValue": "100003",
0023 "UMask": "0x4"
0024 },
0025 {
0026 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0027 "CollectPEBSRecord": "2",
0028 "Counter": "0,1,2,3,4,5,6,7",
0029 "EventCode": "0xc7",
0030 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
0031 "PEBScounters": "0,1,2,3,4,5,6,7",
0032 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0033 "SampleAfterValue": "100003",
0034 "UMask": "0x8"
0035 },
0036 {
0037 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0038 "CollectPEBSRecord": "2",
0039 "Counter": "0,1,2,3,4,5,6,7",
0040 "EventCode": "0xc7",
0041 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
0042 "PEBScounters": "0,1,2,3,4,5,6,7",
0043 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0044 "SampleAfterValue": "100003",
0045 "UMask": "0x10"
0046 },
0047 {
0048 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0049 "CollectPEBSRecord": "2",
0050 "Counter": "0,1,2,3,4,5,6,7",
0051 "EventCode": "0xc7",
0052 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
0053 "PEBScounters": "0,1,2,3,4,5,6,7",
0054 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0055 "SampleAfterValue": "100003",
0056 "UMask": "0x20"
0057 },
0058 {
0059 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0060 "CollectPEBSRecord": "2",
0061 "Counter": "0,1,2,3,4,5,6,7",
0062 "EventCode": "0xc7",
0063 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
0064 "PEBScounters": "0,1,2,3,4,5,6,7",
0065 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0066 "SampleAfterValue": "100003",
0067 "UMask": "0x40"
0068 },
0069 {
0070 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0071 "CollectPEBSRecord": "2",
0072 "Counter": "0,1,2,3,4,5,6,7",
0073 "EventCode": "0xc7",
0074 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
0075 "PEBScounters": "0,1,2,3,4,5,6,7",
0076 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0077 "SampleAfterValue": "100003",
0078 "UMask": "0x80"
0079 },
0080 {
0081 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0082 "CollectPEBSRecord": "2",
0083 "Counter": "0,1,2,3,4,5,6,7",
0084 "EventCode": "0xc7",
0085 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
0086 "PEBScounters": "0,1,2,3,4,5,6,7",
0087 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0088 "SampleAfterValue": "100003",
0089 "UMask": "0x1"
0090 },
0091 {
0092 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0093 "CollectPEBSRecord": "2",
0094 "Counter": "0,1,2,3,4,5,6,7",
0095 "EventCode": "0xc7",
0096 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
0097 "PEBScounters": "0,1,2,3,4,5,6,7",
0098 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
0099 "SampleAfterValue": "100003",
0100 "UMask": "0x2"
0101 }
0102 ]
