0001 [
0002 {
0003 "BriefDescription": "DRAM Activate Count; Activate due to Read",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0x1",
0006 "EventName": "UNC_M_ACT_COUNT.RD",
0007 "PerPkg": "1",
0008 "UMask": "0x1",
0009 "Unit": "iMC"
0010 },
0011 {
0012 "BriefDescription": "DRAM Activate Count; Activate due to Write",
0013 "Counter": "0,1,2,3",
0014 "EventCode": "0x1",
0015 "EventName": "UNC_M_ACT_COUNT.WR",
0016 "PerPkg": "1",
0017 "UMask": "0x2",
0018 "Unit": "iMC"
0019 },
0020 {
0021 "BriefDescription": "DRAM Activate Count; Activate due to Write",
0022 "Counter": "0,1,2,3",
0023 "EventCode": "0x1",
0024 "EventName": "UNC_M_ACT_COUNT.BYP",
0025 "PerPkg": "1",
0026 "UMask": "0x8",
0027 "Unit": "iMC"
0028 },
0029 {
0030 "BriefDescription": "ACT command issued by 2 cycle bypass",
0031 "Counter": "0,1,2,3",
0032 "EventCode": "0xA1",
0033 "EventName": "UNC_M_BYP_CMDS.ACT",
0034 "PerPkg": "1",
0035 "UMask": "0x1",
0036 "Unit": "iMC"
0037 },
0038 {
0039 "BriefDescription": "CAS command issued by 2 cycle bypass",
0040 "Counter": "0,1,2,3",
0041 "EventCode": "0xA1",
0042 "EventName": "UNC_M_BYP_CMDS.CAS",
0043 "PerPkg": "1",
0044 "UMask": "0x2",
0045 "Unit": "iMC"
0046 },
0047 {
0048 "BriefDescription": "PRE command issued by 2 cycle bypass",
0049 "Counter": "0,1,2,3",
0050 "EventCode": "0xA1",
0051 "EventName": "UNC_M_BYP_CMDS.PRE",
0052 "PerPkg": "1",
0053 "UMask": "0x4",
0054 "Unit": "iMC"
0055 },
0056 {
0057 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
0058 "Counter": "0,1,2,3",
0059 "EventCode": "0x4",
0060 "EventName": "UNC_M_CAS_COUNT.RD_REG",
0061 "PerPkg": "1",
0062 "UMask": "0x1",
0063 "Unit": "iMC"
0064 },
0065 {
0066 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
0067 "Counter": "0,1,2,3",
0068 "EventCode": "0x4",
0069 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
0070 "PerPkg": "1",
0071 "UMask": "0x2",
0072 "Unit": "iMC"
0073 },
0074 {
0075 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
0076 "Counter": "0,1,2,3",
0077 "EventCode": "0x4",
0078 "EventName": "LLC_MISSES.MEM_READ",
0079 "PerPkg": "1",
0080 "ScaleUnit": "64Bytes",
0081 "UMask": "0x3",
0082 "Unit": "iMC"
0083 },
0084 {
0085 "BriefDescription": "read requests to memory controller",
0086 "Counter": "0,1,2,3",
0087 "EventCode": "0x4",
0088 "EventName": "UNC_M_CAS_COUNT.RD",
0089 "PerPkg": "1",
0090 "ScaleUnit": "64Bytes",
0091 "UMask": "0x3",
0092 "Unit": "iMC"
0093 },
0094 {
0095 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
0096 "Counter": "0,1,2,3",
0097 "EventCode": "0x4",
0098 "EventName": "UNC_M_CAS_COUNT.WR_WMM",
0099 "PerPkg": "1",
0100 "UMask": "0x4",
0101 "Unit": "iMC"
0102 },
0103 {
0104 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
0105 "Counter": "0,1,2,3",
0106 "EventCode": "0x4",
0107 "EventName": "UNC_M_CAS_COUNT.WR_RMM",
0108 "PerPkg": "1",
0109 "UMask": "0x8",
0110 "Unit": "iMC"
0111 },
0112 {
0113 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
0114 "Counter": "0,1,2,3",
0115 "EventCode": "0x4",
0116 "EventName": "LLC_MISSES.MEM_WRITE",
0117 "PerPkg": "1",
0118 "ScaleUnit": "64Bytes",
0119 "UMask": "0xC",
0120 "Unit": "iMC"
0121 },
0122 {
0123 "BriefDescription": "write requests to memory controller",
0124 "Counter": "0,1,2,3",
0125 "EventCode": "0x4",
0126 "EventName": "UNC_M_CAS_COUNT.WR",
0127 "PerPkg": "1",
0128 "ScaleUnit": "64Bytes",
0129 "UMask": "0xC",
0130 "Unit": "iMC"
0131 },
0132 {
0133 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
0134 "Counter": "0,1,2,3",
0135 "EventCode": "0x4",
0136 "EventName": "UNC_M_CAS_COUNT.ALL",
0137 "PerPkg": "1",
0138 "UMask": "0xF",
0139 "Unit": "iMC"
0140 },
0141 {
0142 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
0143 "Counter": "0,1,2,3",
0144 "EventCode": "0x4",
0145 "EventName": "UNC_M_CAS_COUNT.RD_WMM",
0146 "PerPkg": "1",
0147 "UMask": "0x10",
0148 "Unit": "iMC"
0149 },
0150 {
0151 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
0152 "Counter": "0,1,2,3",
0153 "EventCode": "0x4",
0154 "EventName": "UNC_M_CAS_COUNT.RD_RMM",
0155 "PerPkg": "1",
0156 "UMask": "0x20",
0157 "Unit": "iMC"
0158 },
0159 {
0160 "BriefDescription": "DRAM Clockticks",
0161 "Counter": "0,1,2,3",
0162 "EventName": "UNC_M_CLOCKTICKS",
0163 "PerPkg": "1",
0164 "Unit": "iMC"
0165 },
0166 {
0167 "BriefDescription": "DRAM Precharge All Commands",
0168 "Counter": "0,1,2,3",
0169 "EventCode": "0x6",
0170 "EventName": "UNC_M_DRAM_PRE_ALL",
0171 "PerPkg": "1",
0172 "Unit": "iMC"
0173 },
0174 {
0175 "BriefDescription": "Number of DRAM Refreshes Issued",
0176 "Counter": "0,1,2,3",
0177 "EventCode": "0x5",
0178 "EventName": "UNC_M_DRAM_REFRESH.PANIC",
0179 "PerPkg": "1",
0180 "UMask": "0x2",
0181 "Unit": "iMC"
0182 },
0183 {
0184 "BriefDescription": "Number of DRAM Refreshes Issued",
0185 "Counter": "0,1,2,3",
0186 "EventCode": "0x5",
0187 "EventName": "UNC_M_DRAM_REFRESH.HIGH",
0188 "PerPkg": "1",
0189 "UMask": "0x4",
0190 "Unit": "iMC"
0191 },
0192 {
0193 "BriefDescription": "ECC Correctable Errors",
0194 "Counter": "0,1,2,3",
0195 "EventCode": "0x9",
0196 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
0197 "PerPkg": "1",
0198 "Unit": "iMC"
0199 },
0200 {
0201 "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
0202 "Counter": "0,1,2,3",
0203 "EventCode": "0x7",
0204 "EventName": "UNC_M_MAJOR_MODES.READ",
0205 "PerPkg": "1",
0206 "UMask": "0x1",
0207 "Unit": "iMC"
0208 },
0209 {
0210 "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
0211 "Counter": "0,1,2,3",
0212 "EventCode": "0x7",
0213 "EventName": "UNC_M_MAJOR_MODES.WRITE",
0214 "PerPkg": "1",
0215 "UMask": "0x2",
0216 "Unit": "iMC"
0217 },
0218 {
0219 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
0220 "Counter": "0,1,2,3",
0221 "EventCode": "0x7",
0222 "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
0223 "PerPkg": "1",
0224 "UMask": "0x4",
0225 "Unit": "iMC"
0226 },
0227 {
0228 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
0229 "Counter": "0,1,2,3",
0230 "EventCode": "0x7",
0231 "EventName": "UNC_M_MAJOR_MODES.ISOCH",
0232 "PerPkg": "1",
0233 "UMask": "0x8",
0234 "Unit": "iMC"
0235 },
0236 {
0237 "BriefDescription": "Channel DLLOFF Cycles",
0238 "Counter": "0,1,2,3",
0239 "EventCode": "0x84",
0240 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
0241 "PerPkg": "1",
0242 "Unit": "iMC"
0243 },
0244 {
0245 "BriefDescription": "Channel PPD Cycles",
0246 "Counter": "0,1,2,3",
0247 "EventCode": "0x85",
0248 "EventName": "UNC_M_POWER_CHANNEL_PPD",
0249 "PerPkg": "1",
0250 "Unit": "iMC"
0251 },
0252 {
0253 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0254 "Counter": "0,1,2,3",
0255 "EventCode": "0x83",
0256 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
0257 "PerPkg": "1",
0258 "UMask": "0x1",
0259 "Unit": "iMC"
0260 },
0261 {
0262 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0263 "Counter": "0,1,2,3",
0264 "EventCode": "0x83",
0265 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
0266 "PerPkg": "1",
0267 "UMask": "0x2",
0268 "Unit": "iMC"
0269 },
0270 {
0271 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0272 "Counter": "0,1,2,3",
0273 "EventCode": "0x83",
0274 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
0275 "PerPkg": "1",
0276 "UMask": "0x4",
0277 "Unit": "iMC"
0278 },
0279 {
0280 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0281 "Counter": "0,1,2,3",
0282 "EventCode": "0x83",
0283 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
0284 "PerPkg": "1",
0285 "UMask": "0x8",
0286 "Unit": "iMC"
0287 },
0288 {
0289 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0290 "Counter": "0,1,2,3",
0291 "EventCode": "0x83",
0292 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
0293 "PerPkg": "1",
0294 "UMask": "0x10",
0295 "Unit": "iMC"
0296 },
0297 {
0298 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0299 "Counter": "0,1,2,3",
0300 "EventCode": "0x83",
0301 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
0302 "PerPkg": "1",
0303 "UMask": "0x20",
0304 "Unit": "iMC"
0305 },
0306 {
0307 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0308 "Counter": "0,1,2,3",
0309 "EventCode": "0x83",
0310 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
0311 "PerPkg": "1",
0312 "UMask": "0x40",
0313 "Unit": "iMC"
0314 },
0315 {
0316 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0317 "Counter": "0,1,2,3",
0318 "EventCode": "0x83",
0319 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
0320 "PerPkg": "1",
0321 "UMask": "0x80",
0322 "Unit": "iMC"
0323 },
0324 {
0325 "BriefDescription": "Critical Throttle Cycles",
0326 "Counter": "0,1,2,3",
0327 "EventCode": "0x86",
0328 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
0329 "PerPkg": "1",
0330 "Unit": "iMC"
0331 },
0332 {
0333 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
0334 "Counter": "0,1,2,3",
0335 "EventCode": "0x42",
0336 "EventName": "UNC_M_POWER_PCU_THROTTLING",
0337 "PerPkg": "1",
0338 "Unit": "iMC"
0339 },
0340 {
0341 "BriefDescription": "Clock-Enabled Self-Refresh",
0342 "Counter": "0,1,2,3",
0343 "EventCode": "0x43",
0344 "EventName": "UNC_M_POWER_SELF_REFRESH",
0345 "PerPkg": "1",
0346 "Unit": "iMC"
0347 },
0348 {
0349 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0350 "Counter": "0,1,2,3",
0351 "EventCode": "0x41",
0352 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
0353 "PerPkg": "1",
0354 "UMask": "0x1",
0355 "Unit": "iMC"
0356 },
0357 {
0358 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0359 "Counter": "0,1,2,3",
0360 "EventCode": "0x41",
0361 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
0362 "PerPkg": "1",
0363 "UMask": "0x2",
0364 "Unit": "iMC"
0365 },
0366 {
0367 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0368 "Counter": "0,1,2,3",
0369 "EventCode": "0x41",
0370 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
0371 "PerPkg": "1",
0372 "UMask": "0x4",
0373 "Unit": "iMC"
0374 },
0375 {
0376 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0377 "Counter": "0,1,2,3",
0378 "EventCode": "0x41",
0379 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
0380 "PerPkg": "1",
0381 "UMask": "0x8",
0382 "Unit": "iMC"
0383 },
0384 {
0385 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0386 "Counter": "0,1,2,3",
0387 "EventCode": "0x41",
0388 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
0389 "PerPkg": "1",
0390 "UMask": "0x10",
0391 "Unit": "iMC"
0392 },
0393 {
0394 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0395 "Counter": "0,1,2,3",
0396 "EventCode": "0x41",
0397 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
0398 "PerPkg": "1",
0399 "UMask": "0x20",
0400 "Unit": "iMC"
0401 },
0402 {
0403 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0404 "Counter": "0,1,2,3",
0405 "EventCode": "0x41",
0406 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
0407 "PerPkg": "1",
0408 "UMask": "0x40",
0409 "Unit": "iMC"
0410 },
0411 {
0412 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0413 "Counter": "0,1,2,3",
0414 "EventCode": "0x41",
0415 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
0416 "PerPkg": "1",
0417 "UMask": "0x80",
0418 "Unit": "iMC"
0419 },
0420 {
0421 "BriefDescription": "Read Preemption Count; Read over Read Preemption",
0422 "Counter": "0,1,2,3",
0423 "EventCode": "0x8",
0424 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
0425 "PerPkg": "1",
0426 "UMask": "0x1",
0427 "Unit": "iMC"
0428 },
0429 {
0430 "BriefDescription": "Read Preemption Count; Read over Write Preemption",
0431 "Counter": "0,1,2,3",
0432 "EventCode": "0x8",
0433 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
0434 "PerPkg": "1",
0435 "UMask": "0x2",
0436 "Unit": "iMC"
0437 },
0438 {
0439 "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
0440 "Counter": "0,1,2,3",
0441 "EventCode": "0x2",
0442 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
0443 "PerPkg": "1",
0444 "UMask": "0x1",
0445 "Unit": "iMC"
0446 },
0447 {
0448 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
0449 "Counter": "0,1,2,3",
0450 "EventCode": "0x2",
0451 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
0452 "PerPkg": "1",
0453 "UMask": "0x2",
0454 "Unit": "iMC"
0455 },
0456 {
0457 "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
0458 "Counter": "0,1,2,3",
0459 "EventCode": "0x2",
0460 "EventName": "UNC_M_PRE_COUNT.RD",
0461 "PerPkg": "1",
0462 "UMask": "0x4",
0463 "Unit": "iMC"
0464 },
0465 {
0466 "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
0467 "Counter": "0,1,2,3",
0468 "EventCode": "0x2",
0469 "EventName": "UNC_M_PRE_COUNT.WR",
0470 "PerPkg": "1",
0471 "UMask": "0x8",
0472 "Unit": "iMC"
0473 },
0474 {
0475 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
0476 "Counter": "0,1,2,3",
0477 "EventCode": "0x2",
0478 "EventName": "UNC_M_PRE_COUNT.BYP",
0479 "PerPkg": "1",
0480 "UMask": "0x10",
0481 "Unit": "iMC"
0482 },
0483 {
0484 "BriefDescription": "Read CAS issued with LOW priority",
0485 "Counter": "0,1,2,3",
0486 "EventCode": "0xA0",
0487 "EventName": "UNC_M_RD_CAS_PRIO.LOW",
0488 "PerPkg": "1",
0489 "UMask": "0x1",
0490 "Unit": "iMC"
0491 },
0492 {
0493 "BriefDescription": "Read CAS issued with MEDIUM priority",
0494 "Counter": "0,1,2,3",
0495 "EventCode": "0xA0",
0496 "EventName": "UNC_M_RD_CAS_PRIO.MED",
0497 "PerPkg": "1",
0498 "UMask": "0x2",
0499 "Unit": "iMC"
0500 },
0501 {
0502 "BriefDescription": "Read CAS issued with HIGH priority",
0503 "Counter": "0,1,2,3",
0504 "EventCode": "0xA0",
0505 "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
0506 "PerPkg": "1",
0507 "UMask": "0x4",
0508 "Unit": "iMC"
0509 },
0510 {
0511 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
0512 "Counter": "0,1,2,3",
0513 "EventCode": "0xA0",
0514 "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
0515 "PerPkg": "1",
0516 "UMask": "0x8",
0517 "Unit": "iMC"
0518 },
0519 {
0520 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
0521 "Counter": "0,1,2,3",
0522 "EventCode": "0xB0",
0523 "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
0524 "PerPkg": "1",
0525 "UMask": "0x1",
0526 "Unit": "iMC"
0527 },
0528 {
0529 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
0530 "Counter": "0,1,2,3",
0531 "EventCode": "0xB0",
0532 "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
0533 "PerPkg": "1",
0534 "UMask": "0x2",
0535 "Unit": "iMC"
0536 },
0537 {
0538 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
0539 "Counter": "0,1,2,3",
0540 "EventCode": "0xB0",
0541 "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
0542 "PerPkg": "1",
0543 "UMask": "0x4",
0544 "Unit": "iMC"
0545 },
0546 {
0547 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
0548 "Counter": "0,1,2,3",
0549 "EventCode": "0xB0",
0550 "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
0551 "PerPkg": "1",
0552 "UMask": "0x8",
0553 "Unit": "iMC"
0554 },
0555 {
0556 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
0557 "Counter": "0,1,2,3",
0558 "EventCode": "0xB0",
0559 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
0560 "PerPkg": "1",
0561 "UMask": "0x10",
0562 "Unit": "iMC"
0563 },
0564 {
0565 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
0566 "Counter": "0,1,2,3",
0567 "EventCode": "0xB0",
0568 "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
0569 "PerPkg": "1",
0570 "Unit": "iMC"
0571 },
0572 {
0573 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
0574 "Counter": "0,1,2,3",
0575 "EventCode": "0xB0",
0576 "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
0577 "PerPkg": "1",
0578 "UMask": "0x3",
0579 "Unit": "iMC"
0580 },
0581 {
0582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
0583 "Counter": "0,1,2,3",
0584 "EventCode": "0xB0",
0585 "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
0586 "PerPkg": "1",
0587 "UMask": "0x5",
0588 "Unit": "iMC"
0589 },
0590 {
0591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
0592 "Counter": "0,1,2,3",
0593 "EventCode": "0xB0",
0594 "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
0595 "PerPkg": "1",
0596 "UMask": "0x6",
0597 "Unit": "iMC"
0598 },
0599 {
0600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
0601 "Counter": "0,1,2,3",
0602 "EventCode": "0xB0",
0603 "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
0604 "PerPkg": "1",
0605 "UMask": "0x7",
0606 "Unit": "iMC"
0607 },
0608 {
0609 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
0610 "Counter": "0,1,2,3",
0611 "EventCode": "0xB0",
0612 "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
0613 "PerPkg": "1",
0614 "UMask": "0x9",
0615 "Unit": "iMC"
0616 },
0617 {
0618 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
0619 "Counter": "0,1,2,3",
0620 "EventCode": "0xB0",
0621 "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
0622 "PerPkg": "1",
0623 "UMask": "0xA",
0624 "Unit": "iMC"
0625 },
0626 {
0627 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
0628 "Counter": "0,1,2,3",
0629 "EventCode": "0xB0",
0630 "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
0631 "PerPkg": "1",
0632 "UMask": "0xB",
0633 "Unit": "iMC"
0634 },
0635 {
0636 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
0637 "Counter": "0,1,2,3",
0638 "EventCode": "0xB0",
0639 "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
0640 "PerPkg": "1",
0641 "UMask": "0xC",
0642 "Unit": "iMC"
0643 },
0644 {
0645 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
0646 "Counter": "0,1,2,3",
0647 "EventCode": "0xB0",
0648 "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
0649 "PerPkg": "1",
0650 "UMask": "0xD",
0651 "Unit": "iMC"
0652 },
0653 {
0654 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
0655 "Counter": "0,1,2,3",
0656 "EventCode": "0xB0",
0657 "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
0658 "PerPkg": "1",
0659 "UMask": "0xE",
0660 "Unit": "iMC"
0661 },
0662 {
0663 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
0664 "Counter": "0,1,2,3",
0665 "EventCode": "0xB0",
0666 "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
0667 "PerPkg": "1",
0668 "UMask": "0xF",
0669 "Unit": "iMC"
0670 },
0671 {
0672 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
0673 "Counter": "0,1,2,3",
0674 "EventCode": "0xB0",
0675 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
0676 "PerPkg": "1",
0677 "UMask": "0x11",
0678 "Unit": "iMC"
0679 },
0680 {
0681 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
0682 "Counter": "0,1,2,3",
0683 "EventCode": "0xB0",
0684 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
0685 "PerPkg": "1",
0686 "UMask": "0x12",
0687 "Unit": "iMC"
0688 },
0689 {
0690 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
0691 "Counter": "0,1,2,3",
0692 "EventCode": "0xB0",
0693 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
0694 "PerPkg": "1",
0695 "UMask": "0x13",
0696 "Unit": "iMC"
0697 },
0698 {
0699 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
0700 "Counter": "0,1,2,3",
0701 "EventCode": "0xB0",
0702 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
0703 "PerPkg": "1",
0704 "UMask": "0x14",
0705 "Unit": "iMC"
0706 },
0707 {
0708 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
0709 "Counter": "0,1,2,3",
0710 "EventCode": "0xB1",
0711 "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
0712 "PerPkg": "1",
0713 "UMask": "0x1",
0714 "Unit": "iMC"
0715 },
0716 {
0717 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
0718 "Counter": "0,1,2,3",
0719 "EventCode": "0xB1",
0720 "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
0721 "PerPkg": "1",
0722 "UMask": "0x2",
0723 "Unit": "iMC"
0724 },
0725 {
0726 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
0727 "Counter": "0,1,2,3",
0728 "EventCode": "0xB1",
0729 "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
0730 "PerPkg": "1",
0731 "UMask": "0x4",
0732 "Unit": "iMC"
0733 },
0734 {
0735 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
0736 "Counter": "0,1,2,3",
0737 "EventCode": "0xB1",
0738 "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
0739 "PerPkg": "1",
0740 "UMask": "0x8",
0741 "Unit": "iMC"
0742 },
0743 {
0744 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
0745 "Counter": "0,1,2,3",
0746 "EventCode": "0xB1",
0747 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
0748 "PerPkg": "1",
0749 "UMask": "0x10",
0750 "Unit": "iMC"
0751 },
0752 {
0753 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
0754 "Counter": "0,1,2,3",
0755 "EventCode": "0xB1",
0756 "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
0757 "PerPkg": "1",
0758 "Unit": "iMC"
0759 },
0760 {
0761 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
0762 "Counter": "0,1,2,3",
0763 "EventCode": "0xB1",
0764 "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
0765 "PerPkg": "1",
0766 "UMask": "0x3",
0767 "Unit": "iMC"
0768 },
0769 {
0770 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
0771 "Counter": "0,1,2,3",
0772 "EventCode": "0xB1",
0773 "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
0774 "PerPkg": "1",
0775 "UMask": "0x5",
0776 "Unit": "iMC"
0777 },
0778 {
0779 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
0780 "Counter": "0,1,2,3",
0781 "EventCode": "0xB1",
0782 "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
0783 "PerPkg": "1",
0784 "UMask": "0x6",
0785 "Unit": "iMC"
0786 },
0787 {
0788 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
0789 "Counter": "0,1,2,3",
0790 "EventCode": "0xB1",
0791 "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
0792 "PerPkg": "1",
0793 "UMask": "0x7",
0794 "Unit": "iMC"
0795 },
0796 {
0797 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
0798 "Counter": "0,1,2,3",
0799 "EventCode": "0xB1",
0800 "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
0801 "PerPkg": "1",
0802 "UMask": "0x9",
0803 "Unit": "iMC"
0804 },
0805 {
0806 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
0807 "Counter": "0,1,2,3",
0808 "EventCode": "0xB1",
0809 "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
0810 "PerPkg": "1",
0811 "UMask": "0xA",
0812 "Unit": "iMC"
0813 },
0814 {
0815 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
0816 "Counter": "0,1,2,3",
0817 "EventCode": "0xB1",
0818 "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
0819 "PerPkg": "1",
0820 "UMask": "0xB",
0821 "Unit": "iMC"
0822 },
0823 {
0824 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
0825 "Counter": "0,1,2,3",
0826 "EventCode": "0xB1",
0827 "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
0828 "PerPkg": "1",
0829 "UMask": "0xC",
0830 "Unit": "iMC"
0831 },
0832 {
0833 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
0834 "Counter": "0,1,2,3",
0835 "EventCode": "0xB1",
0836 "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
0837 "PerPkg": "1",
0838 "UMask": "0xD",
0839 "Unit": "iMC"
0840 },
0841 {
0842 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
0843 "Counter": "0,1,2,3",
0844 "EventCode": "0xB1",
0845 "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
0846 "PerPkg": "1",
0847 "UMask": "0xE",
0848 "Unit": "iMC"
0849 },
0850 {
0851 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
0852 "Counter": "0,1,2,3",
0853 "EventCode": "0xB1",
0854 "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
0855 "PerPkg": "1",
0856 "UMask": "0xF",
0857 "Unit": "iMC"
0858 },
0859 {
0860 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
0861 "Counter": "0,1,2,3",
0862 "EventCode": "0xB1",
0863 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
0864 "PerPkg": "1",
0865 "UMask": "0x11",
0866 "Unit": "iMC"
0867 },
0868 {
0869 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
0870 "Counter": "0,1,2,3",
0871 "EventCode": "0xB1",
0872 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
0873 "PerPkg": "1",
0874 "UMask": "0x12",
0875 "Unit": "iMC"
0876 },
0877 {
0878 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
0879 "Counter": "0,1,2,3",
0880 "EventCode": "0xB1",
0881 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
0882 "PerPkg": "1",
0883 "UMask": "0x13",
0884 "Unit": "iMC"
0885 },
0886 {
0887 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
0888 "Counter": "0,1,2,3",
0889 "EventCode": "0xB1",
0890 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
0891 "PerPkg": "1",
0892 "UMask": "0x14",
0893 "Unit": "iMC"
0894 },
0895 {
0896 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
0897 "Counter": "0,1,2,3",
0898 "EventCode": "0xB2",
0899 "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
0900 "PerPkg": "1",
0901 "Unit": "iMC"
0902 },
0903 {
0904 "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
0905 "Counter": "0,1,2,3",
0906 "EventCode": "0xB4",
0907 "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
0908 "PerPkg": "1",
0909 "UMask": "0x1",
0910 "Unit": "iMC"
0911 },
0912 {
0913 "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
0914 "Counter": "0,1,2,3",
0915 "EventCode": "0xB4",
0916 "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
0917 "PerPkg": "1",
0918 "UMask": "0x2",
0919 "Unit": "iMC"
0920 },
0921 {
0922 "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
0923 "Counter": "0,1,2,3",
0924 "EventCode": "0xB4",
0925 "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
0926 "PerPkg": "1",
0927 "UMask": "0x4",
0928 "Unit": "iMC"
0929 },
0930 {
0931 "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
0932 "Counter": "0,1,2,3",
0933 "EventCode": "0xB4",
0934 "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
0935 "PerPkg": "1",
0936 "UMask": "0x8",
0937 "Unit": "iMC"
0938 },
0939 {
0940 "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
0941 "Counter": "0,1,2,3",
0942 "EventCode": "0xB4",
0943 "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
0944 "PerPkg": "1",
0945 "UMask": "0x10",
0946 "Unit": "iMC"
0947 },
0948 {
0949 "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
0950 "Counter": "0,1,2,3",
0951 "EventCode": "0xB4",
0952 "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
0953 "PerPkg": "1",
0954 "Unit": "iMC"
0955 },
0956 {
0957 "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
0958 "Counter": "0,1,2,3",
0959 "EventCode": "0xB4",
0960 "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
0961 "PerPkg": "1",
0962 "UMask": "0x3",
0963 "Unit": "iMC"
0964 },
0965 {
0966 "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
0967 "Counter": "0,1,2,3",
0968 "EventCode": "0xB4",
0969 "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
0970 "PerPkg": "1",
0971 "UMask": "0x5",
0972 "Unit": "iMC"
0973 },
0974 {
0975 "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
0976 "Counter": "0,1,2,3",
0977 "EventCode": "0xB4",
0978 "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
0979 "PerPkg": "1",
0980 "UMask": "0x6",
0981 "Unit": "iMC"
0982 },
0983 {
0984 "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
0985 "Counter": "0,1,2,3",
0986 "EventCode": "0xB4",
0987 "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
0988 "PerPkg": "1",
0989 "UMask": "0x7",
0990 "Unit": "iMC"
0991 },
0992 {
0993 "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
0994 "Counter": "0,1,2,3",
0995 "EventCode": "0xB4",
0996 "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
0997 "PerPkg": "1",
0998 "UMask": "0x9",
0999 "Unit": "iMC"
1000 },
1001 {
1002 "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
1003 "Counter": "0,1,2,3",
1004 "EventCode": "0xB4",
1005 "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
1006 "PerPkg": "1",
1007 "UMask": "0xA",
1008 "Unit": "iMC"
1009 },
1010 {
1011 "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
1012 "Counter": "0,1,2,3",
1013 "EventCode": "0xB4",
1014 "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
1015 "PerPkg": "1",
1016 "UMask": "0xB",
1017 "Unit": "iMC"
1018 },
1019 {
1020 "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
1021 "Counter": "0,1,2,3",
1022 "EventCode": "0xB4",
1023 "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
1024 "PerPkg": "1",
1025 "UMask": "0xC",
1026 "Unit": "iMC"
1027 },
1028 {
1029 "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
1030 "Counter": "0,1,2,3",
1031 "EventCode": "0xB4",
1032 "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
1033 "PerPkg": "1",
1034 "UMask": "0xD",
1035 "Unit": "iMC"
1036 },
1037 {
1038 "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
1039 "Counter": "0,1,2,3",
1040 "EventCode": "0xB4",
1041 "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
1042 "PerPkg": "1",
1043 "UMask": "0xE",
1044 "Unit": "iMC"
1045 },
1046 {
1047 "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
1048 "Counter": "0,1,2,3",
1049 "EventCode": "0xB4",
1050 "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
1051 "PerPkg": "1",
1052 "UMask": "0xF",
1053 "Unit": "iMC"
1054 },
1055 {
1056 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
1057 "Counter": "0,1,2,3",
1058 "EventCode": "0xB4",
1059 "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
1060 "PerPkg": "1",
1061 "UMask": "0x11",
1062 "Unit": "iMC"
1063 },
1064 {
1065 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
1066 "Counter": "0,1,2,3",
1067 "EventCode": "0xB4",
1068 "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
1069 "PerPkg": "1",
1070 "UMask": "0x12",
1071 "Unit": "iMC"
1072 },
1073 {
1074 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
1075 "Counter": "0,1,2,3",
1076 "EventCode": "0xB4",
1077 "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
1078 "PerPkg": "1",
1079 "UMask": "0x13",
1080 "Unit": "iMC"
1081 },
1082 {
1083 "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
1084 "Counter": "0,1,2,3",
1085 "EventCode": "0xB4",
1086 "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
1087 "PerPkg": "1",
1088 "UMask": "0x14",
1089 "Unit": "iMC"
1090 },
1091 {
1092 "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
1093 "Counter": "0,1,2,3",
1094 "EventCode": "0xB5",
1095 "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
1096 "PerPkg": "1",
1097 "UMask": "0x1",
1098 "Unit": "iMC"
1099 },
1100 {
1101 "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
1102 "Counter": "0,1,2,3",
1103 "EventCode": "0xB5",
1104 "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
1105 "PerPkg": "1",
1106 "UMask": "0x2",
1107 "Unit": "iMC"
1108 },
1109 {
1110 "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
1111 "Counter": "0,1,2,3",
1112 "EventCode": "0xB5",
1113 "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
1114 "PerPkg": "1",
1115 "UMask": "0x4",
1116 "Unit": "iMC"
1117 },
1118 {
1119 "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
1120 "Counter": "0,1,2,3",
1121 "EventCode": "0xB5",
1122 "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
1123 "PerPkg": "1",
1124 "UMask": "0x8",
1125 "Unit": "iMC"
1126 },
1127 {
1128 "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
1129 "Counter": "0,1,2,3",
1130 "EventCode": "0xB5",
1131 "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
1132 "PerPkg": "1",
1133 "UMask": "0x10",
1134 "Unit": "iMC"
1135 },
1136 {
1137 "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
1138 "Counter": "0,1,2,3",
1139 "EventCode": "0xB5",
1140 "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
1141 "PerPkg": "1",
1142 "Unit": "iMC"
1143 },
1144 {
1145 "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
1146 "Counter": "0,1,2,3",
1147 "EventCode": "0xB5",
1148 "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
1149 "PerPkg": "1",
1150 "UMask": "0x3",
1151 "Unit": "iMC"
1152 },
1153 {
1154 "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
1155 "Counter": "0,1,2,3",
1156 "EventCode": "0xB5",
1157 "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
1158 "PerPkg": "1",
1159 "UMask": "0x5",
1160 "Unit": "iMC"
1161 },
1162 {
1163 "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
1164 "Counter": "0,1,2,3",
1165 "EventCode": "0xB5",
1166 "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
1167 "PerPkg": "1",
1168 "UMask": "0x6",
1169 "Unit": "iMC"
1170 },
1171 {
1172 "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
1173 "Counter": "0,1,2,3",
1174 "EventCode": "0xB5",
1175 "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
1176 "PerPkg": "1",
1177 "UMask": "0x7",
1178 "Unit": "iMC"
1179 },
1180 {
1181 "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
1182 "Counter": "0,1,2,3",
1183 "EventCode": "0xB5",
1184 "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
1185 "PerPkg": "1",
1186 "UMask": "0x9",
1187 "Unit": "iMC"
1188 },
1189 {
1190 "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
1191 "Counter": "0,1,2,3",
1192 "EventCode": "0xB5",
1193 "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
1194 "PerPkg": "1",
1195 "UMask": "0xA",
1196 "Unit": "iMC"
1197 },
1198 {
1199 "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
1200 "Counter": "0,1,2,3",
1201 "EventCode": "0xB5",
1202 "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
1203 "PerPkg": "1",
1204 "UMask": "0xB",
1205 "Unit": "iMC"
1206 },
1207 {
1208 "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
1209 "Counter": "0,1,2,3",
1210 "EventCode": "0xB5",
1211 "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
1212 "PerPkg": "1",
1213 "UMask": "0xC",
1214 "Unit": "iMC"
1215 },
1216 {
1217 "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
1218 "Counter": "0,1,2,3",
1219 "EventCode": "0xB5",
1220 "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
1221 "PerPkg": "1",
1222 "UMask": "0xD",
1223 "Unit": "iMC"
1224 },
1225 {
1226 "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
1227 "Counter": "0,1,2,3",
1228 "EventCode": "0xB5",
1229 "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
1230 "PerPkg": "1",
1231 "UMask": "0xE",
1232 "Unit": "iMC"
1233 },
1234 {
1235 "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
1236 "Counter": "0,1,2,3",
1237 "EventCode": "0xB5",
1238 "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
1239 "PerPkg": "1",
1240 "UMask": "0xF",
1241 "Unit": "iMC"
1242 },
1243 {
1244 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
1245 "Counter": "0,1,2,3",
1246 "EventCode": "0xB5",
1247 "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
1248 "PerPkg": "1",
1249 "UMask": "0x11",
1250 "Unit": "iMC"
1251 },
1252 {
1253 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
1254 "Counter": "0,1,2,3",
1255 "EventCode": "0xB5",
1256 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
1257 "PerPkg": "1",
1258 "UMask": "0x12",
1259 "Unit": "iMC"
1260 },
1261 {
1262 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
1263 "Counter": "0,1,2,3",
1264 "EventCode": "0xB5",
1265 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
1266 "PerPkg": "1",
1267 "UMask": "0x13",
1268 "Unit": "iMC"
1269 },
1270 {
1271 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
1272 "Counter": "0,1,2,3",
1273 "EventCode": "0xB5",
1274 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
1275 "PerPkg": "1",
1276 "UMask": "0x14",
1277 "Unit": "iMC"
1278 },
1279 {
1280 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
1281 "Counter": "0,1,2,3",
1282 "EventCode": "0xB6",
1283 "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
1284 "PerPkg": "1",
1285 "UMask": "0x1",
1286 "Unit": "iMC"
1287 },
1288 {
1289 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
1290 "Counter": "0,1,2,3",
1291 "EventCode": "0xB6",
1292 "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
1293 "PerPkg": "1",
1294 "UMask": "0x2",
1295 "Unit": "iMC"
1296 },
1297 {
1298 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
1299 "Counter": "0,1,2,3",
1300 "EventCode": "0xB6",
1301 "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
1302 "PerPkg": "1",
1303 "UMask": "0x4",
1304 "Unit": "iMC"
1305 },
1306 {
1307 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
1308 "Counter": "0,1,2,3",
1309 "EventCode": "0xB6",
1310 "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
1311 "PerPkg": "1",
1312 "UMask": "0x8",
1313 "Unit": "iMC"
1314 },
1315 {
1316 "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
1317 "Counter": "0,1,2,3",
1318 "EventCode": "0xB6",
1319 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
1320 "PerPkg": "1",
1321 "UMask": "0x10",
1322 "Unit": "iMC"
1323 },
1324 {
1325 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
1326 "Counter": "0,1,2,3",
1327 "EventCode": "0xB6",
1328 "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
1329 "PerPkg": "1",
1330 "Unit": "iMC"
1331 },
1332 {
1333 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
1334 "Counter": "0,1,2,3",
1335 "EventCode": "0xB6",
1336 "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
1337 "PerPkg": "1",
1338 "UMask": "0x3",
1339 "Unit": "iMC"
1340 },
1341 {
1342 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
1343 "Counter": "0,1,2,3",
1344 "EventCode": "0xB6",
1345 "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
1346 "PerPkg": "1",
1347 "UMask": "0x5",
1348 "Unit": "iMC"
1349 },
1350 {
1351 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
1352 "Counter": "0,1,2,3",
1353 "EventCode": "0xB6",
1354 "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
1355 "PerPkg": "1",
1356 "UMask": "0x6",
1357 "Unit": "iMC"
1358 },
1359 {
1360 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
1361 "Counter": "0,1,2,3",
1362 "EventCode": "0xB6",
1363 "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
1364 "PerPkg": "1",
1365 "UMask": "0x7",
1366 "Unit": "iMC"
1367 },
1368 {
1369 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
1370 "Counter": "0,1,2,3",
1371 "EventCode": "0xB6",
1372 "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
1373 "PerPkg": "1",
1374 "UMask": "0x9",
1375 "Unit": "iMC"
1376 },
1377 {
1378 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
1379 "Counter": "0,1,2,3",
1380 "EventCode": "0xB6",
1381 "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
1382 "PerPkg": "1",
1383 "UMask": "0xA",
1384 "Unit": "iMC"
1385 },
1386 {
1387 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
1388 "Counter": "0,1,2,3",
1389 "EventCode": "0xB6",
1390 "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
1391 "PerPkg": "1",
1392 "UMask": "0xB",
1393 "Unit": "iMC"
1394 },
1395 {
1396 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
1397 "Counter": "0,1,2,3",
1398 "EventCode": "0xB6",
1399 "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
1400 "PerPkg": "1",
1401 "UMask": "0xC",
1402 "Unit": "iMC"
1403 },
1404 {
1405 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
1406 "Counter": "0,1,2,3",
1407 "EventCode": "0xB6",
1408 "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
1409 "PerPkg": "1",
1410 "UMask": "0xD",
1411 "Unit": "iMC"
1412 },
1413 {
1414 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
1415 "Counter": "0,1,2,3",
1416 "EventCode": "0xB6",
1417 "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
1418 "PerPkg": "1",
1419 "UMask": "0xE",
1420 "Unit": "iMC"
1421 },
1422 {
1423 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
1424 "Counter": "0,1,2,3",
1425 "EventCode": "0xB6",
1426 "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
1427 "PerPkg": "1",
1428 "UMask": "0xF",
1429 "Unit": "iMC"
1430 },
1431 {
1432 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
1433 "Counter": "0,1,2,3",
1434 "EventCode": "0xB6",
1435 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
1436 "PerPkg": "1",
1437 "UMask": "0x11",
1438 "Unit": "iMC"
1439 },
1440 {
1441 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
1442 "Counter": "0,1,2,3",
1443 "EventCode": "0xB6",
1444 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
1445 "PerPkg": "1",
1446 "UMask": "0x12",
1447 "Unit": "iMC"
1448 },
1449 {
1450 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
1451 "Counter": "0,1,2,3",
1452 "EventCode": "0xB6",
1453 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
1454 "PerPkg": "1",
1455 "UMask": "0x13",
1456 "Unit": "iMC"
1457 },
1458 {
1459 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
1460 "Counter": "0,1,2,3",
1461 "EventCode": "0xB6",
1462 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
1463 "PerPkg": "1",
1464 "UMask": "0x14",
1465 "Unit": "iMC"
1466 },
1467 {
1468 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
1469 "Counter": "0,1,2,3",
1470 "EventCode": "0xB7",
1471 "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
1472 "PerPkg": "1",
1473 "UMask": "0x1",
1474 "Unit": "iMC"
1475 },
1476 {
1477 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
1478 "Counter": "0,1,2,3",
1479 "EventCode": "0xB7",
1480 "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
1481 "PerPkg": "1",
1482 "UMask": "0x2",
1483 "Unit": "iMC"
1484 },
1485 {
1486 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
1487 "Counter": "0,1,2,3",
1488 "EventCode": "0xB7",
1489 "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
1490 "PerPkg": "1",
1491 "UMask": "0x4",
1492 "Unit": "iMC"
1493 },
1494 {
1495 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
1496 "Counter": "0,1,2,3",
1497 "EventCode": "0xB7",
1498 "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
1499 "PerPkg": "1",
1500 "UMask": "0x8",
1501 "Unit": "iMC"
1502 },
1503 {
1504 "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
1505 "Counter": "0,1,2,3",
1506 "EventCode": "0xB7",
1507 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
1508 "PerPkg": "1",
1509 "UMask": "0x10",
1510 "Unit": "iMC"
1511 },
1512 {
1513 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
1514 "Counter": "0,1,2,3",
1515 "EventCode": "0xB7",
1516 "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
1517 "PerPkg": "1",
1518 "Unit": "iMC"
1519 },
1520 {
1521 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
1522 "Counter": "0,1,2,3",
1523 "EventCode": "0xB7",
1524 "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
1525 "PerPkg": "1",
1526 "UMask": "0x3",
1527 "Unit": "iMC"
1528 },
1529 {
1530 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
1531 "Counter": "0,1,2,3",
1532 "EventCode": "0xB7",
1533 "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
1534 "PerPkg": "1",
1535 "UMask": "0x5",
1536 "Unit": "iMC"
1537 },
1538 {
1539 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
1540 "Counter": "0,1,2,3",
1541 "EventCode": "0xB7",
1542 "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
1543 "PerPkg": "1",
1544 "UMask": "0x6",
1545 "Unit": "iMC"
1546 },
1547 {
1548 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
1549 "Counter": "0,1,2,3",
1550 "EventCode": "0xB7",
1551 "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
1552 "PerPkg": "1",
1553 "UMask": "0x7",
1554 "Unit": "iMC"
1555 },
1556 {
1557 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
1558 "Counter": "0,1,2,3",
1559 "EventCode": "0xB7",
1560 "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
1561 "PerPkg": "1",
1562 "UMask": "0x9",
1563 "Unit": "iMC"
1564 },
1565 {
1566 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
1567 "Counter": "0,1,2,3",
1568 "EventCode": "0xB7",
1569 "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
1570 "PerPkg": "1",
1571 "UMask": "0xA",
1572 "Unit": "iMC"
1573 },
1574 {
1575 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
1576 "Counter": "0,1,2,3",
1577 "EventCode": "0xB7",
1578 "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
1579 "PerPkg": "1",
1580 "UMask": "0xB",
1581 "Unit": "iMC"
1582 },
1583 {
1584 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
1585 "Counter": "0,1,2,3",
1586 "EventCode": "0xB7",
1587 "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
1588 "PerPkg": "1",
1589 "UMask": "0xC",
1590 "Unit": "iMC"
1591 },
1592 {
1593 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
1594 "Counter": "0,1,2,3",
1595 "EventCode": "0xB7",
1596 "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
1597 "PerPkg": "1",
1598 "UMask": "0xD",
1599 "Unit": "iMC"
1600 },
1601 {
1602 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
1603 "Counter": "0,1,2,3",
1604 "EventCode": "0xB7",
1605 "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
1606 "PerPkg": "1",
1607 "UMask": "0xE",
1608 "Unit": "iMC"
1609 },
1610 {
1611 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
1612 "Counter": "0,1,2,3",
1613 "EventCode": "0xB7",
1614 "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
1615 "PerPkg": "1",
1616 "UMask": "0xF",
1617 "Unit": "iMC"
1618 },
1619 {
1620 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
1621 "Counter": "0,1,2,3",
1622 "EventCode": "0xB7",
1623 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
1624 "PerPkg": "1",
1625 "UMask": "0x11",
1626 "Unit": "iMC"
1627 },
1628 {
1629 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
1630 "Counter": "0,1,2,3",
1631 "EventCode": "0xB7",
1632 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
1633 "PerPkg": "1",
1634 "UMask": "0x12",
1635 "Unit": "iMC"
1636 },
1637 {
1638 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
1639 "Counter": "0,1,2,3",
1640 "EventCode": "0xB7",
1641 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
1642 "PerPkg": "1",
1643 "UMask": "0x13",
1644 "Unit": "iMC"
1645 },
1646 {
1647 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
1648 "Counter": "0,1,2,3",
1649 "EventCode": "0xB7",
1650 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
1651 "PerPkg": "1",
1652 "UMask": "0x14",
1653 "Unit": "iMC"
1654 },
1655 {
1656 "BriefDescription": "Read Pending Queue Not Empty",
1657 "Counter": "0,1,2,3",
1658 "EventCode": "0x11",
1659 "EventName": "UNC_M_RPQ_CYCLES_NE",
1660 "PerPkg": "1",
1661 "Unit": "iMC"
1662 },
1663 {
1664 "BriefDescription": "Read Pending Queue Allocations",
1665 "Counter": "0,1,2,3",
1666 "EventCode": "0x10",
1667 "EventName": "UNC_M_RPQ_INSERTS",
1668 "PerPkg": "1",
1669 "Unit": "iMC"
1670 },
1671 {
1672 "BriefDescription": "VMSE MXB write buffer occupancy",
1673 "Counter": "0,1,2,3",
1674 "EventCode": "0x91",
1675 "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
1676 "PerPkg": "1",
1677 "Unit": "iMC"
1678 },
1679 {
1680 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
1681 "Counter": "0,1,2,3",
1682 "EventCode": "0x90",
1683 "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
1684 "PerPkg": "1",
1685 "UMask": "0x1",
1686 "Unit": "iMC"
1687 },
1688 {
1689 "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
1690 "Counter": "0,1,2,3",
1691 "EventCode": "0x90",
1692 "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
1693 "PerPkg": "1",
1694 "UMask": "0x2",
1695 "Unit": "iMC"
1696 },
1697 {
1698 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
1699 "Counter": "0,1,2,3",
1700 "EventCode": "0xC0",
1701 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
1702 "PerPkg": "1",
1703 "UMask": "0x1",
1704 "Unit": "iMC"
1705 },
1706 {
1707 "BriefDescription": "Transition from WMM to RMM because of low threshold",
1708 "Counter": "0,1,2,3",
1709 "EventCode": "0xC0",
1710 "EventName": "UNC_M_WMM_TO_RMM.STARVE",
1711 "PerPkg": "1",
1712 "UMask": "0x2",
1713 "Unit": "iMC"
1714 },
1715 {
1716 "BriefDescription": "Transition from WMM to RMM because of low threshold",
1717 "Counter": "0,1,2,3",
1718 "EventCode": "0xC0",
1719 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
1720 "PerPkg": "1",
1721 "UMask": "0x4",
1722 "Unit": "iMC"
1723 },
1724 {
1725 "BriefDescription": "Write Pending Queue Full Cycles",
1726 "Counter": "0,1,2,3",
1727 "EventCode": "0x22",
1728 "EventName": "UNC_M_WPQ_CYCLES_FULL",
1729 "PerPkg": "1",
1730 "Unit": "iMC"
1731 },
1732 {
1733 "BriefDescription": "Write Pending Queue Not Empty",
1734 "Counter": "0,1,2,3",
1735 "EventCode": "0x21",
1736 "EventName": "UNC_M_WPQ_CYCLES_NE",
1737 "PerPkg": "1",
1738 "Unit": "iMC"
1739 },
1740 {
1741 "BriefDescription": "Write Pending Queue CAM Match",
1742 "Counter": "0,1,2,3",
1743 "EventCode": "0x23",
1744 "EventName": "UNC_M_WPQ_READ_HIT",
1745 "PerPkg": "1",
1746 "Unit": "iMC"
1747 },
1748 {
1749 "BriefDescription": "Write Pending Queue CAM Match",
1750 "Counter": "0,1,2,3",
1751 "EventCode": "0x24",
1752 "EventName": "UNC_M_WPQ_WRITE_HIT",
1753 "PerPkg": "1",
1754 "Unit": "iMC"
1755 },
1756 {
1757 "BriefDescription": "Not getting the requested Major Mode",
1758 "Counter": "0,1,2,3",
1759 "EventCode": "0xC1",
1760 "EventName": "UNC_M_WRONG_MM",
1761 "PerPkg": "1",
1762 "Unit": "iMC"
1763 },
1764 {
1765 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
1766 "Counter": "0,1,2,3",
1767 "EventCode": "0xB8",
1768 "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
1769 "PerPkg": "1",
1770 "UMask": "0x1",
1771 "Unit": "iMC"
1772 },
1773 {
1774 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
1775 "Counter": "0,1,2,3",
1776 "EventCode": "0xB8",
1777 "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
1778 "PerPkg": "1",
1779 "UMask": "0x2",
1780 "Unit": "iMC"
1781 },
1782 {
1783 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
1784 "Counter": "0,1,2,3",
1785 "EventCode": "0xB8",
1786 "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
1787 "PerPkg": "1",
1788 "UMask": "0x4",
1789 "Unit": "iMC"
1790 },
1791 {
1792 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
1793 "Counter": "0,1,2,3",
1794 "EventCode": "0xB8",
1795 "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
1796 "PerPkg": "1",
1797 "UMask": "0x8",
1798 "Unit": "iMC"
1799 },
1800 {
1801 "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
1802 "Counter": "0,1,2,3",
1803 "EventCode": "0xB8",
1804 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
1805 "PerPkg": "1",
1806 "UMask": "0x10",
1807 "Unit": "iMC"
1808 },
1809 {
1810 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
1811 "Counter": "0,1,2,3",
1812 "EventCode": "0xB8",
1813 "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
1814 "PerPkg": "1",
1815 "Unit": "iMC"
1816 },
1817 {
1818 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
1819 "Counter": "0,1,2,3",
1820 "EventCode": "0xB8",
1821 "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
1822 "PerPkg": "1",
1823 "UMask": "0x3",
1824 "Unit": "iMC"
1825 },
1826 {
1827 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
1828 "Counter": "0,1,2,3",
1829 "EventCode": "0xB8",
1830 "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
1831 "PerPkg": "1",
1832 "UMask": "0x5",
1833 "Unit": "iMC"
1834 },
1835 {
1836 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
1837 "Counter": "0,1,2,3",
1838 "EventCode": "0xB8",
1839 "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
1840 "PerPkg": "1",
1841 "UMask": "0x6",
1842 "Unit": "iMC"
1843 },
1844 {
1845 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
1846 "Counter": "0,1,2,3",
1847 "EventCode": "0xB8",
1848 "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
1849 "PerPkg": "1",
1850 "UMask": "0x7",
1851 "Unit": "iMC"
1852 },
1853 {
1854 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
1855 "Counter": "0,1,2,3",
1856 "EventCode": "0xB8",
1857 "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
1858 "PerPkg": "1",
1859 "UMask": "0x9",
1860 "Unit": "iMC"
1861 },
1862 {
1863 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
1864 "Counter": "0,1,2,3",
1865 "EventCode": "0xB8",
1866 "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
1867 "PerPkg": "1",
1868 "UMask": "0xA",
1869 "Unit": "iMC"
1870 },
1871 {
1872 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
1873 "Counter": "0,1,2,3",
1874 "EventCode": "0xB8",
1875 "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
1876 "PerPkg": "1",
1877 "UMask": "0xB",
1878 "Unit": "iMC"
1879 },
1880 {
1881 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
1882 "Counter": "0,1,2,3",
1883 "EventCode": "0xB8",
1884 "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
1885 "PerPkg": "1",
1886 "UMask": "0xC",
1887 "Unit": "iMC"
1888 },
1889 {
1890 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
1891 "Counter": "0,1,2,3",
1892 "EventCode": "0xB8",
1893 "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
1894 "PerPkg": "1",
1895 "UMask": "0xD",
1896 "Unit": "iMC"
1897 },
1898 {
1899 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
1900 "Counter": "0,1,2,3",
1901 "EventCode": "0xB8",
1902 "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
1903 "PerPkg": "1",
1904 "UMask": "0xE",
1905 "Unit": "iMC"
1906 },
1907 {
1908 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
1909 "Counter": "0,1,2,3",
1910 "EventCode": "0xB8",
1911 "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
1912 "PerPkg": "1",
1913 "UMask": "0xF",
1914 "Unit": "iMC"
1915 },
1916 {
1917 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
1918 "Counter": "0,1,2,3",
1919 "EventCode": "0xB8",
1920 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
1921 "PerPkg": "1",
1922 "UMask": "0x11",
1923 "Unit": "iMC"
1924 },
1925 {
1926 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
1927 "Counter": "0,1,2,3",
1928 "EventCode": "0xB8",
1929 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
1930 "PerPkg": "1",
1931 "UMask": "0x12",
1932 "Unit": "iMC"
1933 },
1934 {
1935 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
1936 "Counter": "0,1,2,3",
1937 "EventCode": "0xB8",
1938 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
1939 "PerPkg": "1",
1940 "UMask": "0x13",
1941 "Unit": "iMC"
1942 },
1943 {
1944 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
1945 "Counter": "0,1,2,3",
1946 "EventCode": "0xB8",
1947 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
1948 "PerPkg": "1",
1949 "UMask": "0x14",
1950 "Unit": "iMC"
1951 },
1952 {
1953 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
1954 "Counter": "0,1,2,3",
1955 "EventCode": "0xB9",
1956 "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
1957 "PerPkg": "1",
1958 "UMask": "0x1",
1959 "Unit": "iMC"
1960 },
1961 {
1962 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
1963 "Counter": "0,1,2,3",
1964 "EventCode": "0xB9",
1965 "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
1966 "PerPkg": "1",
1967 "UMask": "0x2",
1968 "Unit": "iMC"
1969 },
1970 {
1971 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
1972 "Counter": "0,1,2,3",
1973 "EventCode": "0xB9",
1974 "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
1975 "PerPkg": "1",
1976 "UMask": "0x4",
1977 "Unit": "iMC"
1978 },
1979 {
1980 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
1981 "Counter": "0,1,2,3",
1982 "EventCode": "0xB9",
1983 "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
1984 "PerPkg": "1",
1985 "UMask": "0x8",
1986 "Unit": "iMC"
1987 },
1988 {
1989 "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
1990 "Counter": "0,1,2,3",
1991 "EventCode": "0xB9",
1992 "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
1993 "PerPkg": "1",
1994 "UMask": "0x10",
1995 "Unit": "iMC"
1996 },
1997 {
1998 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
1999 "Counter": "0,1,2,3",
2000 "EventCode": "0xB9",
2001 "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
2002 "PerPkg": "1",
2003 "Unit": "iMC"
2004 },
2005 {
2006 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
2007 "Counter": "0,1,2,3",
2008 "EventCode": "0xB9",
2009 "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
2010 "PerPkg": "1",
2011 "UMask": "0x3",
2012 "Unit": "iMC"
2013 },
2014 {
2015 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
2016 "Counter": "0,1,2,3",
2017 "EventCode": "0xB9",
2018 "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
2019 "PerPkg": "1",
2020 "UMask": "0x5",
2021 "Unit": "iMC"
2022 },
2023 {
2024 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
2025 "Counter": "0,1,2,3",
2026 "EventCode": "0xB9",
2027 "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
2028 "PerPkg": "1",
2029 "UMask": "0x6",
2030 "Unit": "iMC"
2031 },
2032 {
2033 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
2034 "Counter": "0,1,2,3",
2035 "EventCode": "0xB9",
2036 "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
2037 "PerPkg": "1",
2038 "UMask": "0x7",
2039 "Unit": "iMC"
2040 },
2041 {
2042 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
2043 "Counter": "0,1,2,3",
2044 "EventCode": "0xB9",
2045 "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
2046 "PerPkg": "1",
2047 "UMask": "0x9",
2048 "Unit": "iMC"
2049 },
2050 {
2051 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
2052 "Counter": "0,1,2,3",
2053 "EventCode": "0xB9",
2054 "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
2055 "PerPkg": "1",
2056 "UMask": "0xA",
2057 "Unit": "iMC"
2058 },
2059 {
2060 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
2061 "Counter": "0,1,2,3",
2062 "EventCode": "0xB9",
2063 "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
2064 "PerPkg": "1",
2065 "UMask": "0xB",
2066 "Unit": "iMC"
2067 },
2068 {
2069 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
2070 "Counter": "0,1,2,3",
2071 "EventCode": "0xB9",
2072 "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
2073 "PerPkg": "1",
2074 "UMask": "0xC",
2075 "Unit": "iMC"
2076 },
2077 {
2078 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
2079 "Counter": "0,1,2,3",
2080 "EventCode": "0xB9",
2081 "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
2082 "PerPkg": "1",
2083 "UMask": "0xD",
2084 "Unit": "iMC"
2085 },
2086 {
2087 "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
2088 "Counter": "0,1,2,3",
2089 "EventCode": "0xB9",
2090 "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
2091 "PerPkg": "1",
2092 "UMask": "0xE",
2093 "Unit": "iMC"
2094 },
2095 {
2096 "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
2097 "Counter": "0,1,2,3",
2098 "EventCode": "0xB9",
2099 "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
2100 "PerPkg": "1",
2101 "UMask": "0xF",
2102 "Unit": "iMC"
2103 },
2104 {
2105 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
2106 "Counter": "0,1,2,3",
2107 "EventCode": "0xB9",
2108 "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
2109 "PerPkg": "1",
2110 "UMask": "0x11",
2111 "Unit": "iMC"
2112 },
2113 {
2114 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
2115 "Counter": "0,1,2,3",
2116 "EventCode": "0xB9",
2117 "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
2118 "PerPkg": "1",
2119 "UMask": "0x12",
2120 "Unit": "iMC"
2121 },
2122 {
2123 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
2124 "Counter": "0,1,2,3",
2125 "EventCode": "0xB9",
2126 "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
2127 "PerPkg": "1",
2128 "UMask": "0x13",
2129 "Unit": "iMC"
2130 },
2131 {
2132 "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
2133 "Counter": "0,1,2,3",
2134 "EventCode": "0xB9",
2135 "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
2136 "PerPkg": "1",
2137 "UMask": "0x14",
2138 "Unit": "iMC"
2139 },
2140 {
2141 "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
2142 "Counter": "0,1,2,3",
2143 "EventCode": "0xBC",
2144 "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
2145 "PerPkg": "1",
2146 "UMask": "0x1",
2147 "Unit": "iMC"
2148 },
2149 {
2150 "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
2151 "Counter": "0,1,2,3",
2152 "EventCode": "0xBC",
2153 "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
2154 "PerPkg": "1",
2155 "UMask": "0x2",
2156 "Unit": "iMC"
2157 },
2158 {
2159 "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
2160 "Counter": "0,1,2,3",
2161 "EventCode": "0xBC",
2162 "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
2163 "PerPkg": "1",
2164 "UMask": "0x4",
2165 "Unit": "iMC"
2166 },
2167 {
2168 "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
2169 "Counter": "0,1,2,3",
2170 "EventCode": "0xBC",
2171 "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
2172 "PerPkg": "1",
2173 "UMask": "0x8",
2174 "Unit": "iMC"
2175 },
2176 {
2177 "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
2178 "Counter": "0,1,2,3",
2179 "EventCode": "0xBC",
2180 "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
2181 "PerPkg": "1",
2182 "UMask": "0x10",
2183 "Unit": "iMC"
2184 },
2185 {
2186 "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
2187 "Counter": "0,1,2,3",
2188 "EventCode": "0xBC",
2189 "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
2190 "PerPkg": "1",
2191 "Unit": "iMC"
2192 },
2193 {
2194 "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
2195 "Counter": "0,1,2,3",
2196 "EventCode": "0xBC",
2197 "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
2198 "PerPkg": "1",
2199 "UMask": "0x3",
2200 "Unit": "iMC"
2201 },
2202 {
2203 "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
2204 "Counter": "0,1,2,3",
2205 "EventCode": "0xBC",
2206 "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
2207 "PerPkg": "1",
2208 "UMask": "0x5",
2209 "Unit": "iMC"
2210 },
2211 {
2212 "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
2213 "Counter": "0,1,2,3",
2214 "EventCode": "0xBC",
2215 "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
2216 "PerPkg": "1",
2217 "UMask": "0x6",
2218 "Unit": "iMC"
2219 },
2220 {
2221 "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
2222 "Counter": "0,1,2,3",
2223 "EventCode": "0xBC",
2224 "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
2225 "PerPkg": "1",
2226 "UMask": "0x7",
2227 "Unit": "iMC"
2228 },
2229 {
2230 "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
2231 "Counter": "0,1,2,3",
2232 "EventCode": "0xBC",
2233 "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
2234 "PerPkg": "1",
2235 "UMask": "0x9",
2236 "Unit": "iMC"
2237 },
2238 {
2239 "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
2240 "Counter": "0,1,2,3",
2241 "EventCode": "0xBC",
2242 "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
2243 "PerPkg": "1",
2244 "UMask": "0xA",
2245 "Unit": "iMC"
2246 },
2247 {
2248 "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
2249 "Counter": "0,1,2,3",
2250 "EventCode": "0xBC",
2251 "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
2252 "PerPkg": "1",
2253 "UMask": "0xB",
2254 "Unit": "iMC"
2255 },
2256 {
2257 "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
2258 "Counter": "0,1,2,3",
2259 "EventCode": "0xBC",
2260 "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
2261 "PerPkg": "1",
2262 "UMask": "0xC",
2263 "Unit": "iMC"
2264 },
2265 {
2266 "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
2267 "Counter": "0,1,2,3",
2268 "EventCode": "0xBC",
2269 "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
2270 "PerPkg": "1",
2271 "UMask": "0xD",
2272 "Unit": "iMC"
2273 },
2274 {
2275 "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
2276 "Counter": "0,1,2,3",
2277 "EventCode": "0xBC",
2278 "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
2279 "PerPkg": "1",
2280 "UMask": "0xE",
2281 "Unit": "iMC"
2282 },
2283 {
2284 "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
2285 "Counter": "0,1,2,3",
2286 "EventCode": "0xBC",
2287 "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
2288 "PerPkg": "1",
2289 "UMask": "0xF",
2290 "Unit": "iMC"
2291 },
2292 {
2293 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
2294 "Counter": "0,1,2,3",
2295 "EventCode": "0xBC",
2296 "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
2297 "PerPkg": "1",
2298 "UMask": "0x11",
2299 "Unit": "iMC"
2300 },
2301 {
2302 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
2303 "Counter": "0,1,2,3",
2304 "EventCode": "0xBC",
2305 "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
2306 "PerPkg": "1",
2307 "UMask": "0x12",
2308 "Unit": "iMC"
2309 },
2310 {
2311 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
2312 "Counter": "0,1,2,3",
2313 "EventCode": "0xBC",
2314 "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
2315 "PerPkg": "1",
2316 "UMask": "0x13",
2317 "Unit": "iMC"
2318 },
2319 {
2320 "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
2321 "Counter": "0,1,2,3",
2322 "EventCode": "0xBC",
2323 "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
2324 "PerPkg": "1",
2325 "UMask": "0x14",
2326 "Unit": "iMC"
2327 },
2328 {
2329 "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
2330 "Counter": "0,1,2,3",
2331 "EventCode": "0xBD",
2332 "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
2333 "PerPkg": "1",
2334 "UMask": "0x1",
2335 "Unit": "iMC"
2336 },
2337 {
2338 "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
2339 "Counter": "0,1,2,3",
2340 "EventCode": "0xBD",
2341 "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
2342 "PerPkg": "1",
2343 "UMask": "0x2",
2344 "Unit": "iMC"
2345 },
2346 {
2347 "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
2348 "Counter": "0,1,2,3",
2349 "EventCode": "0xBD",
2350 "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
2351 "PerPkg": "1",
2352 "UMask": "0x4",
2353 "Unit": "iMC"
2354 },
2355 {
2356 "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
2357 "Counter": "0,1,2,3",
2358 "EventCode": "0xBD",
2359 "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
2360 "PerPkg": "1",
2361 "UMask": "0x8",
2362 "Unit": "iMC"
2363 },
2364 {
2365 "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
2366 "Counter": "0,1,2,3",
2367 "EventCode": "0xBD",
2368 "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
2369 "PerPkg": "1",
2370 "UMask": "0x10",
2371 "Unit": "iMC"
2372 },
2373 {
2374 "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
2375 "Counter": "0,1,2,3",
2376 "EventCode": "0xBD",
2377 "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
2378 "PerPkg": "1",
2379 "Unit": "iMC"
2380 },
2381 {
2382 "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
2383 "Counter": "0,1,2,3",
2384 "EventCode": "0xBD",
2385 "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
2386 "PerPkg": "1",
2387 "UMask": "0x3",
2388 "Unit": "iMC"
2389 },
2390 {
2391 "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
2392 "Counter": "0,1,2,3",
2393 "EventCode": "0xBD",
2394 "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
2395 "PerPkg": "1",
2396 "UMask": "0x5",
2397 "Unit": "iMC"
2398 },
2399 {
2400 "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
2401 "Counter": "0,1,2,3",
2402 "EventCode": "0xBD",
2403 "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
2404 "PerPkg": "1",
2405 "UMask": "0x6",
2406 "Unit": "iMC"
2407 },
2408 {
2409 "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
2410 "Counter": "0,1,2,3",
2411 "EventCode": "0xBD",
2412 "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
2413 "PerPkg": "1",
2414 "UMask": "0x7",
2415 "Unit": "iMC"
2416 },
2417 {
2418 "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
2419 "Counter": "0,1,2,3",
2420 "EventCode": "0xBD",
2421 "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
2422 "PerPkg": "1",
2423 "UMask": "0x9",
2424 "Unit": "iMC"
2425 },
2426 {
2427 "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
2428 "Counter": "0,1,2,3",
2429 "EventCode": "0xBD",
2430 "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
2431 "PerPkg": "1",
2432 "UMask": "0xA",
2433 "Unit": "iMC"
2434 },
2435 {
2436 "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
2437 "Counter": "0,1,2,3",
2438 "EventCode": "0xBD",
2439 "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
2440 "PerPkg": "1",
2441 "UMask": "0xB",
2442 "Unit": "iMC"
2443 },
2444 {
2445 "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
2446 "Counter": "0,1,2,3",
2447 "EventCode": "0xBD",
2448 "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
2449 "PerPkg": "1",
2450 "UMask": "0xC",
2451 "Unit": "iMC"
2452 },
2453 {
2454 "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
2455 "Counter": "0,1,2,3",
2456 "EventCode": "0xBD",
2457 "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
2458 "PerPkg": "1",
2459 "UMask": "0xD",
2460 "Unit": "iMC"
2461 },
2462 {
2463 "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
2464 "Counter": "0,1,2,3",
2465 "EventCode": "0xBD",
2466 "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
2467 "PerPkg": "1",
2468 "UMask": "0xE",
2469 "Unit": "iMC"
2470 },
2471 {
2472 "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
2473 "Counter": "0,1,2,3",
2474 "EventCode": "0xBD",
2475 "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
2476 "PerPkg": "1",
2477 "UMask": "0xF",
2478 "Unit": "iMC"
2479 },
2480 {
2481 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
2482 "Counter": "0,1,2,3",
2483 "EventCode": "0xBD",
2484 "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
2485 "PerPkg": "1",
2486 "UMask": "0x11",
2487 "Unit": "iMC"
2488 },
2489 {
2490 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
2491 "Counter": "0,1,2,3",
2492 "EventCode": "0xBD",
2493 "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
2494 "PerPkg": "1",
2495 "UMask": "0x12",
2496 "Unit": "iMC"
2497 },
2498 {
2499 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
2500 "Counter": "0,1,2,3",
2501 "EventCode": "0xBD",
2502 "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
2503 "PerPkg": "1",
2504 "UMask": "0x13",
2505 "Unit": "iMC"
2506 },
2507 {
2508 "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
2509 "Counter": "0,1,2,3",
2510 "EventCode": "0xBD",
2511 "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
2512 "PerPkg": "1",
2513 "UMask": "0x14",
2514 "Unit": "iMC"
2515 },
2516 {
2517 "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
2518 "Counter": "0,1,2,3",
2519 "EventCode": "0xBE",
2520 "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
2521 "PerPkg": "1",
2522 "UMask": "0x1",
2523 "Unit": "iMC"
2524 },
2525 {
2526 "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
2527 "Counter": "0,1,2,3",
2528 "EventCode": "0xBE",
2529 "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
2530 "PerPkg": "1",
2531 "UMask": "0x2",
2532 "Unit": "iMC"
2533 },
2534 {
2535 "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
2536 "Counter": "0,1,2,3",
2537 "EventCode": "0xBE",
2538 "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
2539 "PerPkg": "1",
2540 "UMask": "0x4",
2541 "Unit": "iMC"
2542 },
2543 {
2544 "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
2545 "Counter": "0,1,2,3",
2546 "EventCode": "0xBE",
2547 "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
2548 "PerPkg": "1",
2549 "UMask": "0x8",
2550 "Unit": "iMC"
2551 },
2552 {
2553 "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
2554 "Counter": "0,1,2,3",
2555 "EventCode": "0xBE",
2556 "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
2557 "PerPkg": "1",
2558 "UMask": "0x10",
2559 "Unit": "iMC"
2560 },
2561 {
2562 "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
2563 "Counter": "0,1,2,3",
2564 "EventCode": "0xBE",
2565 "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
2566 "PerPkg": "1",
2567 "Unit": "iMC"
2568 },
2569 {
2570 "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
2571 "Counter": "0,1,2,3",
2572 "EventCode": "0xBE",
2573 "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
2574 "PerPkg": "1",
2575 "UMask": "0x3",
2576 "Unit": "iMC"
2577 },
2578 {
2579 "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
2580 "Counter": "0,1,2,3",
2581 "EventCode": "0xBE",
2582 "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
2583 "PerPkg": "1",
2584 "UMask": "0x5",
2585 "Unit": "iMC"
2586 },
2587 {
2588 "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
2589 "Counter": "0,1,2,3",
2590 "EventCode": "0xBE",
2591 "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
2592 "PerPkg": "1",
2593 "UMask": "0x6",
2594 "Unit": "iMC"
2595 },
2596 {
2597 "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
2598 "Counter": "0,1,2,3",
2599 "EventCode": "0xBE",
2600 "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
2601 "PerPkg": "1",
2602 "UMask": "0x7",
2603 "Unit": "iMC"
2604 },
2605 {
2606 "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
2607 "Counter": "0,1,2,3",
2608 "EventCode": "0xBE",
2609 "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
2610 "PerPkg": "1",
2611 "UMask": "0x9",
2612 "Unit": "iMC"
2613 },
2614 {
2615 "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
2616 "Counter": "0,1,2,3",
2617 "EventCode": "0xBE",
2618 "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
2619 "PerPkg": "1",
2620 "UMask": "0xA",
2621 "Unit": "iMC"
2622 },
2623 {
2624 "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
2625 "Counter": "0,1,2,3",
2626 "EventCode": "0xBE",
2627 "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
2628 "PerPkg": "1",
2629 "UMask": "0xB",
2630 "Unit": "iMC"
2631 },
2632 {
2633 "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
2634 "Counter": "0,1,2,3",
2635 "EventCode": "0xBE",
2636 "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
2637 "PerPkg": "1",
2638 "UMask": "0xC",
2639 "Unit": "iMC"
2640 },
2641 {
2642 "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
2643 "Counter": "0,1,2,3",
2644 "EventCode": "0xBE",
2645 "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
2646 "PerPkg": "1",
2647 "UMask": "0xD",
2648 "Unit": "iMC"
2649 },
2650 {
2651 "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
2652 "Counter": "0,1,2,3",
2653 "EventCode": "0xBE",
2654 "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
2655 "PerPkg": "1",
2656 "UMask": "0xE",
2657 "Unit": "iMC"
2658 },
2659 {
2660 "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
2661 "Counter": "0,1,2,3",
2662 "EventCode": "0xBE",
2663 "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
2664 "PerPkg": "1",
2665 "UMask": "0xF",
2666 "Unit": "iMC"
2667 },
2668 {
2669 "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
2670 "Counter": "0,1,2,3",
2671 "EventCode": "0xBE",
2672 "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
2673 "PerPkg": "1",
2674 "UMask": "0x11",
2675 "Unit": "iMC"
2676 },
2677 {
2678 "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
2679 "Counter": "0,1,2,3",
2680 "EventCode": "0xBE",
2681 "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
2682 "PerPkg": "1",
2683 "UMask": "0x12",
2684 "Unit": "iMC"
2685 },
2686 {
2687 "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
2688 "Counter": "0,1,2,3",
2689 "EventCode": "0xBE",
2690 "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
2691 "PerPkg": "1",
2692 "UMask": "0x13",
2693 "Unit": "iMC"
2694 },
2695 {
2696 "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
2697 "Counter": "0,1,2,3",
2698 "EventCode": "0xBE",
2699 "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
2700 "PerPkg": "1",
2701 "UMask": "0x14",
2702 "Unit": "iMC"
2703 },
2704 {
2705 "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
2706 "Counter": "0,1,2,3",
2707 "EventCode": "0xBF",
2708 "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
2709 "PerPkg": "1",
2710 "UMask": "0x1",
2711 "Unit": "iMC"
2712 },
2713 {
2714 "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
2715 "Counter": "0,1,2,3",
2716 "EventCode": "0xBF",
2717 "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
2718 "PerPkg": "1",
2719 "UMask": "0x2",
2720 "Unit": "iMC"
2721 },
2722 {
2723 "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
2724 "Counter": "0,1,2,3",
2725 "EventCode": "0xBF",
2726 "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
2727 "PerPkg": "1",
2728 "UMask": "0x4",
2729 "Unit": "iMC"
2730 },
2731 {
2732 "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
2733 "Counter": "0,1,2,3",
2734 "EventCode": "0xBF",
2735 "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
2736 "PerPkg": "1",
2737 "UMask": "0x8",
2738 "Unit": "iMC"
2739 },
2740 {
2741 "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
2742 "Counter": "0,1,2,3",
2743 "EventCode": "0xBF",
2744 "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
2745 "PerPkg": "1",
2746 "UMask": "0x10",
2747 "Unit": "iMC"
2748 },
2749 {
2750 "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
2751 "Counter": "0,1,2,3",
2752 "EventCode": "0xBF",
2753 "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
2754 "PerPkg": "1",
2755 "Unit": "iMC"
2756 },
2757 {
2758 "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
2759 "Counter": "0,1,2,3",
2760 "EventCode": "0xBF",
2761 "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
2762 "PerPkg": "1",
2763 "UMask": "0x3",
2764 "Unit": "iMC"
2765 },
2766 {
2767 "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
2768 "Counter": "0,1,2,3",
2769 "EventCode": "0xBF",
2770 "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
2771 "PerPkg": "1",
2772 "UMask": "0x5",
2773 "Unit": "iMC"
2774 },
2775 {
2776 "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
2777 "Counter": "0,1,2,3",
2778 "EventCode": "0xBF",
2779 "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
2780 "PerPkg": "1",
2781 "UMask": "0x6",
2782 "Unit": "iMC"
2783 },
2784 {
2785 "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
2786 "Counter": "0,1,2,3",
2787 "EventCode": "0xBF",
2788 "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
2789 "PerPkg": "1",
2790 "UMask": "0x7",
2791 "Unit": "iMC"
2792 },
2793 {
2794 "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
2795 "Counter": "0,1,2,3",
2796 "EventCode": "0xBF",
2797 "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
2798 "PerPkg": "1",
2799 "UMask": "0x9",
2800 "Unit": "iMC"
2801 },
2802 {
2803 "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
2804 "Counter": "0,1,2,3",
2805 "EventCode": "0xBF",
2806 "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
2807 "PerPkg": "1",
2808 "UMask": "0xA",
2809 "Unit": "iMC"
2810 },
2811 {
2812 "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
2813 "Counter": "0,1,2,3",
2814 "EventCode": "0xBF",
2815 "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
2816 "PerPkg": "1",
2817 "UMask": "0xB",
2818 "Unit": "iMC"
2819 },
2820 {
2821 "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
2822 "Counter": "0,1,2,3",
2823 "EventCode": "0xBF",
2824 "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
2825 "PerPkg": "1",
2826 "UMask": "0xC",
2827 "Unit": "iMC"
2828 },
2829 {
2830 "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
2831 "Counter": "0,1,2,3",
2832 "EventCode": "0xBF",
2833 "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
2834 "PerPkg": "1",
2835 "UMask": "0xD",
2836 "Unit": "iMC"
2837 },
2838 {
2839 "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
2840 "Counter": "0,1,2,3",
2841 "EventCode": "0xBF",
2842 "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
2843 "PerPkg": "1",
2844 "UMask": "0xE",
2845 "Unit": "iMC"
2846 },
2847 {
2848 "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
2849 "Counter": "0,1,2,3",
2850 "EventCode": "0xBF",
2851 "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
2852 "PerPkg": "1",
2853 "UMask": "0xF",
2854 "Unit": "iMC"
2855 },
2856 {
2857 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
2858 "Counter": "0,1,2,3",
2859 "EventCode": "0xBF",
2860 "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
2861 "PerPkg": "1",
2862 "UMask": "0x11",
2863 "Unit": "iMC"
2864 },
2865 {
2866 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
2867 "Counter": "0,1,2,3",
2868 "EventCode": "0xBF",
2869 "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
2870 "PerPkg": "1",
2871 "UMask": "0x12",
2872 "Unit": "iMC"
2873 },
2874 {
2875 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
2876 "Counter": "0,1,2,3",
2877 "EventCode": "0xBF",
2878 "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
2879 "PerPkg": "1",
2880 "UMask": "0x13",
2881 "Unit": "iMC"
2882 },
2883 {
2884 "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
2885 "Counter": "0,1,2,3",
2886 "EventCode": "0xBF",
2887 "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
2888 "PerPkg": "1",
2889 "UMask": "0x14",
2890 "Unit": "iMC"
2891 },
2892 {
2893 "BriefDescription": "DRAM Clockticks",
2894 "Counter": "0,1,2,3",
2895 "EventName": "UNC_M_DCLOCKTICKS",
2896 "PerPkg": "1",
2897 "Unit": "iMC"
2898 }
2899 ]
