0001 [
0002 {
0003 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x08",
0007 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
0008 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
0009 "SampleAfterValue": "100003",
0010 "UMask": "0x1"
0011 },
0012 {
0013 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "EventCode": "0x08",
0017 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
0018 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
0019 "SampleAfterValue": "100003",
0020 "UMask": "0x80"
0021 },
0022 {
0023 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
0024 "Counter": "0,1,2,3",
0025 "CounterHTOff": "0,1,2,3,4,5,6,7",
0026 "EventCode": "0x08",
0027 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
0028 "PublicDescription": "Number of cache load STLB hits. No page walk.",
0029 "SampleAfterValue": "2000003",
0030 "UMask": "0x60"
0031 },
0032 {
0033 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
0034 "Counter": "0,1,2,3",
0035 "CounterHTOff": "0,1,2,3,4,5,6,7",
0036 "EventCode": "0x08",
0037 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
0038 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
0039 "SampleAfterValue": "2000003",
0040 "UMask": "0x40"
0041 },
0042 {
0043 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
0044 "Counter": "0,1,2,3",
0045 "CounterHTOff": "0,1,2,3,4,5,6,7",
0046 "EventCode": "0x08",
0047 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
0048 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
0049 "SampleAfterValue": "2000003",
0050 "UMask": "0x20"
0051 },
0052 {
0053 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
0054 "Counter": "0,1,2,3",
0055 "CounterHTOff": "0,1,2,3,4,5,6,7",
0056 "EventCode": "0x08",
0057 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0058 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
0059 "SampleAfterValue": "100003",
0060 "UMask": "0xe"
0061 },
0062 {
0063 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
0064 "Counter": "0,1,2,3",
0065 "CounterHTOff": "0,1,2,3,4,5,6,7",
0066 "EventCode": "0x08",
0067 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
0068 "SampleAfterValue": "2000003",
0069 "UMask": "0x8"
0070 },
0071 {
0072 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
0073 "Counter": "0,1,2,3",
0074 "CounterHTOff": "0,1,2,3,4,5,6,7",
0075 "EventCode": "0x08",
0076 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
0077 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
0078 "SampleAfterValue": "2000003",
0079 "UMask": "0x4"
0080 },
0081 {
0082 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
0083 "Counter": "0,1,2,3",
0084 "CounterHTOff": "0,1,2,3,4,5,6,7",
0085 "EventCode": "0x08",
0086 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
0087 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
0088 "SampleAfterValue": "2000003",
0089 "UMask": "0x2"
0090 },
0091 {
0092 "BriefDescription": "Cycles when PMH is busy with page walks",
0093 "Counter": "0,1,2,3",
0094 "CounterHTOff": "0,1,2,3,4,5,6,7",
0095 "EventCode": "0x08",
0096 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
0097 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
0098 "SampleAfterValue": "2000003",
0099 "UMask": "0x10"
0100 },
0101 {
0102 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
0103 "Counter": "0,1,2,3",
0104 "CounterHTOff": "0,1,2,3,4,5,6,7",
0105 "EventCode": "0x49",
0106 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
0107 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
0108 "SampleAfterValue": "100003",
0109 "UMask": "0x1"
0110 },
0111 {
0112 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
0113 "Counter": "0,1,2,3",
0114 "CounterHTOff": "0,1,2,3,4,5,6,7",
0115 "EventCode": "0x49",
0116 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
0117 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
0118 "SampleAfterValue": "100003",
0119 "UMask": "0x80"
0120 },
0121 {
0122 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
0123 "Counter": "0,1,2,3",
0124 "CounterHTOff": "0,1,2,3,4,5,6,7",
0125 "EventCode": "0x49",
0126 "EventName": "DTLB_STORE_MISSES.STLB_HIT",
0127 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
0128 "SampleAfterValue": "100003",
0129 "UMask": "0x60"
0130 },
0131 {
0132 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
0133 "Counter": "0,1,2,3",
0134 "CounterHTOff": "0,1,2,3,4,5,6,7",
0135 "EventCode": "0x49",
0136 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
0137 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
0138 "SampleAfterValue": "100003",
0139 "UMask": "0x40"
0140 },
0141 {
0142 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
0143 "Counter": "0,1,2,3",
0144 "CounterHTOff": "0,1,2,3,4,5,6,7",
0145 "EventCode": "0x49",
0146 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
0147 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
0148 "SampleAfterValue": "100003",
0149 "UMask": "0x20"
0150 },
0151 {
0152 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
0153 "Counter": "0,1,2,3",
0154 "CounterHTOff": "0,1,2,3,4,5,6,7",
0155 "EventCode": "0x49",
0156 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
0157 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
0158 "SampleAfterValue": "100003",
0159 "UMask": "0xe"
0160 },
0161 {
0162 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
0163 "Counter": "0,1,2,3",
0164 "CounterHTOff": "0,1,2,3,4,5,6,7",
0165 "EventCode": "0x49",
0166 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
0167 "SampleAfterValue": "100003",
0168 "UMask": "0x8"
0169 },
0170 {
0171 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
0172 "Counter": "0,1,2,3",
0173 "CounterHTOff": "0,1,2,3,4,5,6,7",
0174 "EventCode": "0x49",
0175 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
0176 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
0177 "SampleAfterValue": "100003",
0178 "UMask": "0x4"
0179 },
0180 {
0181 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
0182 "Counter": "0,1,2,3",
0183 "CounterHTOff": "0,1,2,3,4,5,6,7",
0184 "EventCode": "0x49",
0185 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
0186 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
0187 "SampleAfterValue": "100003",
0188 "UMask": "0x2"
0189 },
0190 {
0191 "BriefDescription": "Cycles when PMH is busy with page walks",
0192 "Counter": "0,1,2,3",
0193 "CounterHTOff": "0,1,2,3,4,5,6,7",
0194 "EventCode": "0x49",
0195 "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
0196 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
0197 "SampleAfterValue": "100003",
0198 "UMask": "0x10"
0199 },
0200 {
0201 "BriefDescription": "Cycle count for an Extended Page table walk.",
0202 "Counter": "0,1,2,3",
0203 "CounterHTOff": "0,1,2,3,4,5,6,7",
0204 "EventCode": "0x4f",
0205 "EventName": "EPT.WALK_CYCLES",
0206 "SampleAfterValue": "2000003",
0207 "UMask": "0x10"
0208 },
0209 {
0210 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
0211 "Counter": "0,1,2,3",
0212 "CounterHTOff": "0,1,2,3,4,5,6,7",
0213 "EventCode": "0xae",
0214 "EventName": "ITLB.ITLB_FLUSH",
0215 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
0216 "SampleAfterValue": "100003",
0217 "UMask": "0x1"
0218 },
0219 {
0220 "BriefDescription": "Misses at all ITLB levels that cause page walks",
0221 "Counter": "0,1,2,3",
0222 "CounterHTOff": "0,1,2,3,4,5,6,7",
0223 "EventCode": "0x85",
0224 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
0225 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
0226 "SampleAfterValue": "100003",
0227 "UMask": "0x1"
0228 },
0229 {
0230 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
0231 "Counter": "0,1,2,3",
0232 "CounterHTOff": "0,1,2,3,4,5,6,7",
0233 "EventCode": "0x85",
0234 "EventName": "ITLB_MISSES.STLB_HIT",
0235 "PublicDescription": "ITLB misses that hit STLB. No page walk.",
0236 "SampleAfterValue": "100003",
0237 "UMask": "0x60"
0238 },
0239 {
0240 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
0241 "Counter": "0,1,2,3",
0242 "CounterHTOff": "0,1,2,3,4,5,6,7",
0243 "EventCode": "0x85",
0244 "EventName": "ITLB_MISSES.STLB_HIT_2M",
0245 "PublicDescription": "ITLB misses that hit STLB (2M).",
0246 "SampleAfterValue": "100003",
0247 "UMask": "0x40"
0248 },
0249 {
0250 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
0251 "Counter": "0,1,2,3",
0252 "CounterHTOff": "0,1,2,3,4,5,6,7",
0253 "EventCode": "0x85",
0254 "EventName": "ITLB_MISSES.STLB_HIT_4K",
0255 "PublicDescription": "ITLB misses that hit STLB (4K).",
0256 "SampleAfterValue": "100003",
0257 "UMask": "0x20"
0258 },
0259 {
0260 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
0261 "Counter": "0,1,2,3",
0262 "CounterHTOff": "0,1,2,3,4,5,6,7",
0263 "EventCode": "0x85",
0264 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0265 "PublicDescription": "Completed page walks in ITLB of any page size.",
0266 "SampleAfterValue": "100003",
0267 "UMask": "0xe"
0268 },
0269 {
0270 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
0271 "Counter": "0,1,2,3",
0272 "CounterHTOff": "0,1,2,3,4,5,6,7",
0273 "EventCode": "0x85",
0274 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
0275 "SampleAfterValue": "100003",
0276 "UMask": "0x8"
0277 },
0278 {
0279 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
0280 "Counter": "0,1,2,3",
0281 "CounterHTOff": "0,1,2,3,4,5,6,7",
0282 "EventCode": "0x85",
0283 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
0284 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
0285 "SampleAfterValue": "100003",
0286 "UMask": "0x4"
0287 },
0288 {
0289 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
0290 "Counter": "0,1,2,3",
0291 "CounterHTOff": "0,1,2,3,4,5,6,7",
0292 "EventCode": "0x85",
0293 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
0294 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
0295 "SampleAfterValue": "100003",
0296 "UMask": "0x2"
0297 },
0298 {
0299 "BriefDescription": "Cycles when PMH is busy with page walks",
0300 "Counter": "0,1,2,3",
0301 "CounterHTOff": "0,1,2,3,4,5,6,7",
0302 "EventCode": "0x85",
0303 "EventName": "ITLB_MISSES.WALK_DURATION",
0304 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
0305 "SampleAfterValue": "100003",
0306 "UMask": "0x10"
0307 },
0308 {
0309 "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
0310 "Counter": "0,1,2,3",
0311 "CounterHTOff": "0,1,2,3",
0312 "EventCode": "0xBC",
0313 "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
0314 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
0315 "SampleAfterValue": "2000003",
0316 "UMask": "0x11"
0317 },
0318 {
0319 "BriefDescription": "Number of DTLB page walker hits in the L2",
0320 "Counter": "0,1,2,3",
0321 "CounterHTOff": "0,1,2,3",
0322 "EventCode": "0xBC",
0323 "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
0324 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
0325 "SampleAfterValue": "2000003",
0326 "UMask": "0x12"
0327 },
0328 {
0329 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
0330 "Counter": "0,1,2,3",
0331 "CounterHTOff": "0,1,2,3",
0332 "Errata": "HSD25",
0333 "EventCode": "0xBC",
0334 "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
0335 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
0336 "SampleAfterValue": "2000003",
0337 "UMask": "0x14"
0338 },
0339 {
0340 "BriefDescription": "Number of DTLB page walker hits in Memory",
0341 "Counter": "0,1,2,3",
0342 "CounterHTOff": "0,1,2,3",
0343 "Errata": "HSD25",
0344 "EventCode": "0xBC",
0345 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
0346 "PublicDescription": "Number of DTLB page walker loads from memory.",
0347 "SampleAfterValue": "2000003",
0348 "UMask": "0x18"
0349 },
0350 {
0351 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
0352 "Counter": "0,1,2,3",
0353 "CounterHTOff": "0,1,2,3",
0354 "EventCode": "0xBC",
0355 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
0356 "SampleAfterValue": "2000003",
0357 "UMask": "0x41"
0358 },
0359 {
0360 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
0361 "Counter": "0,1,2,3",
0362 "CounterHTOff": "0,1,2,3",
0363 "EventCode": "0xBC",
0364 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
0365 "SampleAfterValue": "2000003",
0366 "UMask": "0x42"
0367 },
0368 {
0369 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
0370 "Counter": "0,1,2,3",
0371 "CounterHTOff": "0,1,2,3",
0372 "EventCode": "0xBC",
0373 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
0374 "SampleAfterValue": "2000003",
0375 "UMask": "0x44"
0376 },
0377 {
0378 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
0379 "Counter": "0,1,2,3",
0380 "CounterHTOff": "0,1,2,3",
0381 "EventCode": "0xBC",
0382 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
0383 "SampleAfterValue": "2000003",
0384 "UMask": "0x48"
0385 },
0386 {
0387 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
0388 "Counter": "0,1,2,3",
0389 "CounterHTOff": "0,1,2,3",
0390 "EventCode": "0xBC",
0391 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
0392 "SampleAfterValue": "2000003",
0393 "UMask": "0x81"
0394 },
0395 {
0396 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
0397 "Counter": "0,1,2,3",
0398 "CounterHTOff": "0,1,2,3",
0399 "EventCode": "0xBC",
0400 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
0401 "SampleAfterValue": "2000003",
0402 "UMask": "0x82"
0403 },
0404 {
0405 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
0406 "Counter": "0,1,2,3",
0407 "CounterHTOff": "0,1,2,3",
0408 "EventCode": "0xBC",
0409 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
0410 "SampleAfterValue": "2000003",
0411 "UMask": "0x84"
0412 },
0413 {
0414 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
0415 "Counter": "0,1,2,3",
0416 "CounterHTOff": "0,1,2,3",
0417 "EventCode": "0xBC",
0418 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
0419 "SampleAfterValue": "2000003",
0420 "UMask": "0x88"
0421 },
0422 {
0423 "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
0424 "Counter": "0,1,2,3",
0425 "CounterHTOff": "0,1,2,3",
0426 "EventCode": "0xBC",
0427 "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
0428 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
0429 "SampleAfterValue": "2000003",
0430 "UMask": "0x21"
0431 },
0432 {
0433 "BriefDescription": "Number of ITLB page walker hits in the L2",
0434 "Counter": "0,1,2,3",
0435 "CounterHTOff": "0,1,2,3",
0436 "EventCode": "0xBC",
0437 "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
0438 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
0439 "SampleAfterValue": "2000003",
0440 "UMask": "0x22"
0441 },
0442 {
0443 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
0444 "Counter": "0,1,2,3",
0445 "CounterHTOff": "0,1,2,3",
0446 "Errata": "HSD25",
0447 "EventCode": "0xBC",
0448 "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
0449 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
0450 "SampleAfterValue": "2000003",
0451 "UMask": "0x24"
0452 },
0453 {
0454 "BriefDescription": "Number of ITLB page walker hits in Memory",
0455 "Counter": "0,1,2,3",
0456 "CounterHTOff": "0,1,2,3",
0457 "Errata": "HSD25",
0458 "EventCode": "0xBC",
0459 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
0460 "PublicDescription": "Number of ITLB page walker loads from memory.",
0461 "SampleAfterValue": "2000003",
0462 "UMask": "0x28"
0463 },
0464 {
0465 "BriefDescription": "DTLB flush attempts of the thread-specific entries",
0466 "Counter": "0,1,2,3",
0467 "CounterHTOff": "0,1,2,3,4,5,6,7",
0468 "EventCode": "0xBD",
0469 "EventName": "TLB_FLUSH.DTLB_THREAD",
0470 "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
0471 "SampleAfterValue": "100003",
0472 "UMask": "0x1"
0473 },
0474 {
0475 "BriefDescription": "STLB flush attempts",
0476 "Counter": "0,1,2,3",
0477 "CounterHTOff": "0,1,2,3,4,5,6,7",
0478 "EventCode": "0xBD",
0479 "EventName": "TLB_FLUSH.STLB_ANY",
0480 "PublicDescription": "Count number of STLB flush attempts.",
0481 "SampleAfterValue": "100003",
0482 "UMask": "0x20"
0483 }
0484 ]
