0001 [
0002 {
0003 "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x5C",
0007 "EventName": "CPL_CYCLES.RING0",
0008 "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
0009 "SampleAfterValue": "2000003",
0010 "UMask": "0x1"
0011 },
0012 {
0013 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "CounterMask": "1",
0017 "EdgeDetect": "1",
0018 "EventCode": "0x5C",
0019 "EventName": "CPL_CYCLES.RING0_TRANS",
0020 "SampleAfterValue": "100003",
0021 "UMask": "0x1"
0022 },
0023 {
0024 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
0025 "Counter": "0,1,2,3",
0026 "CounterHTOff": "0,1,2,3,4,5,6,7",
0027 "EventCode": "0x5C",
0028 "EventName": "CPL_CYCLES.RING123",
0029 "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x2"
0032 },
0033 {
0034 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
0035 "Counter": "0,1,2,3",
0036 "CounterHTOff": "0,1,2,3,4,5,6,7",
0037 "EventCode": "0x63",
0038 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
0039 "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
0040 "SampleAfterValue": "2000003",
0041 "UMask": "0x1"
0042 }
0043 ]
