0001 [
0002 {
0003 "BriefDescription": "L1D data line replacements",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x51",
0007 "EventName": "L1D.REPLACEMENT",
0008 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
0009 "SampleAfterValue": "2000003",
0010 "UMask": "0x1"
0011 },
0012 {
0013 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "CounterMask": "1",
0017 "EventCode": "0x48",
0018 "EventName": "L1D_PEND_MISS.FB_FULL",
0019 "SampleAfterValue": "2000003",
0020 "UMask": "0x2"
0021 },
0022 {
0023 "BriefDescription": "L1D miss oustandings duration in cycles",
0024 "Counter": "2",
0025 "CounterHTOff": "2",
0026 "EventCode": "0x48",
0027 "EventName": "L1D_PEND_MISS.PENDING",
0028 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
0029 "SampleAfterValue": "2000003",
0030 "UMask": "0x1"
0031 },
0032 {
0033 "BriefDescription": "Cycles with L1D load Misses outstanding.",
0034 "Counter": "2",
0035 "CounterHTOff": "2",
0036 "CounterMask": "1",
0037 "EventCode": "0x48",
0038 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
0039 "SampleAfterValue": "2000003",
0040 "UMask": "0x1"
0041 },
0042 {
0043 "AnyThread": "1",
0044 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
0045 "Counter": "2",
0046 "CounterHTOff": "2",
0047 "CounterMask": "1",
0048 "EventCode": "0x48",
0049 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
0050 "SampleAfterValue": "2000003",
0051 "UMask": "0x1"
0052 },
0053 {
0054 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
0055 "Counter": "0,1,2,3",
0056 "CounterHTOff": "0,1,2,3,4,5,6,7",
0057 "EventCode": "0x48",
0058 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
0059 "SampleAfterValue": "2000003",
0060 "UMask": "0x2"
0061 },
0062 {
0063 "BriefDescription": "Not rejected writebacks that hit L2 cache",
0064 "Counter": "0,1,2,3",
0065 "CounterHTOff": "0,1,2,3,4,5,6,7",
0066 "EventCode": "0x27",
0067 "EventName": "L2_DEMAND_RQSTS.WB_HIT",
0068 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
0069 "SampleAfterValue": "200003",
0070 "UMask": "0x50"
0071 },
0072 {
0073 "BriefDescription": "L2 cache lines filling L2",
0074 "Counter": "0,1,2,3",
0075 "CounterHTOff": "0,1,2,3,4,5,6,7",
0076 "EventCode": "0xF1",
0077 "EventName": "L2_LINES_IN.ALL",
0078 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
0079 "SampleAfterValue": "100003",
0080 "UMask": "0x7"
0081 },
0082 {
0083 "BriefDescription": "L2 cache lines in E state filling L2",
0084 "Counter": "0,1,2,3",
0085 "CounterHTOff": "0,1,2,3,4,5,6,7",
0086 "EventCode": "0xF1",
0087 "EventName": "L2_LINES_IN.E",
0088 "PublicDescription": "L2 cache lines in E state filling L2.",
0089 "SampleAfterValue": "100003",
0090 "UMask": "0x4"
0091 },
0092 {
0093 "BriefDescription": "L2 cache lines in I state filling L2",
0094 "Counter": "0,1,2,3",
0095 "CounterHTOff": "0,1,2,3,4,5,6,7",
0096 "EventCode": "0xF1",
0097 "EventName": "L2_LINES_IN.I",
0098 "PublicDescription": "L2 cache lines in I state filling L2.",
0099 "SampleAfterValue": "100003",
0100 "UMask": "0x1"
0101 },
0102 {
0103 "BriefDescription": "L2 cache lines in S state filling L2",
0104 "Counter": "0,1,2,3",
0105 "CounterHTOff": "0,1,2,3,4,5,6,7",
0106 "EventCode": "0xF1",
0107 "EventName": "L2_LINES_IN.S",
0108 "PublicDescription": "L2 cache lines in S state filling L2.",
0109 "SampleAfterValue": "100003",
0110 "UMask": "0x2"
0111 },
0112 {
0113 "BriefDescription": "Clean L2 cache lines evicted by demand",
0114 "Counter": "0,1,2,3",
0115 "CounterHTOff": "0,1,2,3,4,5,6,7",
0116 "EventCode": "0xF2",
0117 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
0118 "PublicDescription": "Clean L2 cache lines evicted by demand.",
0119 "SampleAfterValue": "100003",
0120 "UMask": "0x5"
0121 },
0122 {
0123 "BriefDescription": "Dirty L2 cache lines evicted by demand",
0124 "Counter": "0,1,2,3",
0125 "CounterHTOff": "0,1,2,3,4,5,6,7",
0126 "EventCode": "0xF2",
0127 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
0128 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
0129 "SampleAfterValue": "100003",
0130 "UMask": "0x6"
0131 },
0132 {
0133 "BriefDescription": "L2 code requests",
0134 "Counter": "0,1,2,3",
0135 "CounterHTOff": "0,1,2,3,4,5,6,7",
0136 "EventCode": "0x24",
0137 "EventName": "L2_RQSTS.ALL_CODE_RD",
0138 "PublicDescription": "Counts all L2 code requests.",
0139 "SampleAfterValue": "200003",
0140 "UMask": "0xe4"
0141 },
0142 {
0143 "BriefDescription": "Demand Data Read requests",
0144 "Counter": "0,1,2,3",
0145 "CounterHTOff": "0,1,2,3,4,5,6,7",
0146 "Errata": "HSD78, HSM80",
0147 "EventCode": "0x24",
0148 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
0149 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
0150 "SampleAfterValue": "200003",
0151 "UMask": "0xe1"
0152 },
0153 {
0154 "BriefDescription": "Demand requests that miss L2 cache",
0155 "Counter": "0,1,2,3",
0156 "CounterHTOff": "0,1,2,3,4,5,6,7",
0157 "Errata": "HSD78, HSM80",
0158 "EventCode": "0x24",
0159 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
0160 "PublicDescription": "Demand requests that miss L2 cache.",
0161 "SampleAfterValue": "200003",
0162 "UMask": "0x27"
0163 },
0164 {
0165 "BriefDescription": "Demand requests to L2 cache",
0166 "Counter": "0,1,2,3",
0167 "CounterHTOff": "0,1,2,3,4,5,6,7",
0168 "Errata": "HSD78, HSM80",
0169 "EventCode": "0x24",
0170 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
0171 "PublicDescription": "Demand requests to L2 cache.",
0172 "SampleAfterValue": "200003",
0173 "UMask": "0xe7"
0174 },
0175 {
0176 "BriefDescription": "Requests from L2 hardware prefetchers",
0177 "Counter": "0,1,2,3",
0178 "CounterHTOff": "0,1,2,3,4,5,6,7",
0179 "EventCode": "0x24",
0180 "EventName": "L2_RQSTS.ALL_PF",
0181 "PublicDescription": "Counts all L2 HW prefetcher requests.",
0182 "SampleAfterValue": "200003",
0183 "UMask": "0xf8"
0184 },
0185 {
0186 "BriefDescription": "RFO requests to L2 cache",
0187 "Counter": "0,1,2,3",
0188 "CounterHTOff": "0,1,2,3,4,5,6,7",
0189 "EventCode": "0x24",
0190 "EventName": "L2_RQSTS.ALL_RFO",
0191 "PublicDescription": "Counts all L2 store RFO requests.",
0192 "SampleAfterValue": "200003",
0193 "UMask": "0xe2"
0194 },
0195 {
0196 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
0197 "Counter": "0,1,2,3",
0198 "CounterHTOff": "0,1,2,3,4,5,6,7",
0199 "EventCode": "0x24",
0200 "EventName": "L2_RQSTS.CODE_RD_HIT",
0201 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
0202 "SampleAfterValue": "200003",
0203 "UMask": "0xc4"
0204 },
0205 {
0206 "BriefDescription": "L2 cache misses when fetching instructions",
0207 "Counter": "0,1,2,3",
0208 "CounterHTOff": "0,1,2,3,4,5,6,7",
0209 "EventCode": "0x24",
0210 "EventName": "L2_RQSTS.CODE_RD_MISS",
0211 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
0212 "SampleAfterValue": "200003",
0213 "UMask": "0x24"
0214 },
0215 {
0216 "BriefDescription": "Demand Data Read requests that hit L2 cache",
0217 "Counter": "0,1,2,3",
0218 "CounterHTOff": "0,1,2,3,4,5,6,7",
0219 "Errata": "HSD78, HSM80",
0220 "EventCode": "0x24",
0221 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
0222 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
0223 "SampleAfterValue": "200003",
0224 "UMask": "0xc1"
0225 },
0226 {
0227 "BriefDescription": "Demand Data Read miss L2, no rejects",
0228 "Counter": "0,1,2,3",
0229 "CounterHTOff": "0,1,2,3,4,5,6,7",
0230 "Errata": "HSD78, HSM80",
0231 "EventCode": "0x24",
0232 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
0233 "PublicDescription": "Demand data read requests that missed L2, no rejects.",
0234 "SampleAfterValue": "200003",
0235 "UMask": "0x21"
0236 },
0237 {
0238 "BriefDescription": "L2 prefetch requests that hit L2 cache",
0239 "Counter": "0,1,2,3",
0240 "CounterHTOff": "0,1,2,3,4,5,6,7",
0241 "EventCode": "0x24",
0242 "EventName": "L2_RQSTS.L2_PF_HIT",
0243 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
0244 "SampleAfterValue": "200003",
0245 "UMask": "0xd0"
0246 },
0247 {
0248 "BriefDescription": "L2 prefetch requests that miss L2 cache",
0249 "Counter": "0,1,2,3",
0250 "CounterHTOff": "0,1,2,3,4,5,6,7",
0251 "EventCode": "0x24",
0252 "EventName": "L2_RQSTS.L2_PF_MISS",
0253 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
0254 "SampleAfterValue": "200003",
0255 "UMask": "0x30"
0256 },
0257 {
0258 "BriefDescription": "All requests that miss L2 cache",
0259 "Counter": "0,1,2,3",
0260 "CounterHTOff": "0,1,2,3,4,5,6,7",
0261 "Errata": "HSD78, HSM80",
0262 "EventCode": "0x24",
0263 "EventName": "L2_RQSTS.MISS",
0264 "PublicDescription": "All requests that missed L2.",
0265 "SampleAfterValue": "200003",
0266 "UMask": "0x3f"
0267 },
0268 {
0269 "BriefDescription": "All L2 requests",
0270 "Counter": "0,1,2,3",
0271 "CounterHTOff": "0,1,2,3,4,5,6,7",
0272 "Errata": "HSD78, HSM80",
0273 "EventCode": "0x24",
0274 "EventName": "L2_RQSTS.REFERENCES",
0275 "PublicDescription": "All requests to L2 cache.",
0276 "SampleAfterValue": "200003",
0277 "UMask": "0xff"
0278 },
0279 {
0280 "BriefDescription": "RFO requests that hit L2 cache",
0281 "Counter": "0,1,2,3",
0282 "CounterHTOff": "0,1,2,3,4,5,6,7",
0283 "EventCode": "0x24",
0284 "EventName": "L2_RQSTS.RFO_HIT",
0285 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
0286 "SampleAfterValue": "200003",
0287 "UMask": "0xc2"
0288 },
0289 {
0290 "BriefDescription": "RFO requests that miss L2 cache",
0291 "Counter": "0,1,2,3",
0292 "CounterHTOff": "0,1,2,3,4,5,6,7",
0293 "EventCode": "0x24",
0294 "EventName": "L2_RQSTS.RFO_MISS",
0295 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
0296 "SampleAfterValue": "200003",
0297 "UMask": "0x22"
0298 },
0299 {
0300 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
0301 "Counter": "0,1,2,3",
0302 "CounterHTOff": "0,1,2,3,4,5,6,7",
0303 "EventCode": "0xf0",
0304 "EventName": "L2_TRANS.ALL_PF",
0305 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
0306 "SampleAfterValue": "200003",
0307 "UMask": "0x8"
0308 },
0309 {
0310 "BriefDescription": "Transactions accessing L2 pipe",
0311 "Counter": "0,1,2,3",
0312 "CounterHTOff": "0,1,2,3,4,5,6,7",
0313 "EventCode": "0xf0",
0314 "EventName": "L2_TRANS.ALL_REQUESTS",
0315 "PublicDescription": "Transactions accessing L2 pipe.",
0316 "SampleAfterValue": "200003",
0317 "UMask": "0x80"
0318 },
0319 {
0320 "BriefDescription": "L2 cache accesses when fetching instructions",
0321 "Counter": "0,1,2,3",
0322 "CounterHTOff": "0,1,2,3,4,5,6,7",
0323 "EventCode": "0xf0",
0324 "EventName": "L2_TRANS.CODE_RD",
0325 "PublicDescription": "L2 cache accesses when fetching instructions.",
0326 "SampleAfterValue": "200003",
0327 "UMask": "0x4"
0328 },
0329 {
0330 "BriefDescription": "Demand Data Read requests that access L2 cache",
0331 "Counter": "0,1,2,3",
0332 "CounterHTOff": "0,1,2,3,4,5,6,7",
0333 "EventCode": "0xf0",
0334 "EventName": "L2_TRANS.DEMAND_DATA_RD",
0335 "PublicDescription": "Demand data read requests that access L2 cache.",
0336 "SampleAfterValue": "200003",
0337 "UMask": "0x1"
0338 },
0339 {
0340 "BriefDescription": "L1D writebacks that access L2 cache",
0341 "Counter": "0,1,2,3",
0342 "CounterHTOff": "0,1,2,3,4,5,6,7",
0343 "EventCode": "0xf0",
0344 "EventName": "L2_TRANS.L1D_WB",
0345 "PublicDescription": "L1D writebacks that access L2 cache.",
0346 "SampleAfterValue": "200003",
0347 "UMask": "0x10"
0348 },
0349 {
0350 "BriefDescription": "L2 fill requests that access L2 cache",
0351 "Counter": "0,1,2,3",
0352 "CounterHTOff": "0,1,2,3,4,5,6,7",
0353 "EventCode": "0xf0",
0354 "EventName": "L2_TRANS.L2_FILL",
0355 "PublicDescription": "L2 fill requests that access L2 cache.",
0356 "SampleAfterValue": "200003",
0357 "UMask": "0x20"
0358 },
0359 {
0360 "BriefDescription": "L2 writebacks that access L2 cache",
0361 "Counter": "0,1,2,3",
0362 "CounterHTOff": "0,1,2,3,4,5,6,7",
0363 "EventCode": "0xf0",
0364 "EventName": "L2_TRANS.L2_WB",
0365 "PublicDescription": "L2 writebacks that access L2 cache.",
0366 "SampleAfterValue": "200003",
0367 "UMask": "0x40"
0368 },
0369 {
0370 "BriefDescription": "RFO requests that access L2 cache",
0371 "Counter": "0,1,2,3",
0372 "CounterHTOff": "0,1,2,3,4,5,6,7",
0373 "EventCode": "0xf0",
0374 "EventName": "L2_TRANS.RFO",
0375 "PublicDescription": "RFO requests that access L2 cache.",
0376 "SampleAfterValue": "200003",
0377 "UMask": "0x2"
0378 },
0379 {
0380 "BriefDescription": "Cycles when L1D is locked",
0381 "Counter": "0,1,2,3",
0382 "CounterHTOff": "0,1,2,3,4,5,6,7",
0383 "EventCode": "0x63",
0384 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
0385 "PublicDescription": "Cycles in which the L1D is locked.",
0386 "SampleAfterValue": "2000003",
0387 "UMask": "0x2"
0388 },
0389 {
0390 "BriefDescription": "Core-originated cacheable demand requests missed L3",
0391 "Counter": "0,1,2,3",
0392 "CounterHTOff": "0,1,2,3,4,5,6,7",
0393 "EventCode": "0x2E",
0394 "EventName": "LONGEST_LAT_CACHE.MISS",
0395 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
0396 "SampleAfterValue": "100003",
0397 "UMask": "0x41"
0398 },
0399 {
0400 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
0401 "Counter": "0,1,2,3",
0402 "CounterHTOff": "0,1,2,3,4,5,6,7",
0403 "EventCode": "0x2E",
0404 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0405 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
0406 "SampleAfterValue": "100003",
0407 "UMask": "0x4f"
0408 },
0409 {
0410 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
0411 "Counter": "0,1,2,3",
0412 "CounterHTOff": "0,1,2,3",
0413 "Data_LA": "1",
0414 "Errata": "HSD29, HSD25, HSM26, HSM30",
0415 "EventCode": "0xD2",
0416 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
0417 "PEBS": "1",
0418 "SampleAfterValue": "20011",
0419 "UMask": "0x2"
0420 },
0421 {
0422 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
0423 "Counter": "0,1,2,3",
0424 "CounterHTOff": "0,1,2,3",
0425 "Data_LA": "1",
0426 "Errata": "HSD29, HSD25, HSM26, HSM30",
0427 "EventCode": "0xD2",
0428 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
0429 "PEBS": "1",
0430 "SampleAfterValue": "20011",
0431 "UMask": "0x4"
0432 },
0433 {
0434 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
0435 "Counter": "0,1,2,3",
0436 "CounterHTOff": "0,1,2,3",
0437 "Data_LA": "1",
0438 "Errata": "HSD29, HSD25, HSM26, HSM30",
0439 "EventCode": "0xD2",
0440 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
0441 "PEBS": "1",
0442 "SampleAfterValue": "20011",
0443 "UMask": "0x1"
0444 },
0445 {
0446 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
0447 "Counter": "0,1,2,3",
0448 "CounterHTOff": "0,1,2,3",
0449 "Data_LA": "1",
0450 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
0451 "EventCode": "0xD2",
0452 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
0453 "PEBS": "1",
0454 "SampleAfterValue": "100003",
0455 "UMask": "0x8"
0456 },
0457 {
0458 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
0459 "Counter": "0,1,2,3",
0460 "CounterHTOff": "0,1,2,3",
0461 "Data_LA": "1",
0462 "Errata": "HSD74, HSD29, HSD25, HSM30",
0463 "EventCode": "0xD3",
0464 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
0465 "PEBS": "1",
0466 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
0467 "SampleAfterValue": "100003",
0468 "UMask": "0x1"
0469 },
0470 {
0471 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
0472 "Counter": "0,1,2,3",
0473 "CounterHTOff": "0,1,2,3",
0474 "Data_LA": "1",
0475 "Errata": "HSM30",
0476 "EventCode": "0xD1",
0477 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
0478 "PEBS": "1",
0479 "SampleAfterValue": "100003",
0480 "UMask": "0x40"
0481 },
0482 {
0483 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
0484 "Counter": "0,1,2,3",
0485 "CounterHTOff": "0,1,2,3",
0486 "Data_LA": "1",
0487 "Errata": "HSD29, HSM30",
0488 "EventCode": "0xD1",
0489 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
0490 "PEBS": "1",
0491 "SampleAfterValue": "2000003",
0492 "UMask": "0x1"
0493 },
0494 {
0495 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
0496 "Counter": "0,1,2,3",
0497 "CounterHTOff": "0,1,2,3",
0498 "Data_LA": "1",
0499 "Errata": "HSM30",
0500 "EventCode": "0xD1",
0501 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
0502 "PEBS": "1",
0503 "PublicDescription": "Retired load uops missed L1 cache as data sources.",
0504 "SampleAfterValue": "100003",
0505 "UMask": "0x8"
0506 },
0507 {
0508 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
0509 "Counter": "0,1,2,3",
0510 "CounterHTOff": "0,1,2,3",
0511 "Data_LA": "1",
0512 "Errata": "HSD76, HSD29, HSM30",
0513 "EventCode": "0xD1",
0514 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
0515 "PEBS": "1",
0516 "SampleAfterValue": "100003",
0517 "UMask": "0x2"
0518 },
0519 {
0520 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
0521 "Counter": "0,1,2,3",
0522 "CounterHTOff": "0,1,2,3",
0523 "Data_LA": "1",
0524 "Errata": "HSD29, HSM30",
0525 "EventCode": "0xD1",
0526 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
0527 "PEBS": "1",
0528 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
0529 "SampleAfterValue": "50021",
0530 "UMask": "0x10"
0531 },
0532 {
0533 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
0534 "Counter": "0,1,2,3",
0535 "CounterHTOff": "0,1,2,3",
0536 "Data_LA": "1",
0537 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
0538 "EventCode": "0xD1",
0539 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
0540 "PEBS": "1",
0541 "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
0542 "SampleAfterValue": "50021",
0543 "UMask": "0x4"
0544 },
0545 {
0546 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
0547 "Counter": "0,1,2,3",
0548 "CounterHTOff": "0,1,2,3",
0549 "Data_LA": "1",
0550 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
0551 "EventCode": "0xD1",
0552 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
0553 "PEBS": "1",
0554 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
0555 "SampleAfterValue": "100003",
0556 "UMask": "0x20"
0557 },
0558 {
0559 "BriefDescription": "Retired load uops.",
0560 "Counter": "0,1,2,3",
0561 "CounterHTOff": "0,1,2,3",
0562 "Data_LA": "1",
0563 "Errata": "HSD29, HSM30",
0564 "EventCode": "0xD0",
0565 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
0566 "PEBS": "1",
0567 "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
0568 "SampleAfterValue": "2000003",
0569 "UMask": "0x81"
0570 },
0571 {
0572 "BriefDescription": "Retired store uops.",
0573 "Counter": "0,1,2,3",
0574 "CounterHTOff": "0,1,2,3",
0575 "Data_LA": "1",
0576 "Errata": "HSD29, HSM30",
0577 "EventCode": "0xD0",
0578 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
0579 "L1_Hit_Indication": "1",
0580 "PEBS": "1",
0581 "PublicDescription": "Counts all retired store uops.",
0582 "SampleAfterValue": "2000003",
0583 "UMask": "0x82"
0584 },
0585 {
0586 "BriefDescription": "Retired load uops with locked access.",
0587 "Counter": "0,1,2,3",
0588 "CounterHTOff": "0,1,2,3",
0589 "Data_LA": "1",
0590 "Errata": "HSD76, HSD29, HSM30",
0591 "EventCode": "0xD0",
0592 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
0593 "PEBS": "1",
0594 "SampleAfterValue": "100003",
0595 "UMask": "0x21"
0596 },
0597 {
0598 "BriefDescription": "Retired load uops that split across a cacheline boundary.",
0599 "Counter": "0,1,2,3",
0600 "CounterHTOff": "0,1,2,3",
0601 "Data_LA": "1",
0602 "Errata": "HSD29, HSM30",
0603 "EventCode": "0xD0",
0604 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
0605 "PEBS": "1",
0606 "SampleAfterValue": "100003",
0607 "UMask": "0x41"
0608 },
0609 {
0610 "BriefDescription": "Retired store uops that split across a cacheline boundary.",
0611 "Counter": "0,1,2,3",
0612 "CounterHTOff": "0,1,2,3",
0613 "Data_LA": "1",
0614 "Errata": "HSD29, HSM30",
0615 "EventCode": "0xD0",
0616 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
0617 "L1_Hit_Indication": "1",
0618 "PEBS": "1",
0619 "SampleAfterValue": "100003",
0620 "UMask": "0x42"
0621 },
0622 {
0623 "BriefDescription": "Retired load uops that miss the STLB.",
0624 "Counter": "0,1,2,3",
0625 "CounterHTOff": "0,1,2,3",
0626 "Data_LA": "1",
0627 "Errata": "HSD29, HSM30",
0628 "EventCode": "0xD0",
0629 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
0630 "PEBS": "1",
0631 "SampleAfterValue": "100003",
0632 "UMask": "0x11"
0633 },
0634 {
0635 "BriefDescription": "Retired store uops that miss the STLB.",
0636 "Counter": "0,1,2,3",
0637 "CounterHTOff": "0,1,2,3",
0638 "Data_LA": "1",
0639 "Errata": "HSD29, HSM30",
0640 "EventCode": "0xD0",
0641 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
0642 "L1_Hit_Indication": "1",
0643 "PEBS": "1",
0644 "SampleAfterValue": "100003",
0645 "UMask": "0x12"
0646 },
0647 {
0648 "BriefDescription": "Demand and prefetch data reads",
0649 "Counter": "0,1,2,3",
0650 "CounterHTOff": "0,1,2,3,4,5,6,7",
0651 "EventCode": "0xB0",
0652 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
0653 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
0654 "SampleAfterValue": "100003",
0655 "UMask": "0x8"
0656 },
0657 {
0658 "BriefDescription": "Cacheable and noncachaeble code read requests",
0659 "Counter": "0,1,2,3",
0660 "CounterHTOff": "0,1,2,3,4,5,6,7",
0661 "EventCode": "0xB0",
0662 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
0663 "PublicDescription": "Demand code read requests sent to uncore.",
0664 "SampleAfterValue": "100003",
0665 "UMask": "0x2"
0666 },
0667 {
0668 "BriefDescription": "Demand Data Read requests sent to uncore",
0669 "Counter": "0,1,2,3",
0670 "CounterHTOff": "0,1,2,3,4,5,6,7",
0671 "Errata": "HSD78, HSM80",
0672 "EventCode": "0xb0",
0673 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
0674 "PublicDescription": "Demand data read requests sent to uncore.",
0675 "SampleAfterValue": "100003",
0676 "UMask": "0x1"
0677 },
0678 {
0679 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
0680 "Counter": "0,1,2,3",
0681 "CounterHTOff": "0,1,2,3,4,5,6,7",
0682 "EventCode": "0xB0",
0683 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
0684 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
0685 "SampleAfterValue": "100003",
0686 "UMask": "0x4"
0687 },
0688 {
0689 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
0690 "Counter": "0,1,2,3",
0691 "CounterHTOff": "0,1,2,3,4,5,6,7",
0692 "EventCode": "0xb2",
0693 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
0694 "SampleAfterValue": "2000003",
0695 "UMask": "0x1"
0696 },
0697 {
0698 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
0699 "Counter": "0,1,2,3",
0700 "CounterHTOff": "0,1,2,3,4,5,6,7",
0701 "Errata": "HSD62, HSD61, HSM63",
0702 "EventCode": "0x60",
0703 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
0704 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0705 "SampleAfterValue": "2000003",
0706 "UMask": "0x8"
0707 },
0708 {
0709 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
0710 "Counter": "0,1,2,3",
0711 "CounterHTOff": "0,1,2,3,4,5,6,7",
0712 "CounterMask": "1",
0713 "Errata": "HSD62, HSD61, HSM63",
0714 "EventCode": "0x60",
0715 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
0716 "SampleAfterValue": "2000003",
0717 "UMask": "0x8"
0718 },
0719 {
0720 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
0721 "Counter": "0,1,2,3",
0722 "CounterHTOff": "0,1,2,3,4,5,6,7",
0723 "CounterMask": "1",
0724 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
0725 "EventCode": "0x60",
0726 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
0727 "SampleAfterValue": "2000003",
0728 "UMask": "0x1"
0729 },
0730 {
0731 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
0732 "Counter": "0,1,2,3",
0733 "CounterHTOff": "0,1,2,3,4,5,6,7",
0734 "CounterMask": "1",
0735 "Errata": "HSD62, HSD61, HSM63",
0736 "EventCode": "0x60",
0737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
0738 "SampleAfterValue": "2000003",
0739 "UMask": "0x4"
0740 },
0741 {
0742 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
0743 "Counter": "0,1,2,3",
0744 "CounterHTOff": "0,1,2,3,4,5,6,7",
0745 "Errata": "HSD62, HSD61, HSM63",
0746 "EventCode": "0x60",
0747 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
0748 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0749 "SampleAfterValue": "2000003",
0750 "UMask": "0x2"
0751 },
0752 {
0753 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
0754 "Counter": "0,1,2,3",
0755 "CounterHTOff": "0,1,2,3,4,5,6,7",
0756 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
0757 "EventCode": "0x60",
0758 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
0759 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0760 "SampleAfterValue": "2000003",
0761 "UMask": "0x1"
0762 },
0763 {
0764 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
0765 "Counter": "0,1,2,3",
0766 "CounterHTOff": "0,1,2,3,4,5,6,7",
0767 "CounterMask": "6",
0768 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
0769 "EventCode": "0x60",
0770 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
0771 "SampleAfterValue": "2000003",
0772 "UMask": "0x1"
0773 },
0774 {
0775 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
0776 "Counter": "0,1,2,3",
0777 "CounterHTOff": "0,1,2,3,4,5,6,7",
0778 "Errata": "HSD62, HSD61, HSM63",
0779 "EventCode": "0x60",
0780 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
0781 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
0782 "SampleAfterValue": "2000003",
0783 "UMask": "0x4"
0784 },
0785 {
0786 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
0787 "Counter": "0,1,2,3",
0788 "CounterHTOff": "0,1,2,3",
0789 "EventCode": "0xB7, 0xBB",
0790 "EventName": "OFFCORE_RESPONSE",
0791 "SampleAfterValue": "100003",
0792 "UMask": "0x1"
0793 },
0794 {
0795 "BriefDescription": "Counts all demand & prefetch code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0796 "Counter": "0,1,2,3",
0797 "CounterHTOff": "0,1,2,3",
0798 "EventCode": "0xB7, 0xBB",
0799 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0800 "MSRIndex": "0x1a6,0x1a7",
0801 "MSRValue": "0x4003C0244",
0802 "Offcore": "1",
0803 "SampleAfterValue": "100003",
0804 "UMask": "0x1"
0805 },
0806 {
0807 "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0808 "Counter": "0,1,2,3",
0809 "CounterHTOff": "0,1,2,3",
0810 "EventCode": "0xB7, 0xBB",
0811 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
0812 "MSRIndex": "0x1a6,0x1a7",
0813 "MSRValue": "0x10003C0091",
0814 "Offcore": "1",
0815 "SampleAfterValue": "100003",
0816 "UMask": "0x1"
0817 },
0818 {
0819 "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0820 "Counter": "0,1,2,3",
0821 "CounterHTOff": "0,1,2,3",
0822 "EventCode": "0xB7, 0xBB",
0823 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0824 "MSRIndex": "0x1a6,0x1a7",
0825 "MSRValue": "0x4003C0091",
0826 "Offcore": "1",
0827 "SampleAfterValue": "100003",
0828 "UMask": "0x1"
0829 },
0830 {
0831 "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0832 "Counter": "0,1,2,3",
0833 "CounterHTOff": "0,1,2,3",
0834 "EventCode": "0xB7, 0xBB",
0835 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
0836 "MSRIndex": "0x1a6,0x1a7",
0837 "MSRValue": "0x10003C07F7",
0838 "Offcore": "1",
0839 "SampleAfterValue": "100003",
0840 "UMask": "0x1"
0841 },
0842 {
0843 "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0844 "Counter": "0,1,2,3",
0845 "CounterHTOff": "0,1,2,3",
0846 "EventCode": "0xB7, 0xBB",
0847 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0848 "MSRIndex": "0x1a6,0x1a7",
0849 "MSRValue": "0x4003C07F7",
0850 "Offcore": "1",
0851 "SampleAfterValue": "100003",
0852 "UMask": "0x1"
0853 },
0854 {
0855 "BriefDescription": "Counts all requestshit in the L3",
0856 "Counter": "0,1,2,3",
0857 "CounterHTOff": "0,1,2,3",
0858 "EventCode": "0xB7, 0xBB",
0859 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
0860 "MSRIndex": "0x1a6,0x1a7",
0861 "MSRValue": "0x3F803C8FFF",
0862 "Offcore": "1",
0863 "SampleAfterValue": "100003",
0864 "UMask": "0x1"
0865 },
0866 {
0867 "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0868 "Counter": "0,1,2,3",
0869 "CounterHTOff": "0,1,2,3",
0870 "EventCode": "0xB7, 0xBB",
0871 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
0872 "MSRIndex": "0x1a6,0x1a7",
0873 "MSRValue": "0x10003C0122",
0874 "Offcore": "1",
0875 "SampleAfterValue": "100003",
0876 "UMask": "0x1"
0877 },
0878 {
0879 "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0880 "Counter": "0,1,2,3",
0881 "CounterHTOff": "0,1,2,3",
0882 "EventCode": "0xB7, 0xBB",
0883 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0884 "MSRIndex": "0x1a6,0x1a7",
0885 "MSRValue": "0x4003C0122",
0886 "Offcore": "1",
0887 "SampleAfterValue": "100003",
0888 "UMask": "0x1"
0889 },
0890 {
0891 "BriefDescription": "Counts all demand code readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0892 "Counter": "0,1,2,3",
0893 "CounterHTOff": "0,1,2,3",
0894 "EventCode": "0xB7, 0xBB",
0895 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
0896 "MSRIndex": "0x1a6,0x1a7",
0897 "MSRValue": "0x10003C0004",
0898 "Offcore": "1",
0899 "SampleAfterValue": "100003",
0900 "UMask": "0x1"
0901 },
0902 {
0903 "BriefDescription": "Counts all demand code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0904 "Counter": "0,1,2,3",
0905 "CounterHTOff": "0,1,2,3",
0906 "EventCode": "0xB7, 0xBB",
0907 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0908 "MSRIndex": "0x1a6,0x1a7",
0909 "MSRValue": "0x4003C0004",
0910 "Offcore": "1",
0911 "SampleAfterValue": "100003",
0912 "UMask": "0x1"
0913 },
0914 {
0915 "BriefDescription": "Counts demand data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0916 "Counter": "0,1,2,3",
0917 "CounterHTOff": "0,1,2,3",
0918 "EventCode": "0xB7, 0xBB",
0919 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
0920 "MSRIndex": "0x1a6,0x1a7",
0921 "MSRValue": "0x10003C0001",
0922 "Offcore": "1",
0923 "SampleAfterValue": "100003",
0924 "UMask": "0x1"
0925 },
0926 {
0927 "BriefDescription": "Counts demand data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0928 "Counter": "0,1,2,3",
0929 "CounterHTOff": "0,1,2,3",
0930 "EventCode": "0xB7, 0xBB",
0931 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0932 "MSRIndex": "0x1a6,0x1a7",
0933 "MSRValue": "0x4003C0001",
0934 "Offcore": "1",
0935 "SampleAfterValue": "100003",
0936 "UMask": "0x1"
0937 },
0938 {
0939 "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
0940 "Counter": "0,1,2,3",
0941 "CounterHTOff": "0,1,2,3",
0942 "EventCode": "0xB7, 0xBB",
0943 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
0944 "MSRIndex": "0x1a6,0x1a7",
0945 "MSRValue": "0x10003C0002",
0946 "Offcore": "1",
0947 "SampleAfterValue": "100003",
0948 "UMask": "0x1"
0949 },
0950 {
0951 "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
0952 "Counter": "0,1,2,3",
0953 "CounterHTOff": "0,1,2,3",
0954 "EventCode": "0xB7, 0xBB",
0955 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
0956 "MSRIndex": "0x1a6,0x1a7",
0957 "MSRValue": "0x4003C0002",
0958 "Offcore": "1",
0959 "SampleAfterValue": "100003",
0960 "UMask": "0x1"
0961 },
0962 {
0963 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readshit in the L3",
0964 "Counter": "0,1,2,3",
0965 "CounterHTOff": "0,1,2,3",
0966 "EventCode": "0xB7, 0xBB",
0967 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
0968 "MSRIndex": "0x1a6,0x1a7",
0969 "MSRValue": "0x3F803C0040",
0970 "Offcore": "1",
0971 "SampleAfterValue": "100003",
0972 "UMask": "0x1"
0973 },
0974 {
0975 "BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3",
0976 "Counter": "0,1,2,3",
0977 "CounterHTOff": "0,1,2,3",
0978 "EventCode": "0xB7, 0xBB",
0979 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
0980 "MSRIndex": "0x1a6,0x1a7",
0981 "MSRValue": "0x3F803C0010",
0982 "Offcore": "1",
0983 "SampleAfterValue": "100003",
0984 "UMask": "0x1"
0985 },
0986 {
0987 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3",
0988 "Counter": "0,1,2,3",
0989 "CounterHTOff": "0,1,2,3",
0990 "EventCode": "0xB7, 0xBB",
0991 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
0992 "MSRIndex": "0x1a6,0x1a7",
0993 "MSRValue": "0x3F803C0020",
0994 "Offcore": "1",
0995 "SampleAfterValue": "100003",
0996 "UMask": "0x1"
0997 },
0998 {
0999 "BriefDescription": "Counts prefetch (that bring data to LLC only) code readshit in the L3",
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3",
1002 "EventCode": "0xB7, 0xBB",
1003 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
1004 "MSRIndex": "0x1a6,0x1a7",
1005 "MSRValue": "0x3F803C0200",
1006 "Offcore": "1",
1007 "SampleAfterValue": "100003",
1008 "UMask": "0x1"
1009 },
1010 {
1011 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readshit in the L3",
1012 "Counter": "0,1,2,3",
1013 "CounterHTOff": "0,1,2,3",
1014 "EventCode": "0xB7, 0xBB",
1015 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
1016 "MSRIndex": "0x1a6,0x1a7",
1017 "MSRValue": "0x3F803C0080",
1018 "Offcore": "1",
1019 "SampleAfterValue": "100003",
1020 "UMask": "0x1"
1021 },
1022 {
1023 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOshit in the L3",
1024 "Counter": "0,1,2,3",
1025 "CounterHTOff": "0,1,2,3",
1026 "EventCode": "0xB7, 0xBB",
1027 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
1028 "MSRIndex": "0x1a6,0x1a7",
1029 "MSRValue": "0x3F803C0100",
1030 "Offcore": "1",
1031 "SampleAfterValue": "100003",
1032 "UMask": "0x1"
1033 },
1034 {
1035 "BriefDescription": "Split locks in SQ",
1036 "Counter": "0,1,2,3",
1037 "CounterHTOff": "0,1,2,3,4,5,6,7",
1038 "EventCode": "0xf4",
1039 "EventName": "SQ_MISC.SPLIT_LOCK",
1040 "SampleAfterValue": "100003",
1041 "UMask": "0x10"
1042 }
1043 ]
