0001 [
0002 {
0003 "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3",
0006 "EventCode": "0xc3",
0007 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0008 "PDIR_COUNTER": "NA",
0009 "PEBScounters": "0,1,2,3",
0010 "SampleAfterValue": "20003",
0011 "UMask": "0x2"
0012 },
0013 {
0014 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
0015 "CollectPEBSRecord": "2",
0016 "Counter": "0,1,2,3",
0017 "EventCode": "0x13",
0018 "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
0019 "PEBS": "1",
0020 "PEBScounters": "0,1,2,3",
0021 "SampleAfterValue": "200003",
0022 "UMask": "0x2"
0023 },
0024 {
0025 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
0026 "CollectPEBSRecord": "2",
0027 "Counter": "0,1,2,3",
0028 "EventCode": "0x13",
0029 "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
0030 "PEBS": "1",
0031 "PEBScounters": "0,1,2,3",
0032 "SampleAfterValue": "200003",
0033 "UMask": "0x4"
0034 },
0035 {
0036 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
0037 "Counter": "0,1,2,3",
0038 "EventCode": "0XB7",
0039 "EventName": "OCR.ALL_CODE_RD.L3_MISS",
0040 "MSRIndex": "0x1a6,0x1a7",
0041 "MSRValue": "0x2184000044",
0042 "Offcore": "1",
0043 "SampleAfterValue": "100003",
0044 "UMask": "0x1"
0045 },
0046 {
0047 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
0048 "Counter": "0,1,2,3",
0049 "EventCode": "0XB7",
0050 "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
0051 "MSRIndex": "0x1a6,0x1a7",
0052 "MSRValue": "0x2184000044",
0053 "Offcore": "1",
0054 "SampleAfterValue": "100003",
0055 "UMask": "0x1"
0056 },
0057 {
0058 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
0059 "Counter": "0,1,2,3",
0060 "EventCode": "0XB7",
0061 "EventName": "OCR.COREWB_M.L3_MISS",
0062 "MSRIndex": "0x1a6,0x1a7",
0063 "MSRValue": "0x3002184000000",
0064 "Offcore": "1",
0065 "SampleAfterValue": "100003",
0066 "UMask": "0x1"
0067 },
0068 {
0069 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
0070 "Counter": "0,1,2,3",
0071 "EventCode": "0XB7",
0072 "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
0073 "MSRIndex": "0x1a6,0x1a7",
0074 "MSRValue": "0x3002184000000",
0075 "Offcore": "1",
0076 "SampleAfterValue": "100003",
0077 "UMask": "0x1"
0078 },
0079 {
0080 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
0081 "Counter": "0,1,2,3",
0082 "EventCode": "0XB7",
0083 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
0084 "MSRIndex": "0x1a6,0x1a7",
0085 "MSRValue": "0x2184000004",
0086 "Offcore": "1",
0087 "SampleAfterValue": "100003",
0088 "UMask": "0x1"
0089 },
0090 {
0091 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
0092 "Counter": "0,1,2,3",
0093 "EventCode": "0XB7",
0094 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
0095 "MSRIndex": "0x1a6,0x1a7",
0096 "MSRValue": "0x2184000004",
0097 "Offcore": "1",
0098 "SampleAfterValue": "100003",
0099 "UMask": "0x1"
0100 },
0101 {
0102 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
0103 "Counter": "0,1,2,3",
0104 "EventCode": "0XB7",
0105 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
0106 "MSRIndex": "0x1a6,0x1a7",
0107 "MSRValue": "0x2184000001",
0108 "Offcore": "1",
0109 "SampleAfterValue": "100003",
0110 "UMask": "0x1"
0111 },
0112 {
0113 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
0114 "Counter": "0,1,2,3",
0115 "EventCode": "0XB7",
0116 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
0117 "MSRIndex": "0x1a6,0x1a7",
0118 "MSRValue": "0x2184000001",
0119 "Offcore": "1",
0120 "SampleAfterValue": "100003",
0121 "UMask": "0x1"
0122 },
0123 {
0124 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
0125 "Counter": "0,1,2,3",
0126 "EventCode": "0XB7",
0127 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
0128 "MSRIndex": "0x1a6,0x1a7",
0129 "MSRValue": "0x2184000001",
0130 "Offcore": "1",
0131 "SampleAfterValue": "100003",
0132 "UMask": "0x1"
0133 },
0134 {
0135 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
0136 "Counter": "0,1,2,3",
0137 "EventCode": "0XB7",
0138 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
0139 "MSRIndex": "0x1a6,0x1a7",
0140 "MSRValue": "0x2184000001",
0141 "Offcore": "1",
0142 "SampleAfterValue": "100003",
0143 "UMask": "0x1"
0144 },
0145 {
0146 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
0147 "Counter": "0,1,2,3",
0148 "EventCode": "0XB7",
0149 "EventName": "OCR.DEMAND_RFO.L3_MISS",
0150 "MSRIndex": "0x1a6,0x1a7",
0151 "MSRValue": "0x2184000002",
0152 "Offcore": "1",
0153 "SampleAfterValue": "100003",
0154 "UMask": "0x1"
0155 },
0156 {
0157 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
0158 "Counter": "0,1,2,3",
0159 "EventCode": "0XB7",
0160 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
0161 "MSRIndex": "0x1a6,0x1a7",
0162 "MSRValue": "0x2184000002",
0163 "Offcore": "1",
0164 "SampleAfterValue": "100003",
0165 "UMask": "0x1"
0166 },
0167 {
0168 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
0169 "Counter": "0,1,2,3",
0170 "EventCode": "0XB7",
0171 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
0172 "MSRIndex": "0x1a6,0x1a7",
0173 "MSRValue": "0x802184000000",
0174 "Offcore": "1",
0175 "SampleAfterValue": "100003",
0176 "UMask": "0x1"
0177 },
0178 {
0179 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
0180 "Counter": "0,1,2,3",
0181 "EventCode": "0XB7",
0182 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
0183 "MSRIndex": "0x1a6,0x1a7",
0184 "MSRValue": "0x802184000000",
0185 "Offcore": "1",
0186 "SampleAfterValue": "100003",
0187 "UMask": "0x1"
0188 },
0189 {
0190 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
0191 "Counter": "0,1,2,3",
0192 "EventCode": "0XB7",
0193 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
0194 "MSRIndex": "0x1a6,0x1a7",
0195 "MSRValue": "0x2184000040",
0196 "Offcore": "1",
0197 "SampleAfterValue": "100003",
0198 "UMask": "0x1"
0199 },
0200 {
0201 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
0202 "Counter": "0,1,2,3",
0203 "EventCode": "0XB7",
0204 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
0205 "MSRIndex": "0x1a6,0x1a7",
0206 "MSRValue": "0x2184000040",
0207 "Offcore": "1",
0208 "SampleAfterValue": "100003",
0209 "UMask": "0x1"
0210 },
0211 {
0212 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
0213 "Counter": "0,1,2,3",
0214 "EventCode": "0XB7",
0215 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
0216 "MSRIndex": "0x1a6,0x1a7",
0217 "MSRValue": "0x2184000010",
0218 "Offcore": "1",
0219 "SampleAfterValue": "100003",
0220 "UMask": "0x1"
0221 },
0222 {
0223 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
0224 "Counter": "0,1,2,3",
0225 "EventCode": "0XB7",
0226 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
0227 "MSRIndex": "0x1a6,0x1a7",
0228 "MSRValue": "0x2184000010",
0229 "Offcore": "1",
0230 "SampleAfterValue": "100003",
0231 "UMask": "0x1"
0232 },
0233 {
0234 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
0235 "Counter": "0,1,2,3",
0236 "EventCode": "0XB7",
0237 "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
0238 "MSRIndex": "0x1a6,0x1a7",
0239 "MSRValue": "0x2184000020",
0240 "Offcore": "1",
0241 "SampleAfterValue": "100003",
0242 "UMask": "0x1"
0243 },
0244 {
0245 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
0246 "Counter": "0,1,2,3",
0247 "EventCode": "0XB7",
0248 "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
0249 "MSRIndex": "0x1a6,0x1a7",
0250 "MSRValue": "0x2184000020",
0251 "Offcore": "1",
0252 "SampleAfterValue": "100003",
0253 "UMask": "0x1"
0254 },
0255 {
0256 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
0257 "Counter": "0,1,2,3",
0258 "EventCode": "0XB7",
0259 "EventName": "OCR.L1WB_M.L3_MISS",
0260 "MSRIndex": "0x1a6,0x1a7",
0261 "MSRValue": "0x1002184000000",
0262 "Offcore": "1",
0263 "SampleAfterValue": "100003",
0264 "UMask": "0x1"
0265 },
0266 {
0267 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
0268 "Counter": "0,1,2,3",
0269 "EventCode": "0XB7",
0270 "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
0271 "MSRIndex": "0x1a6,0x1a7",
0272 "MSRValue": "0x1002184000000",
0273 "Offcore": "1",
0274 "SampleAfterValue": "100003",
0275 "UMask": "0x1"
0276 },
0277 {
0278 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
0279 "Counter": "0,1,2,3",
0280 "EventCode": "0XB7",
0281 "EventName": "OCR.L2WB_M.L3_MISS",
0282 "MSRIndex": "0x1a6,0x1a7",
0283 "MSRValue": "0x2002184000000",
0284 "Offcore": "1",
0285 "SampleAfterValue": "100003",
0286 "UMask": "0x1"
0287 },
0288 {
0289 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
0290 "Counter": "0,1,2,3",
0291 "EventCode": "0XB7",
0292 "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
0293 "MSRIndex": "0x1a6,0x1a7",
0294 "MSRValue": "0x2002184000000",
0295 "Offcore": "1",
0296 "SampleAfterValue": "100003",
0297 "UMask": "0x1"
0298 },
0299 {
0300 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
0301 "Counter": "0,1,2,3",
0302 "EventCode": "0XB7",
0303 "EventName": "OCR.OTHER.L3_MISS",
0304 "MSRIndex": "0x1a6,0x1a7",
0305 "MSRValue": "0x2184008000",
0306 "Offcore": "1",
0307 "SampleAfterValue": "100003",
0308 "UMask": "0x1"
0309 },
0310 {
0311 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
0312 "Counter": "0,1,2,3",
0313 "EventCode": "0XB7",
0314 "EventName": "OCR.OTHER.L3_MISS_LOCAL",
0315 "MSRIndex": "0x1a6,0x1a7",
0316 "MSRValue": "0x2184008000",
0317 "Offcore": "1",
0318 "SampleAfterValue": "100003",
0319 "UMask": "0x1"
0320 },
0321 {
0322 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
0323 "Counter": "0,1,2,3",
0324 "EventCode": "0XB7",
0325 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
0326 "MSRIndex": "0x1a6,0x1a7",
0327 "MSRValue": "0x402184000000",
0328 "Offcore": "1",
0329 "SampleAfterValue": "100003",
0330 "UMask": "0x1"
0331 },
0332 {
0333 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
0334 "Counter": "0,1,2,3",
0335 "EventCode": "0XB7",
0336 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
0337 "MSRIndex": "0x1a6,0x1a7",
0338 "MSRValue": "0x402184000000",
0339 "Offcore": "1",
0340 "SampleAfterValue": "100003",
0341 "UMask": "0x1"
0342 },
0343 {
0344 "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
0345 "Counter": "0,1,2,3",
0346 "EventCode": "0XB7",
0347 "EventName": "OCR.PREFETCHES.L3_MISS",
0348 "MSRIndex": "0x1a6,0x1a7",
0349 "MSRValue": "0x2184000470",
0350 "Offcore": "1",
0351 "SampleAfterValue": "100003",
0352 "UMask": "0x1"
0353 },
0354 {
0355 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
0356 "Counter": "0,1,2,3",
0357 "EventCode": "0XB7",
0358 "EventName": "OCR.READS_TO_CORE.L3_MISS",
0359 "MSRIndex": "0x1a6,0x1a7",
0360 "MSRValue": "0x2184000477",
0361 "Offcore": "1",
0362 "SampleAfterValue": "100003",
0363 "UMask": "0x1"
0364 },
0365 {
0366 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
0367 "Counter": "0,1,2,3",
0368 "EventCode": "0XB7",
0369 "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
0370 "MSRIndex": "0x1a6,0x1a7",
0371 "MSRValue": "0x2184000477",
0372 "Offcore": "1",
0373 "SampleAfterValue": "100003",
0374 "UMask": "0x1"
0375 },
0376 {
0377 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
0378 "Counter": "0,1,2,3",
0379 "EventCode": "0XB7",
0380 "EventName": "OCR.STREAMING_WR.L3_MISS",
0381 "MSRIndex": "0x1a6,0x1a7",
0382 "MSRValue": "0x2184000800",
0383 "Offcore": "1",
0384 "SampleAfterValue": "100003",
0385 "UMask": "0x1"
0386 },
0387 {
0388 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
0389 "Counter": "0,1,2,3",
0390 "EventCode": "0XB7",
0391 "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
0392 "MSRIndex": "0x1a6,0x1a7",
0393 "MSRValue": "0x2184000800",
0394 "Offcore": "1",
0395 "SampleAfterValue": "100003",
0396 "UMask": "0x1"
0397 },
0398 {
0399 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
0400 "Counter": "0,1,2,3",
0401 "EventCode": "0XB7",
0402 "EventName": "OCR.UC_RD.L3_MISS",
0403 "MSRIndex": "0x1a6,0x1a7",
0404 "MSRValue": "0x102184000000",
0405 "Offcore": "1",
0406 "SampleAfterValue": "100003",
0407 "UMask": "0x1"
0408 },
0409 {
0410 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
0411 "Counter": "0,1,2,3",
0412 "EventCode": "0XB7",
0413 "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
0414 "MSRIndex": "0x1a6,0x1a7",
0415 "MSRValue": "0x102184000000",
0416 "Offcore": "1",
0417 "SampleAfterValue": "100003",
0418 "UMask": "0x1"
0419 },
0420 {
0421 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
0422 "Counter": "0,1,2,3",
0423 "EventCode": "0XB7",
0424 "EventName": "OCR.UC_WR.L3_MISS",
0425 "MSRIndex": "0x1a6,0x1a7",
0426 "MSRValue": "0x202184000000",
0427 "Offcore": "1",
0428 "SampleAfterValue": "100003",
0429 "UMask": "0x1"
0430 },
0431 {
0432 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
0433 "Counter": "0,1,2,3",
0434 "EventCode": "0XB7",
0435 "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
0436 "MSRIndex": "0x1a6,0x1a7",
0437 "MSRValue": "0x202184000000",
0438 "Offcore": "1",
0439 "SampleAfterValue": "100003",
0440 "UMask": "0x1"
0441 }
0442 ]
