0001 [
0002 {
0003 "BriefDescription": "DRAM Page Activate commands sent due to a write request",
0004 "Counter": "0,1,2,3",
0005 "EventCode": "0x1",
0006 "EventName": "UNC_M_ACT_COUNT.WR",
0007 "PerPkg": "1",
0008 "UMask": "0x2",
0009 "Unit": "iMC"
0010 },
0011 {
0012 "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
0013 "Counter": "0,1,2,3",
0014 "EventCode": "0x4",
0015 "EventName": "UNC_M_CAS_COUNT.RD_REG",
0016 "PerPkg": "1",
0017 "UMask": "0x1",
0018 "Unit": "iMC"
0019 },
0020 {
0021 "BriefDescription": "DRAM Underfill Read CAS Commands issued",
0022 "Counter": "0,1,2,3",
0023 "EventCode": "0x4",
0024 "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
0025 "PerPkg": "1",
0026 "UMask": "0x2",
0027 "Unit": "iMC"
0028 },
0029 {
0030 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
0031 "Counter": "0,1,2,3",
0032 "EventCode": "0x4",
0033 "EventName": "LLC_MISSES.MEM_READ",
0034 "PerPkg": "1",
0035 "ScaleUnit": "64Bytes",
0036 "UMask": "0x3",
0037 "Unit": "iMC"
0038 },
0039 {
0040 "BriefDescription": "read requests to memory controller",
0041 "Counter": "0,1,2,3",
0042 "EventCode": "0x4",
0043 "EventName": "UNC_M_CAS_COUNT.RD",
0044 "PerPkg": "1",
0045 "ScaleUnit": "64Bytes",
0046 "UMask": "0x3",
0047 "Unit": "iMC"
0048 },
0049 {
0050 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
0051 "Counter": "0,1,2,3",
0052 "EventCode": "0x4",
0053 "EventName": "UNC_M_CAS_COUNT.WR_WMM",
0054 "PerPkg": "1",
0055 "UMask": "0x4",
0056 "Unit": "iMC"
0057 },
0058 {
0059 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
0060 "Counter": "0,1,2,3",
0061 "EventCode": "0x4",
0062 "EventName": "LLC_MISSES.MEM_WRITE",
0063 "PerPkg": "1",
0064 "ScaleUnit": "64Bytes",
0065 "UMask": "0xC",
0066 "Unit": "iMC"
0067 },
0068 {
0069 "BriefDescription": "write requests to memory controller",
0070 "Counter": "0,1,2,3",
0071 "EventCode": "0x4",
0072 "EventName": "UNC_M_CAS_COUNT.WR",
0073 "PerPkg": "1",
0074 "ScaleUnit": "64Bytes",
0075 "UMask": "0xC",
0076 "Unit": "iMC"
0077 },
0078 {
0079 "BriefDescription": "All DRAM CAS Commands issued",
0080 "Counter": "0,1,2,3",
0081 "EventCode": "0x4",
0082 "EventName": "UNC_M_CAS_COUNT.ALL",
0083 "PerPkg": "1",
0084 "UMask": "0xF",
0085 "Unit": "iMC"
0086 },
0087 {
0088 "BriefDescription": "Memory controller clock ticks",
0089 "Counter": "0,1,2,3",
0090 "EventName": "UNC_M_CLOCKTICKS",
0091 "PerPkg": "1",
0092 "Unit": "iMC"
0093 },
0094 {
0095 "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
0096 "Counter": "0,1,2,3",
0097 "EventCode": "0x85",
0098 "EventName": "UNC_M_POWER_CHANNEL_PPD",
0099 "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
0100 "MetricName": "power_channel_ppd %",
0101 "PerPkg": "1",
0102 "Unit": "iMC"
0103 },
0104 {
0105 "BriefDescription": "Cycles Memory is in self refresh power mode",
0106 "Counter": "0,1,2,3",
0107 "EventCode": "0x43",
0108 "EventName": "UNC_M_POWER_SELF_REFRESH",
0109 "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
0110 "MetricName": "power_self_refresh %",
0111 "PerPkg": "1",
0112 "Unit": "iMC"
0113 },
0114 {
0115 "BriefDescription": "Pre-charges due to page misses",
0116 "Counter": "0,1,2,3",
0117 "EventCode": "0x2",
0118 "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
0119 "PerPkg": "1",
0120 "UMask": "0x1",
0121 "Unit": "iMC"
0122 },
0123 {
0124 "BriefDescription": "Pre-charge for reads",
0125 "Counter": "0,1,2,3",
0126 "EventCode": "0x2",
0127 "EventName": "UNC_M_PRE_COUNT.RD",
0128 "PerPkg": "1",
0129 "UMask": "0x4",
0130 "Unit": "iMC"
0131 },
0132 {
0133 "BriefDescription": "Read Pending Queue Allocations",
0134 "Counter": "0,1,2,3",
0135 "EventCode": "0x10",
0136 "EventName": "UNC_M_RPQ_INSERTS",
0137 "PerPkg": "1",
0138 "Unit": "iMC"
0139 },
0140 {
0141 "BriefDescription": "Read Pending Queue Occupancy",
0142 "Counter": "0,1,2,3",
0143 "EventCode": "0x80",
0144 "EventName": "UNC_M_RPQ_OCCUPANCY",
0145 "PerPkg": "1",
0146 "Unit": "iMC"
0147 },
0148 {
0149 "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode",
0150 "Counter": "0,1,2,3",
0151 "EventCode": "0xD3",
0152 "EventName": "UNC_M_TAGCHK.HIT",
0153 "PerPkg": "1",
0154 "UMask": "0x1",
0155 "Unit": "iMC"
0156 },
0157 {
0158 "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode",
0159 "Counter": "0,1,2,3",
0160 "EventCode": "0xD3",
0161 "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
0162 "PerPkg": "1",
0163 "UMask": "0x2",
0164 "Unit": "iMC"
0165 },
0166 {
0167 "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode",
0168 "Counter": "0,1,2,3",
0169 "EventCode": "0xD3",
0170 "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
0171 "PerPkg": "1",
0172 "UMask": "0x4",
0173 "Unit": "iMC"
0174 },
0175 {
0176 "BriefDescription": "Write Pending Queue Allocations",
0177 "Counter": "0,1,2,3",
0178 "EventCode": "0x20",
0179 "EventName": "UNC_M_WPQ_INSERTS",
0180 "PerPkg": "1",
0181 "Unit": "iMC"
0182 },
0183 {
0184 "BriefDescription": "Write Pending Queue Occupancy",
0185 "Counter": "0,1,2,3",
0186 "EventCode": "0x81",
0187 "EventName": "UNC_M_WPQ_OCCUPANCY",
0188 "PerPkg": "1",
0189 "Unit": "iMC"
0190 },
0191 {
0192 "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
0193 "Counter": "0,1,2,3",
0194 "EventCode": "0xE0",
0195 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
0196 "PerPkg": "1",
0197 "UMask": "0x1",
0198 "Unit": "iMC"
0199 },
0200 {
0201 "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all",
0202 "Counter": "0,1,2,3",
0203 "EventCode": "0xE0",
0204 "EventName": "UNC_M_PMM_READ_LATENCY",
0205 "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
0206 "MetricName": "UNC_M_PMM_READ_LATENCY",
0207 "PerPkg": "1",
0208 "ScaleUnit": "6000000000ns",
0209 "UMask": "0x1",
0210 "Unit": "iMC"
0211 },
0212 {
0213 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
0214 "Counter": "0,1,2,3",
0215 "EventCode": "0xE3",
0216 "EventName": "UNC_M_PMM_RPQ_INSERTS",
0217 "PerPkg": "1",
0218 "Unit": "iMC"
0219 },
0220 {
0221 "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts",
0222 "Counter": "0,1,2,3",
0223 "EventCode": "0xE3",
0224 "EventName": "UNC_M_PMM_BANDWIDTH.READ",
0225 "PerPkg": "1",
0226 "ScaleUnit": "6.103515625E-5MB/sec",
0227 "Unit": "iMC"
0228 },
0229 {
0230 "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
0231 "Counter": "0,1,2,3",
0232 "EventCode": "0xE3",
0233 "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL",
0234 "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
0235 "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL",
0236 "PerPkg": "1",
0237 "ScaleUnit": "6.103515625E-5MB/sec",
0238 "Unit": "iMC"
0239 },
0240 {
0241 "BriefDescription": "All commands for Intel Optane DC persistent memory",
0242 "Counter": "0,1,2,3",
0243 "EventCode": "0xEA",
0244 "EventName": "UNC_M_PMM_CMD1.ALL",
0245 "PerPkg": "1",
0246 "UMask": "0x1",
0247 "Unit": "iMC"
0248 },
0249 {
0250 "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory",
0251 "Counter": "0,1,2,3",
0252 "EventCode": "0xEA",
0253 "EventName": "UNC_M_PMM_CMD1.RD",
0254 "PerPkg": "1",
0255 "UMask": "0x2",
0256 "Unit": "iMC"
0257 },
0258 {
0259 "BriefDescription": "Write commands for Intel Optane DC persistent memory",
0260 "Counter": "0,1,2,3",
0261 "EventCode": "0xEA",
0262 "EventName": "UNC_M_PMM_CMD1.WR",
0263 "PerPkg": "1",
0264 "UMask": "0x4",
0265 "Unit": "iMC"
0266 },
0267 {
0268 "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory",
0269 "Counter": "0,1,2,3",
0270 "EventCode": "0xEA",
0271 "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
0272 "PerPkg": "1",
0273 "UMask": "0x8",
0274 "Unit": "iMC"
0275 },
0276 {
0277 "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
0278 "Counter": "0,1,2,3",
0279 "EventCode": "0xE7",
0280 "EventName": "UNC_M_PMM_WPQ_INSERTS",
0281 "PerPkg": "1",
0282 "Unit": "iMC"
0283 },
0284 {
0285 "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
0286 "Counter": "0,1,2,3",
0287 "EventCode": "0xE7",
0288 "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
0289 "PerPkg": "1",
0290 "ScaleUnit": "6.103515625E-5MB/sec",
0291 "Unit": "iMC"
0292 },
0293 {
0294 "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory",
0295 "Counter": "0,1,2,3",
0296 "EventCode": "0xE4",
0297 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
0298 "PerPkg": "1",
0299 "UMask": "0x1",
0300 "Unit": "iMC"
0301 },
0302 {
0303 "BriefDescription": "DRAM Activate Count; Activate due to Read",
0304 "Counter": "0,1,2,3",
0305 "EventCode": "0x1",
0306 "EventName": "UNC_M_ACT_COUNT.RD",
0307 "PerPkg": "1",
0308 "UMask": "0x1",
0309 "Unit": "iMC"
0310 },
0311 {
0312 "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
0313 "Counter": "0,1,2,3",
0314 "EventCode": "0x1",
0315 "EventName": "UNC_M_ACT_COUNT.BYP",
0316 "PerPkg": "1",
0317 "UMask": "0x8",
0318 "Unit": "iMC"
0319 },
0320 {
0321 "BriefDescription": "ACT command issued by 2 cycle bypass",
0322 "Counter": "0,1,2,3",
0323 "EventCode": "0xA1",
0324 "EventName": "UNC_M_BYP_CMDS.ACT",
0325 "PerPkg": "1",
0326 "UMask": "0x1",
0327 "Unit": "iMC"
0328 },
0329 {
0330 "BriefDescription": "CAS command issued by 2 cycle bypass",
0331 "Counter": "0,1,2,3",
0332 "EventCode": "0xA1",
0333 "EventName": "UNC_M_BYP_CMDS.CAS",
0334 "PerPkg": "1",
0335 "UMask": "0x2",
0336 "Unit": "iMC"
0337 },
0338 {
0339 "BriefDescription": "PRE command issued by 2 cycle bypass",
0340 "Counter": "0,1,2,3",
0341 "EventCode": "0xA1",
0342 "EventName": "UNC_M_BYP_CMDS.PRE",
0343 "PerPkg": "1",
0344 "UMask": "0x4",
0345 "Unit": "iMC"
0346 },
0347 {
0348 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
0349 "Counter": "0,1,2,3",
0350 "EventCode": "0x4",
0351 "EventName": "UNC_M_CAS_COUNT.WR_RMM",
0352 "PerPkg": "1",
0353 "UMask": "0x8",
0354 "Unit": "iMC"
0355 },
0356 {
0357 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
0358 "Counter": "0,1,2,3",
0359 "EventCode": "0x4",
0360 "EventName": "UNC_M_CAS_COUNT.RD_WMM",
0361 "PerPkg": "1",
0362 "UMask": "0x10",
0363 "Unit": "iMC"
0364 },
0365 {
0366 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
0367 "Counter": "0,1,2,3",
0368 "EventCode": "0x4",
0369 "EventName": "UNC_M_CAS_COUNT.RD_RMM",
0370 "PerPkg": "1",
0371 "UMask": "0x20",
0372 "Unit": "iMC"
0373 },
0374 {
0375 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
0376 "Counter": "0,1,2,3",
0377 "EventCode": "0x4",
0378 "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
0379 "PerPkg": "1",
0380 "UMask": "0x40",
0381 "Unit": "iMC"
0382 },
0383 {
0384 "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
0385 "Counter": "0,1,2,3",
0386 "EventCode": "0x4",
0387 "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
0388 "PerPkg": "1",
0389 "UMask": "0x80",
0390 "Unit": "iMC"
0391 },
0392 {
0393 "BriefDescription": "DRAM Precharge All Commands",
0394 "Counter": "0,1,2,3",
0395 "EventCode": "0x6",
0396 "EventName": "UNC_M_DRAM_PRE_ALL",
0397 "PerPkg": "1",
0398 "Unit": "iMC"
0399 },
0400 {
0401 "BriefDescription": "ECC Correctable Errors",
0402 "Counter": "0,1,2,3",
0403 "EventCode": "0x9",
0404 "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
0405 "PerPkg": "1",
0406 "Unit": "iMC"
0407 },
0408 {
0409 "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
0410 "Counter": "0,1,2,3",
0411 "EventCode": "0x7",
0412 "EventName": "UNC_M_MAJOR_MODES.READ",
0413 "PerPkg": "1",
0414 "UMask": "0x1",
0415 "Unit": "iMC"
0416 },
0417 {
0418 "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
0419 "Counter": "0,1,2,3",
0420 "EventCode": "0x7",
0421 "EventName": "UNC_M_MAJOR_MODES.WRITE",
0422 "PerPkg": "1",
0423 "UMask": "0x2",
0424 "Unit": "iMC"
0425 },
0426 {
0427 "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
0428 "Counter": "0,1,2,3",
0429 "EventCode": "0x7",
0430 "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
0431 "PerPkg": "1",
0432 "UMask": "0x4",
0433 "Unit": "iMC"
0434 },
0435 {
0436 "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
0437 "Counter": "0,1,2,3",
0438 "EventCode": "0x7",
0439 "EventName": "UNC_M_MAJOR_MODES.ISOCH",
0440 "PerPkg": "1",
0441 "UMask": "0x8",
0442 "Unit": "iMC"
0443 },
0444 {
0445 "BriefDescription": "Channel DLLOFF Cycles",
0446 "Counter": "0,1,2,3",
0447 "EventCode": "0x84",
0448 "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
0449 "PerPkg": "1",
0450 "Unit": "iMC"
0451 },
0452 {
0453 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0454 "Counter": "0,1,2,3",
0455 "EventCode": "0x83",
0456 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
0457 "PerPkg": "1",
0458 "UMask": "0x1",
0459 "Unit": "iMC"
0460 },
0461 {
0462 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0463 "Counter": "0,1,2,3",
0464 "EventCode": "0x83",
0465 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
0466 "PerPkg": "1",
0467 "UMask": "0x2",
0468 "Unit": "iMC"
0469 },
0470 {
0471 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0472 "Counter": "0,1,2,3",
0473 "EventCode": "0x83",
0474 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
0475 "PerPkg": "1",
0476 "UMask": "0x4",
0477 "Unit": "iMC"
0478 },
0479 {
0480 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0481 "Counter": "0,1,2,3",
0482 "EventCode": "0x83",
0483 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
0484 "PerPkg": "1",
0485 "UMask": "0x8",
0486 "Unit": "iMC"
0487 },
0488 {
0489 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0490 "Counter": "0,1,2,3",
0491 "EventCode": "0x83",
0492 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
0493 "PerPkg": "1",
0494 "UMask": "0x10",
0495 "Unit": "iMC"
0496 },
0497 {
0498 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0499 "Counter": "0,1,2,3",
0500 "EventCode": "0x83",
0501 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
0502 "PerPkg": "1",
0503 "UMask": "0x20",
0504 "Unit": "iMC"
0505 },
0506 {
0507 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0508 "Counter": "0,1,2,3",
0509 "EventCode": "0x83",
0510 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
0511 "PerPkg": "1",
0512 "UMask": "0x40",
0513 "Unit": "iMC"
0514 },
0515 {
0516 "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
0517 "Counter": "0,1,2,3",
0518 "EventCode": "0x83",
0519 "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
0520 "PerPkg": "1",
0521 "UMask": "0x80",
0522 "Unit": "iMC"
0523 },
0524 {
0525 "BriefDescription": "Critical Throttle Cycles",
0526 "Counter": "0,1,2,3",
0527 "EventCode": "0x86",
0528 "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
0529 "PerPkg": "1",
0530 "Unit": "iMC"
0531 },
0532 {
0533 "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
0534 "Counter": "0,1,2,3",
0535 "EventCode": "0x42",
0536 "EventName": "UNC_M_POWER_PCU_THROTTLING",
0537 "PerPkg": "1",
0538 "Unit": "iMC"
0539 },
0540 {
0541 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0542 "Counter": "0,1,2,3",
0543 "EventCode": "0x41",
0544 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
0545 "PerPkg": "1",
0546 "UMask": "0x1",
0547 "Unit": "iMC"
0548 },
0549 {
0550 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0551 "Counter": "0,1,2,3",
0552 "EventCode": "0x41",
0553 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
0554 "PerPkg": "1",
0555 "UMask": "0x2",
0556 "Unit": "iMC"
0557 },
0558 {
0559 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0560 "Counter": "0,1,2,3",
0561 "EventCode": "0x41",
0562 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
0563 "PerPkg": "1",
0564 "UMask": "0x4",
0565 "Unit": "iMC"
0566 },
0567 {
0568 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0569 "Counter": "0,1,2,3",
0570 "EventCode": "0x41",
0571 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
0572 "PerPkg": "1",
0573 "UMask": "0x8",
0574 "Unit": "iMC"
0575 },
0576 {
0577 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0578 "Counter": "0,1,2,3",
0579 "EventCode": "0x41",
0580 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
0581 "PerPkg": "1",
0582 "UMask": "0x10",
0583 "Unit": "iMC"
0584 },
0585 {
0586 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0587 "Counter": "0,1,2,3",
0588 "EventCode": "0x41",
0589 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
0590 "PerPkg": "1",
0591 "UMask": "0x20",
0592 "Unit": "iMC"
0593 },
0594 {
0595 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0596 "Counter": "0,1,2,3",
0597 "EventCode": "0x41",
0598 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
0599 "PerPkg": "1",
0600 "UMask": "0x40",
0601 "Unit": "iMC"
0602 },
0603 {
0604 "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
0605 "Counter": "0,1,2,3",
0606 "EventCode": "0x41",
0607 "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
0608 "PerPkg": "1",
0609 "UMask": "0x80",
0610 "Unit": "iMC"
0611 },
0612 {
0613 "BriefDescription": "Read Preemption Count; Read over Read Preemption",
0614 "Counter": "0,1,2,3",
0615 "EventCode": "0x8",
0616 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
0617 "PerPkg": "1",
0618 "UMask": "0x1",
0619 "Unit": "iMC"
0620 },
0621 {
0622 "BriefDescription": "Read Preemption Count; Read over Write Preemption",
0623 "Counter": "0,1,2,3",
0624 "EventCode": "0x8",
0625 "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
0626 "PerPkg": "1",
0627 "UMask": "0x2",
0628 "Unit": "iMC"
0629 },
0630 {
0631 "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
0632 "Counter": "0,1,2,3",
0633 "EventCode": "0x2",
0634 "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
0635 "PerPkg": "1",
0636 "UMask": "0x2",
0637 "Unit": "iMC"
0638 },
0639 {
0640 "BriefDescription": "Pre-charge for writes",
0641 "Counter": "0,1,2,3",
0642 "EventCode": "0x2",
0643 "EventName": "UNC_M_PRE_COUNT.WR",
0644 "PerPkg": "1",
0645 "UMask": "0x8",
0646 "Unit": "iMC"
0647 },
0648 {
0649 "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
0650 "Counter": "0,1,2,3",
0651 "EventCode": "0x2",
0652 "EventName": "UNC_M_PRE_COUNT.BYP",
0653 "PerPkg": "1",
0654 "UMask": "0x10",
0655 "Unit": "iMC"
0656 },
0657 {
0658 "BriefDescription": "Read CAS issued with LOW priority",
0659 "Counter": "0,1,2,3",
0660 "EventCode": "0xA0",
0661 "EventName": "UNC_M_RD_CAS_PRIO.LOW",
0662 "PerPkg": "1",
0663 "UMask": "0x1",
0664 "Unit": "iMC"
0665 },
0666 {
0667 "BriefDescription": "Read CAS issued with MEDIUM priority",
0668 "Counter": "0,1,2,3",
0669 "EventCode": "0xA0",
0670 "EventName": "UNC_M_RD_CAS_PRIO.MED",
0671 "PerPkg": "1",
0672 "UMask": "0x2",
0673 "Unit": "iMC"
0674 },
0675 {
0676 "BriefDescription": "Read CAS issued with HIGH priority",
0677 "Counter": "0,1,2,3",
0678 "EventCode": "0xA0",
0679 "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
0680 "PerPkg": "1",
0681 "UMask": "0x4",
0682 "Unit": "iMC"
0683 },
0684 {
0685 "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
0686 "Counter": "0,1,2,3",
0687 "EventCode": "0xA0",
0688 "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
0689 "PerPkg": "1",
0690 "UMask": "0x8",
0691 "Unit": "iMC"
0692 },
0693 {
0694 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
0695 "Counter": "0,1,2,3",
0696 "EventCode": "0xB0",
0697 "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
0698 "PerPkg": "1",
0699 "Unit": "iMC"
0700 },
0701 {
0702 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
0703 "Counter": "0,1,2,3",
0704 "EventCode": "0xB0",
0705 "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
0706 "PerPkg": "1",
0707 "UMask": "0x1",
0708 "Unit": "iMC"
0709 },
0710 {
0711 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
0712 "Counter": "0,1,2,3",
0713 "EventCode": "0xB0",
0714 "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
0715 "PerPkg": "1",
0716 "UMask": "0x2",
0717 "Unit": "iMC"
0718 },
0719 {
0720 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
0721 "Counter": "0,1,2,3",
0722 "EventCode": "0xB0",
0723 "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
0724 "PerPkg": "1",
0725 "UMask": "0x3",
0726 "Unit": "iMC"
0727 },
0728 {
0729 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
0730 "Counter": "0,1,2,3",
0731 "EventCode": "0xB0",
0732 "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
0733 "PerPkg": "1",
0734 "UMask": "0x4",
0735 "Unit": "iMC"
0736 },
0737 {
0738 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
0739 "Counter": "0,1,2,3",
0740 "EventCode": "0xB0",
0741 "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
0742 "PerPkg": "1",
0743 "UMask": "0x5",
0744 "Unit": "iMC"
0745 },
0746 {
0747 "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
0748 "Counter": "0,1,2,3",
0749 "EventCode": "0xB0",
0750 "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
0751 "PerPkg": "1",
0752 "UMask": "0x6",
0753 "Unit": "iMC"
0754 },
0755 {
0756 "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
0757 "Counter": "0,1,2,3",
0758 "EventCode": "0xB0",
0759 "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
0760 "PerPkg": "1",
0761 "UMask": "0x7",
0762 "Unit": "iMC"
0763 },
0764 {
0765 "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
0766 "Counter": "0,1,2,3",
0767 "EventCode": "0xB0",
0768 "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
0769 "PerPkg": "1",
0770 "UMask": "0x8",
0771 "Unit": "iMC"
0772 },
0773 {
0774 "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
0775 "Counter": "0,1,2,3",
0776 "EventCode": "0xB0",
0777 "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
0778 "PerPkg": "1",
0779 "UMask": "0x9",
0780 "Unit": "iMC"
0781 },
0782 {
0783 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
0784 "Counter": "0,1,2,3",
0785 "EventCode": "0xB0",
0786 "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
0787 "PerPkg": "1",
0788 "UMask": "0xA",
0789 "Unit": "iMC"
0790 },
0791 {
0792 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
0793 "Counter": "0,1,2,3",
0794 "EventCode": "0xB0",
0795 "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
0796 "PerPkg": "1",
0797 "UMask": "0xB",
0798 "Unit": "iMC"
0799 },
0800 {
0801 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
0802 "Counter": "0,1,2,3",
0803 "EventCode": "0xB0",
0804 "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
0805 "PerPkg": "1",
0806 "UMask": "0xC",
0807 "Unit": "iMC"
0808 },
0809 {
0810 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
0811 "Counter": "0,1,2,3",
0812 "EventCode": "0xB0",
0813 "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
0814 "PerPkg": "1",
0815 "UMask": "0xD",
0816 "Unit": "iMC"
0817 },
0818 {
0819 "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
0820 "Counter": "0,1,2,3",
0821 "EventCode": "0xB0",
0822 "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
0823 "PerPkg": "1",
0824 "UMask": "0xE",
0825 "Unit": "iMC"
0826 },
0827 {
0828 "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
0829 "Counter": "0,1,2,3",
0830 "EventCode": "0xB0",
0831 "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
0832 "PerPkg": "1",
0833 "UMask": "0xF",
0834 "Unit": "iMC"
0835 },
0836 {
0837 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
0838 "Counter": "0,1,2,3",
0839 "EventCode": "0xB0",
0840 "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
0841 "PerPkg": "1",
0842 "UMask": "0x10",
0843 "Unit": "iMC"
0844 },
0845 {
0846 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
0847 "Counter": "0,1,2,3",
0848 "EventCode": "0xB0",
0849 "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
0850 "PerPkg": "1",
0851 "UMask": "0x11",
0852 "Unit": "iMC"
0853 },
0854 {
0855 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
0856 "Counter": "0,1,2,3",
0857 "EventCode": "0xB0",
0858 "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
0859 "PerPkg": "1",
0860 "UMask": "0x12",
0861 "Unit": "iMC"
0862 },
0863 {
0864 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
0865 "Counter": "0,1,2,3",
0866 "EventCode": "0xB0",
0867 "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
0868 "PerPkg": "1",
0869 "UMask": "0x13",
0870 "Unit": "iMC"
0871 },
0872 {
0873 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
0874 "Counter": "0,1,2,3",
0875 "EventCode": "0xB0",
0876 "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
0877 "PerPkg": "1",
0878 "UMask": "0x14",
0879 "Unit": "iMC"
0880 },
0881 {
0882 "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
0883 "Counter": "0,1,2,3",
0884 "EventCode": "0xB1",
0885 "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
0886 "PerPkg": "1",
0887 "Unit": "iMC"
0888 },
0889 {
0890 "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
0891 "Counter": "0,1,2,3",
0892 "EventCode": "0xB1",
0893 "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
0894 "PerPkg": "1",
0895 "UMask": "0x1",
0896 "Unit": "iMC"
0897 },
0898 {
0899 "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
0900 "Counter": "0,1,2,3",
0901 "EventCode": "0xB1",
0902 "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
0903 "PerPkg": "1",
0904 "UMask": "0x2",
0905 "Unit": "iMC"
0906 },
0907 {
0908 "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
0909 "Counter": "0,1,2,3",
0910 "EventCode": "0xB1",
0911 "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
0912 "PerPkg": "1",
0913 "UMask": "0x3",
0914 "Unit": "iMC"
0915 },
0916 {
0917 "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
0918 "Counter": "0,1,2,3",
0919 "EventCode": "0xB1",
0920 "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
0921 "PerPkg": "1",
0922 "UMask": "0x4",
0923 "Unit": "iMC"
0924 },
0925 {
0926 "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
0927 "Counter": "0,1,2,3",
0928 "EventCode": "0xB1",
0929 "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
0930 "PerPkg": "1",
0931 "UMask": "0x5",
0932 "Unit": "iMC"
0933 },
0934 {
0935 "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
0936 "Counter": "0,1,2,3",
0937 "EventCode": "0xB1",
0938 "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
0939 "PerPkg": "1",
0940 "UMask": "0x6",
0941 "Unit": "iMC"
0942 },
0943 {
0944 "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
0945 "Counter": "0,1,2,3",
0946 "EventCode": "0xB1",
0947 "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
0948 "PerPkg": "1",
0949 "UMask": "0x7",
0950 "Unit": "iMC"
0951 },
0952 {
0953 "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
0954 "Counter": "0,1,2,3",
0955 "EventCode": "0xB1",
0956 "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
0957 "PerPkg": "1",
0958 "UMask": "0x8",
0959 "Unit": "iMC"
0960 },
0961 {
0962 "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
0963 "Counter": "0,1,2,3",
0964 "EventCode": "0xB1",
0965 "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
0966 "PerPkg": "1",
0967 "UMask": "0x9",
0968 "Unit": "iMC"
0969 },
0970 {
0971 "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
0972 "Counter": "0,1,2,3",
0973 "EventCode": "0xB1",
0974 "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
0975 "PerPkg": "1",
0976 "UMask": "0xA",
0977 "Unit": "iMC"
0978 },
0979 {
0980 "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
0981 "Counter": "0,1,2,3",
0982 "EventCode": "0xB1",
0983 "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
0984 "PerPkg": "1",
0985 "UMask": "0xB",
0986 "Unit": "iMC"
0987 },
0988 {
0989 "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
0990 "Counter": "0,1,2,3",
0991 "EventCode": "0xB1",
0992 "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
0993 "PerPkg": "1",
0994 "UMask": "0xC",
0995 "Unit": "iMC"
0996 },
0997 {
0998 "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
0999 "Counter": "0,1,2,3",
1000 "EventCode": "0xB1",
1001 "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
1002 "PerPkg": "1",
1003 "UMask": "0xD",
1004 "Unit": "iMC"
1005 },
1006 {
1007 "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
1008 "Counter": "0,1,2,3",
1009 "EventCode": "0xB1",
1010 "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
1011 "PerPkg": "1",
1012 "UMask": "0xE",
1013 "Unit": "iMC"
1014 },
1015 {
1016 "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
1017 "Counter": "0,1,2,3",
1018 "EventCode": "0xB1",
1019 "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
1020 "PerPkg": "1",
1021 "UMask": "0xF",
1022 "Unit": "iMC"
1023 },
1024 {
1025 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
1026 "Counter": "0,1,2,3",
1027 "EventCode": "0xB1",
1028 "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
1029 "PerPkg": "1",
1030 "UMask": "0x10",
1031 "Unit": "iMC"
1032 },
1033 {
1034 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
1035 "Counter": "0,1,2,3",
1036 "EventCode": "0xB1",
1037 "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
1038 "PerPkg": "1",
1039 "UMask": "0x11",
1040 "Unit": "iMC"
1041 },
1042 {
1043 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
1044 "Counter": "0,1,2,3",
1045 "EventCode": "0xB1",
1046 "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
1047 "PerPkg": "1",
1048 "UMask": "0x12",
1049 "Unit": "iMC"
1050 },
1051 {
1052 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
1053 "Counter": "0,1,2,3",
1054 "EventCode": "0xB1",
1055 "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
1056 "PerPkg": "1",
1057 "UMask": "0x13",
1058 "Unit": "iMC"
1059 },
1060 {
1061 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
1062 "Counter": "0,1,2,3",
1063 "EventCode": "0xB1",
1064 "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
1065 "PerPkg": "1",
1066 "UMask": "0x14",
1067 "Unit": "iMC"
1068 },
1069 {
1070 "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
1071 "Counter": "0,1,2,3",
1072 "EventCode": "0xB2",
1073 "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
1074 "PerPkg": "1",
1075 "Unit": "iMC"
1076 },
1077 {
1078 "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
1079 "Counter": "0,1,2,3",
1080 "EventCode": "0xB2",
1081 "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
1082 "PerPkg": "1",
1083 "UMask": "0x1",
1084 "Unit": "iMC"
1085 },
1086 {
1087 "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
1088 "Counter": "0,1,2,3",
1089 "EventCode": "0xB2",
1090 "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
1091 "PerPkg": "1",
1092 "UMask": "0x2",
1093 "Unit": "iMC"
1094 },
1095 {
1096 "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
1097 "Counter": "0,1,2,3",
1098 "EventCode": "0xB2",
1099 "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
1100 "PerPkg": "1",
1101 "UMask": "0x3",
1102 "Unit": "iMC"
1103 },
1104 {
1105 "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
1106 "Counter": "0,1,2,3",
1107 "EventCode": "0xB2",
1108 "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
1109 "PerPkg": "1",
1110 "UMask": "0x4",
1111 "Unit": "iMC"
1112 },
1113 {
1114 "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
1115 "Counter": "0,1,2,3",
1116 "EventCode": "0xB2",
1117 "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
1118 "PerPkg": "1",
1119 "UMask": "0x5",
1120 "Unit": "iMC"
1121 },
1122 {
1123 "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
1124 "Counter": "0,1,2,3",
1125 "EventCode": "0xB2",
1126 "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
1127 "PerPkg": "1",
1128 "UMask": "0x6",
1129 "Unit": "iMC"
1130 },
1131 {
1132 "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
1133 "Counter": "0,1,2,3",
1134 "EventCode": "0xB2",
1135 "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
1136 "PerPkg": "1",
1137 "UMask": "0x7",
1138 "Unit": "iMC"
1139 },
1140 {
1141 "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
1142 "Counter": "0,1,2,3",
1143 "EventCode": "0xB2",
1144 "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
1145 "PerPkg": "1",
1146 "UMask": "0x8",
1147 "Unit": "iMC"
1148 },
1149 {
1150 "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
1151 "Counter": "0,1,2,3",
1152 "EventCode": "0xB2",
1153 "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
1154 "PerPkg": "1",
1155 "UMask": "0x9",
1156 "Unit": "iMC"
1157 },
1158 {
1159 "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
1160 "Counter": "0,1,2,3",
1161 "EventCode": "0xB2",
1162 "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
1163 "PerPkg": "1",
1164 "UMask": "0xA",
1165 "Unit": "iMC"
1166 },
1167 {
1168 "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
1169 "Counter": "0,1,2,3",
1170 "EventCode": "0xB2",
1171 "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
1172 "PerPkg": "1",
1173 "UMask": "0xB",
1174 "Unit": "iMC"
1175 },
1176 {
1177 "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
1178 "Counter": "0,1,2,3",
1179 "EventCode": "0xB2",
1180 "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
1181 "PerPkg": "1",
1182 "UMask": "0xC",
1183 "Unit": "iMC"
1184 },
1185 {
1186 "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
1187 "Counter": "0,1,2,3",
1188 "EventCode": "0xB2",
1189 "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
1190 "PerPkg": "1",
1191 "UMask": "0xD",
1192 "Unit": "iMC"
1193 },
1194 {
1195 "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
1196 "Counter": "0,1,2,3",
1197 "EventCode": "0xB2",
1198 "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
1199 "PerPkg": "1",
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1797 "EventCode": "0xB5",
1798 "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
1799 "PerPkg": "1",
1800 "UMask": "0x12",
1801 "Unit": "iMC"
1802 },
1803 {
1804 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
1805 "Counter": "0,1,2,3",
1806 "EventCode": "0xB5",
1807 "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
1808 "PerPkg": "1",
1809 "UMask": "0x13",
1810 "Unit": "iMC"
1811 },
1812 {
1813 "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
1814 "Counter": "0,1,2,3",
1815 "EventCode": "0xB5",
1816 "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
1817 "PerPkg": "1",
1818 "UMask": "0x14",
1819 "Unit": "iMC"
1820 },
1821 {
1822 "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
1823 "Counter": "0,1,2,3",
1824 "EventCode": "0xB6",
1825 "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
1826 "PerPkg": "1",
1827 "Unit": "iMC"
1828 },
1829 {
1830 "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
1831 "Counter": "0,1,2,3",
1832 "EventCode": "0xB6",
1833 "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
1834 "PerPkg": "1",
1835 "UMask": "0x1",
1836 "Unit": "iMC"
1837 },
1838 {
1839 "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
1840 "Counter": "0,1,2,3",
1841 "EventCode": "0xB6",
1842 "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
1843 "PerPkg": "1",
1844 "UMask": "0x2",
1845 "Unit": "iMC"
1846 },
1847 {
1848 "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
1849 "Counter": "0,1,2,3",
1850 "EventCode": "0xB6",
1851 "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
1852 "PerPkg": "1",
1853 "UMask": "0x3",
1854 "Unit": "iMC"
1855 },
1856 {
1857 "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
1858 "Counter": "0,1,2,3",
1859 "EventCode": "0xB6",
1860 "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
1861 "PerPkg": "1",
1862 "UMask": "0x4",
1863 "Unit": "iMC"
1864 },
1865 {
1866 "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
1867 "Counter": "0,1,2,3",
1868 "EventCode": "0xB6",
1869 "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
1870 "PerPkg": "1",
1871 "UMask": "0x5",
1872 "Unit": "iMC"
1873 },
1874 {
1875 "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
1876 "Counter": "0,1,2,3",
1877 "EventCode": "0xB6",
1878 "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
1879 "PerPkg": "1",
1880 "UMask": "0x6",
1881 "Unit": "iMC"
1882 },
1883 {
1884 "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
1885 "Counter": "0,1,2,3",
1886 "EventCode": "0xB6",
1887 "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
1888 "PerPkg": "1",
1889 "UMask": "0x7",
1890 "Unit": "iMC"
1891 },
1892 {
1893 "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
1894 "Counter": "0,1,2,3",
1895 "EventCode": "0xB6",
1896 "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
1897 "PerPkg": "1",
1898 "UMask": "0x8",
1899 "Unit": "iMC"
1900 },
1901 {
1902 "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
1903 "Counter": "0,1,2,3",
1904 "EventCode": "0xB6",
1905 "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
1906 "PerPkg": "1",
1907 "UMask": "0x9",
1908 "Unit": "iMC"
1909 },
1910 {
1911 "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
1912 "Counter": "0,1,2,3",
1913 "EventCode": "0xB6",
1914 "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
1915 "PerPkg": "1",
1916 "UMask": "0xA",
1917 "Unit": "iMC"
1918 },
1919 {
1920 "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
1921 "Counter": "0,1,2,3",
1922 "EventCode": "0xB6",
1923 "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
1924 "PerPkg": "1",
1925 "UMask": "0xB",
1926 "Unit": "iMC"
1927 },
1928 {
1929 "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
1930 "Counter": "0,1,2,3",
1931 "EventCode": "0xB6",
1932 "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
1933 "PerPkg": "1",
1934 "UMask": "0xC",
1935 "Unit": "iMC"
1936 },
1937 {
1938 "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
1939 "Counter": "0,1,2,3",
1940 "EventCode": "0xB6",
1941 "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
1942 "PerPkg": "1",
1943 "UMask": "0xD",
1944 "Unit": "iMC"
1945 },
1946 {
1947 "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
1948 "Counter": "0,1,2,3",
1949 "EventCode": "0xB6",
1950 "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
1951 "PerPkg": "1",
1952 "UMask": "0xE",
1953 "Unit": "iMC"
1954 },
1955 {
1956 "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
1957 "Counter": "0,1,2,3",
1958 "EventCode": "0xB6",
1959 "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
1960 "PerPkg": "1",
1961 "UMask": "0xF",
1962 "Unit": "iMC"
1963 },
1964 {
1965 "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
1966 "Counter": "0,1,2,3",
1967 "EventCode": "0xB6",
1968 "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
1969 "PerPkg": "1",
1970 "UMask": "0x10",
1971 "Unit": "iMC"
1972 },
1973 {
1974 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
1975 "Counter": "0,1,2,3",
1976 "EventCode": "0xB6",
1977 "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
1978 "PerPkg": "1",
1979 "UMask": "0x11",
1980 "Unit": "iMC"
1981 },
1982 {
1983 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
1984 "Counter": "0,1,2,3",
1985 "EventCode": "0xB6",
1986 "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
1987 "PerPkg": "1",
1988 "UMask": "0x12",
1989 "Unit": "iMC"
1990 },
1991 {
1992 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
1993 "Counter": "0,1,2,3",
1994 "EventCode": "0xB6",
1995 "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
1996 "PerPkg": "1",
1997 "UMask": "0x13",
1998 "Unit": "iMC"
1999 },
2000 {
2001 "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
2002 "Counter": "0,1,2,3",
2003 "EventCode": "0xB6",
2004 "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
2005 "PerPkg": "1",
2006 "UMask": "0x14",
2007 "Unit": "iMC"
2008 },
2009 {
2010 "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
2011 "Counter": "0,1,2,3",
2012 "EventCode": "0xB7",
2013 "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
2014 "PerPkg": "1",
2015 "Unit": "iMC"
2016 },
2017 {
2018 "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
2019 "Counter": "0,1,2,3",
2020 "EventCode": "0xB7",
2021 "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
2022 "PerPkg": "1",
2023 "UMask": "0x1",
2024 "Unit": "iMC"
2025 },
2026 {
2027 "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
2028 "Counter": "0,1,2,3",
2029 "EventCode": "0xB7",
2030 "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
2031 "PerPkg": "1",
2032 "UMask": "0x2",
2033 "Unit": "iMC"
2034 },
2035 {
2036 "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
2037 "Counter": "0,1,2,3",
2038 "EventCode": "0xB7",
2039 "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
2040 "PerPkg": "1",
2041 "UMask": "0x3",
2042 "Unit": "iMC"
2043 },
2044 {
2045 "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
2046 "Counter": "0,1,2,3",
2047 "EventCode": "0xB7",
2048 "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
2049 "PerPkg": "1",
2050 "UMask": "0x4",
2051 "Unit": "iMC"
2052 },
2053 {
2054 "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
2055 "Counter": "0,1,2,3",
2056 "EventCode": "0xB7",
2057 "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
2058 "PerPkg": "1",
2059 "UMask": "0x5",
2060 "Unit": "iMC"
2061 },
2062 {
2063 "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
2064 "Counter": "0,1,2,3",
2065 "EventCode": "0xB7",
2066 "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
2067 "PerPkg": "1",
2068 "UMask": "0x6",
2069 "Unit": "iMC"
2070 },
2071 {
2072 "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
2073 "Counter": "0,1,2,3",
2074 "EventCode": "0xB7",
2075 "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
2076 "PerPkg": "1",
2077 "UMask": "0x7",
2078 "Unit": "iMC"
2079 },
2080 {
2081 "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
2082 "Counter": "0,1,2,3",
2083 "EventCode": "0xB7",
2084 "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
2085 "PerPkg": "1",
2086 "UMask": "0x8",
2087 "Unit": "iMC"
2088 },
2089 {
2090 "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
2091 "Counter": "0,1,2,3",
2092 "EventCode": "0xB7",
2093 "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
2094 "PerPkg": "1",
2095 "UMask": "0x9",
2096 "Unit": "iMC"
2097 },
2098 {
2099 "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
2100 "Counter": "0,1,2,3",
2101 "EventCode": "0xB7",
2102 "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
2103 "PerPkg": "1",
2104 "UMask": "0xA",
2105 "Unit": "iMC"
2106 },
2107 {
2108 "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
2109 "Counter": "0,1,2,3",
2110 "EventCode": "0xB7",
2111 "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
2112 "PerPkg": "1",
2113 "UMask": "0xB",
2114 "Unit": "iMC"
2115 },
2116 {
2117 "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
2118 "Counter": "0,1,2,3",
2119 "EventCode": "0xB7",
2120 "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
2121 "PerPkg": "1",
2122 "UMask": "0xC",
2123 "Unit": "iMC"
2124 },
2125 {
2126 "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
2127 "Counter": "0,1,2,3",
2128 "EventCode": "0xB7",
2129 "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
2130 "PerPkg": "1",
2131 "UMask": "0xD",
2132 "Unit": "iMC"
2133 },
2134 {
2135 "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
2136 "Counter": "0,1,2,3",
2137 "EventCode": "0xB7",
2138 "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
2139 "PerPkg": "1",
2140 "UMask": "0xE",
2141 "Unit": "iMC"
2142 },
2143 {
2144 "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
2145 "Counter": "0,1,2,3",
2146 "EventCode": "0xB7",
2147 "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
2148 "PerPkg": "1",
2149 "UMask": "0xF",
2150 "Unit": "iMC"
2151 },
2152 {
2153 "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
2154 "Counter": "0,1,2,3",
2155 "EventCode": "0xB7",
2156 "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
2157 "PerPkg": "1",
2158 "UMask": "0x10",
2159 "Unit": "iMC"
2160 },
2161 {
2162 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
2163 "Counter": "0,1,2,3",
2164 "EventCode": "0xB7",
2165 "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
2166 "PerPkg": "1",
2167 "UMask": "0x11",
2168 "Unit": "iMC"
2169 },
2170 {
2171 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
2172 "Counter": "0,1,2,3",
2173 "EventCode": "0xB7",
2174 "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
2175 "PerPkg": "1",
2176 "UMask": "0x12",
2177 "Unit": "iMC"
2178 },
2179 {
2180 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
2181 "Counter": "0,1,2,3",
2182 "EventCode": "0xB7",
2183 "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
2184 "PerPkg": "1",
2185 "UMask": "0x13",
2186 "Unit": "iMC"
2187 },
2188 {
2189 "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
2190 "Counter": "0,1,2,3",
2191 "EventCode": "0xB7",
2192 "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
2193 "PerPkg": "1",
2194 "UMask": "0x14",
2195 "Unit": "iMC"
2196 },
2197 {
2198 "BriefDescription": "Read Pending Queue Full Cycles",
2199 "Counter": "0,1,2,3",
2200 "EventCode": "0x12",
2201 "EventName": "UNC_M_RPQ_CYCLES_FULL",
2202 "PerPkg": "1",
2203 "Unit": "iMC"
2204 },
2205 {
2206 "BriefDescription": "Read Pending Queue Not Empty",
2207 "Counter": "0,1,2,3",
2208 "EventCode": "0x11",
2209 "EventName": "UNC_M_RPQ_CYCLES_NE",
2210 "PerPkg": "1",
2211 "Unit": "iMC"
2212 },
2213 {
2214 "BriefDescription": "Scoreboard Accesses; Read Accepts",
2215 "Counter": "0,1,2,3",
2216 "EventCode": "0xD2",
2217 "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
2218 "PerPkg": "1",
2219 "UMask": "0x1",
2220 "Unit": "iMC"
2221 },
2222 {
2223 "BriefDescription": "Scoreboard Accesses; Read Rejects",
2224 "Counter": "0,1,2,3",
2225 "EventCode": "0xD2",
2226 "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
2227 "PerPkg": "1",
2228 "UMask": "0x2",
2229 "Unit": "iMC"
2230 },
2231 {
2232 "BriefDescription": "Scoreboard Accesses; NM read completions",
2233 "Counter": "0,1,2,3",
2234 "EventCode": "0xD2",
2235 "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
2236 "PerPkg": "1",
2237 "UMask": "0x4",
2238 "Unit": "iMC"
2239 },
2240 {
2241 "BriefDescription": "Scoreboard Accesses; NM write completions",
2242 "Counter": "0,1,2,3",
2243 "EventCode": "0xD2",
2244 "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
2245 "PerPkg": "1",
2246 "UMask": "0x8",
2247 "Unit": "iMC"
2248 },
2249 {
2250 "BriefDescription": "Scoreboard Accesses; FM read completions",
2251 "Counter": "0,1,2,3",
2252 "EventCode": "0xD2",
2253 "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
2254 "PerPkg": "1",
2255 "UMask": "0x10",
2256 "Unit": "iMC"
2257 },
2258 {
2259 "BriefDescription": "Scoreboard Accesses; FM write completions",
2260 "Counter": "0,1,2,3",
2261 "EventCode": "0xD2",
2262 "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
2263 "PerPkg": "1",
2264 "UMask": "0x20",
2265 "Unit": "iMC"
2266 },
2267 {
2268 "BriefDescription": "Scoreboard Accesses; Write Accepts",
2269 "Counter": "0,1,2,3",
2270 "EventCode": "0xD2",
2271 "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
2272 "PerPkg": "1",
2273 "UMask": "0x40",
2274 "Unit": "iMC"
2275 },
2276 {
2277 "BriefDescription": "Scoreboard Accesses; Write Rejects",
2278 "Counter": "0,1,2,3",
2279 "EventCode": "0xD2",
2280 "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
2281 "PerPkg": "1",
2282 "UMask": "0x80",
2283 "Unit": "iMC"
2284 },
2285 {
2286 "BriefDescription": "Alloc",
2287 "Counter": "0,1,2,3",
2288 "EventCode": "0xD9",
2289 "EventName": "UNC_M_SB_CANARY.ALLOC",
2290 "PerPkg": "1",
2291 "UMask": "0x1",
2292 "Unit": "iMC"
2293 },
2294 {
2295 "BriefDescription": "Dealloc",
2296 "Counter": "0,1,2,3",
2297 "EventCode": "0xD9",
2298 "EventName": "UNC_M_SB_CANARY.DEALLOC",
2299 "PerPkg": "1",
2300 "UMask": "0x2",
2301 "Unit": "iMC"
2302 },
2303 {
2304 "BriefDescription": "Reject",
2305 "Counter": "0,1,2,3",
2306 "EventCode": "0xD9",
2307 "EventName": "UNC_M_SB_CANARY.REJ",
2308 "PerPkg": "1",
2309 "UMask": "0x4",
2310 "Unit": "iMC"
2311 },
2312 {
2313 "BriefDescription": "Valid",
2314 "Counter": "0,1,2,3",
2315 "EventCode": "0xD9",
2316 "EventName": "UNC_M_SB_CANARY.VLD",
2317 "PerPkg": "1",
2318 "UMask": "0x8",
2319 "Unit": "iMC"
2320 },
2321 {
2322 "BriefDescription": "Near Mem Read Starved",
2323 "Counter": "0,1,2,3",
2324 "EventCode": "0xD9",
2325 "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
2326 "PerPkg": "1",
2327 "UMask": "0x10",
2328 "Unit": "iMC"
2329 },
2330 {
2331 "BriefDescription": "Near Mem Write Starved",
2332 "Counter": "0,1,2,3",
2333 "EventCode": "0xD9",
2334 "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
2335 "PerPkg": "1",
2336 "UMask": "0x20",
2337 "Unit": "iMC"
2338 },
2339 {
2340 "BriefDescription": "Far Mem Read Starved",
2341 "Counter": "0,1,2,3",
2342 "EventCode": "0xD9",
2343 "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
2344 "PerPkg": "1",
2345 "UMask": "0x40",
2346 "Unit": "iMC"
2347 },
2348 {
2349 "BriefDescription": "Far Mem Write Starved",
2350 "Counter": "0,1,2,3",
2351 "EventCode": "0xD9",
2352 "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
2353 "PerPkg": "1",
2354 "UMask": "0x80",
2355 "Unit": "iMC"
2356 },
2357 {
2358 "BriefDescription": "Scoreboard Cycles Full",
2359 "Counter": "0,1,2,3",
2360 "EventCode": "0xD1",
2361 "EventName": "UNC_M_SB_CYCLES_FULL",
2362 "PerPkg": "1",
2363 "Unit": "iMC"
2364 },
2365 {
2366 "BriefDescription": "Scoreboard Cycles Not-Empty",
2367 "Counter": "0,1,2,3",
2368 "EventCode": "0xD0",
2369 "EventName": "UNC_M_SB_CYCLES_NE",
2370 "PerPkg": "1",
2371 "Unit": "iMC"
2372 },
2373 {
2374 "BriefDescription": "Scoreboard Inserts; Reads",
2375 "Counter": "0,1,2,3",
2376 "EventCode": "0xD6",
2377 "EventName": "UNC_M_SB_INSERTS.RDS",
2378 "PerPkg": "1",
2379 "UMask": "0x1",
2380 "Unit": "iMC"
2381 },
2382 {
2383 "BriefDescription": "Scoreboard Inserts; Writes",
2384 "Counter": "0,1,2,3",
2385 "EventCode": "0xD6",
2386 "EventName": "UNC_M_SB_INSERTS.WRS",
2387 "PerPkg": "1",
2388 "UMask": "0x2",
2389 "Unit": "iMC"
2390 },
2391 {
2392 "BriefDescription": "Scoreboard Inserts; Block region reads",
2393 "Counter": "0,1,2,3",
2394 "EventCode": "0xD6",
2395 "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
2396 "PerPkg": "1",
2397 "UMask": "0x10",
2398 "Unit": "iMC"
2399 },
2400 {
2401 "BriefDescription": "Scoreboard Inserts; Block region writes",
2402 "Counter": "0,1,2,3",
2403 "EventCode": "0xD6",
2404 "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
2405 "PerPkg": "1",
2406 "UMask": "0x20",
2407 "Unit": "iMC"
2408 },
2409 {
2410 "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)",
2411 "Counter": "0,1,2,3",
2412 "EventCode": "0xD6",
2413 "EventName": "UNC_M_SB_INSERTS.DEALLOC",
2414 "PerPkg": "1",
2415 "UMask": "0x40",
2416 "Unit": "iMC"
2417 },
2418 {
2419 "BriefDescription": "Scoreboard Inserts; Patrol inserts",
2420 "Counter": "0,1,2,3",
2421 "EventCode": "0xD6",
2422 "EventName": "UNC_M_SB_INSERTS.PATROL",
2423 "PerPkg": "1",
2424 "UMask": "0x80",
2425 "Unit": "iMC"
2426 },
2427 {
2428 "BriefDescription": "Scoreboard Occupancy; Reads",
2429 "Counter": "0,1,2,3",
2430 "EventCode": "0xD5",
2431 "EventName": "UNC_M_SB_OCCUPANCY.RDS",
2432 "PerPkg": "1",
2433 "UMask": "0x1",
2434 "Unit": "iMC"
2435 },
2436 {
2437 "BriefDescription": "Scoreboard Occupancy; Writes",
2438 "Counter": "0,1,2,3",
2439 "EventCode": "0xD5",
2440 "EventName": "UNC_M_SB_OCCUPANCY.WRS",
2441 "PerPkg": "1",
2442 "UMask": "0x2",
2443 "Unit": "iMC"
2444 },
2445 {
2446 "BriefDescription": "Scoreboard Occupancy; Block region reads",
2447 "Counter": "0,1,2,3",
2448 "EventCode": "0xD5",
2449 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
2450 "PerPkg": "1",
2451 "UMask": "0x20",
2452 "Unit": "iMC"
2453 },
2454 {
2455 "BriefDescription": "Scoreboard Occupancy; Block region writes",
2456 "Counter": "0,1,2,3",
2457 "EventCode": "0xD5",
2458 "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
2459 "PerPkg": "1",
2460 "UMask": "0x40",
2461 "Unit": "iMC"
2462 },
2463 {
2464 "BriefDescription": "Scoreboard Occupancy; Patrol",
2465 "Counter": "0,1,2,3",
2466 "EventCode": "0xD5",
2467 "EventName": "UNC_M_SB_OCCUPANCY.PATROL",
2468 "PerPkg": "1",
2469 "UMask": "0x80",
2470 "Unit": "iMC"
2471 },
2472 {
2473 "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict",
2474 "Counter": "0,1,2,3",
2475 "EventCode": "0xD4",
2476 "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
2477 "PerPkg": "1",
2478 "UMask": "0x1",
2479 "Unit": "iMC"
2480 },
2481 {
2482 "BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict",
2483 "Counter": "0,1,2,3",
2484 "EventCode": "0xD4",
2485 "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
2486 "PerPkg": "1",
2487 "UMask": "0x2",
2488 "Unit": "iMC"
2489 },
2490 {
2491 "BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict",
2492 "Counter": "0,1,2,3",
2493 "EventCode": "0xD4",
2494 "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
2495 "PerPkg": "1",
2496 "UMask": "0x4",
2497 "Unit": "iMC"
2498 },
2499 {
2500 "BriefDescription": "Near Mem Read - Set",
2501 "Counter": "0,1,2,3",
2502 "EventCode": "0xD7",
2503 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET",
2504 "PerPkg": "1",
2505 "UMask": "0x1",
2506 "Unit": "iMC"
2507 },
2508 {
2509 "BriefDescription": "Far Mem Read - Set",
2510 "Counter": "0,1,2,3",
2511 "EventCode": "0xD7",
2512 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET",
2513 "PerPkg": "1",
2514 "UMask": "0x2",
2515 "Unit": "iMC"
2516 },
2517 {
2518 "BriefDescription": "Near Mem Write - Set",
2519 "Counter": "0,1,2,3",
2520 "EventCode": "0xD7",
2521 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET",
2522 "PerPkg": "1",
2523 "UMask": "0x4",
2524 "Unit": "iMC"
2525 },
2526 {
2527 "BriefDescription": "Far Mem Write - Set",
2528 "Counter": "0,1,2,3",
2529 "EventCode": "0xD7",
2530 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET",
2531 "PerPkg": "1",
2532 "UMask": "0x8",
2533 "Unit": "iMC"
2534 },
2535 {
2536 "BriefDescription": "Near Mem Read - Clear",
2537 "Counter": "0,1,2,3",
2538 "EventCode": "0xD7",
2539 "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR",
2540 "PerPkg": "1",
2541 "UMask": "0x10",
2542 "Unit": "iMC"
2543 },
2544 {
2545 "BriefDescription": "Far Mem Read - Clear",
2546 "Counter": "0,1,2,3",
2547 "EventCode": "0xD7",
2548 "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR",
2549 "PerPkg": "1",
2550 "UMask": "0x20",
2551 "Unit": "iMC"
2552 },
2553 {
2554 "BriefDescription": "Near Mem Write - Clear",
2555 "Counter": "0,1,2,3",
2556 "EventCode": "0xD7",
2557 "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR",
2558 "PerPkg": "1",
2559 "UMask": "0x40",
2560 "Unit": "iMC"
2561 },
2562 {
2563 "BriefDescription": "Far Mem Write - Clear",
2564 "Counter": "0,1,2,3",
2565 "EventCode": "0xD7",
2566 "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR",
2567 "PerPkg": "1",
2568 "UMask": "0x80",
2569 "Unit": "iMC"
2570 },
2571 {
2572 "BriefDescription": "Near Mem Read",
2573 "Counter": "0,1,2,3",
2574 "EventCode": "0xD8",
2575 "EventName": "UNC_M_SB_STRV_OCC.NMRD",
2576 "PerPkg": "1",
2577 "UMask": "0x1",
2578 "Unit": "iMC"
2579 },
2580 {
2581 "BriefDescription": "Far Mem Read",
2582 "Counter": "0,1,2,3",
2583 "EventCode": "0xD8",
2584 "EventName": "UNC_M_SB_STRV_OCC.FMRD",
2585 "PerPkg": "1",
2586 "UMask": "0x2",
2587 "Unit": "iMC"
2588 },
2589 {
2590 "BriefDescription": "Near Mem Write",
2591 "Counter": "0,1,2,3",
2592 "EventCode": "0xD8",
2593 "EventName": "UNC_M_SB_STRV_OCC.NMWR",
2594 "PerPkg": "1",
2595 "UMask": "0x4",
2596 "Unit": "iMC"
2597 },
2598 {
2599 "BriefDescription": "Far Mem Write",
2600 "Counter": "0,1,2,3",
2601 "EventCode": "0xD8",
2602 "EventName": "UNC_M_SB_STRV_OCC.FMWR",
2603 "PerPkg": "1",
2604 "UMask": "0x8",
2605 "Unit": "iMC"
2606 },
2607 {
2608 "BriefDescription": "UNC_M_SB_TAGGED.NEW",
2609 "Counter": "0,1,2,3",
2610 "EventCode": "0xDD",
2611 "EventName": "UNC_M_SB_TAGGED.NEW",
2612 "PerPkg": "1",
2613 "UMask": "0x1",
2614 "Unit": "iMC"
2615 },
2616 {
2617 "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
2618 "Counter": "0,1,2,3",
2619 "EventCode": "0xDD",
2620 "EventName": "UNC_M_SB_TAGGED.RD_HIT",
2621 "PerPkg": "1",
2622 "UMask": "0x2",
2623 "Unit": "iMC"
2624 },
2625 {
2626 "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
2627 "Counter": "0,1,2,3",
2628 "EventCode": "0xDD",
2629 "EventName": "UNC_M_SB_TAGGED.RD_MISS",
2630 "PerPkg": "1",
2631 "UMask": "0x4",
2632 "Unit": "iMC"
2633 },
2634 {
2635 "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
2636 "Counter": "0,1,2,3",
2637 "EventCode": "0xDD",
2638 "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
2639 "PerPkg": "1",
2640 "UMask": "0x8",
2641 "Unit": "iMC"
2642 },
2643 {
2644 "BriefDescription": "UNC_M_SB_TAGGED.OCC",
2645 "Counter": "0,1,2,3",
2646 "EventCode": "0xDD",
2647 "EventName": "UNC_M_SB_TAGGED.OCC",
2648 "PerPkg": "1",
2649 "UMask": "0x80",
2650 "Unit": "iMC"
2651 },
2652 {
2653 "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
2654 "Counter": "0,1,2,3",
2655 "EventCode": "0xC0",
2656 "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
2657 "PerPkg": "1",
2658 "UMask": "0x1",
2659 "Unit": "iMC"
2660 },
2661 {
2662 "BriefDescription": "Transition from WMM to RMM because of low threshold",
2663 "Counter": "0,1,2,3",
2664 "EventCode": "0xC0",
2665 "EventName": "UNC_M_WMM_TO_RMM.STARVE",
2666 "PerPkg": "1",
2667 "UMask": "0x2",
2668 "Unit": "iMC"
2669 },
2670 {
2671 "BriefDescription": "Transition from WMM to RMM because of low threshold",
2672 "Counter": "0,1,2,3",
2673 "EventCode": "0xC0",
2674 "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
2675 "PerPkg": "1",
2676 "UMask": "0x4",
2677 "Unit": "iMC"
2678 },
2679 {
2680 "BriefDescription": "Write Pending Queue Full Cycles",
2681 "Counter": "0,1,2,3",
2682 "EventCode": "0x22",
2683 "EventName": "UNC_M_WPQ_CYCLES_FULL",
2684 "PerPkg": "1",
2685 "Unit": "iMC"
2686 },
2687 {
2688 "BriefDescription": "Write Pending Queue Not Empty",
2689 "Counter": "0,1,2,3",
2690 "EventCode": "0x21",
2691 "EventName": "UNC_M_WPQ_CYCLES_NE",
2692 "PerPkg": "1",
2693 "Unit": "iMC"
2694 },
2695 {
2696 "BriefDescription": "Write Pending Queue CAM Match",
2697 "Counter": "0,1,2,3",
2698 "EventCode": "0x23",
2699 "EventName": "UNC_M_WPQ_READ_HIT",
2700 "PerPkg": "1",
2701 "Unit": "iMC"
2702 },
2703 {
2704 "BriefDescription": "Write Pending Queue CAM Match",
2705 "Counter": "0,1,2,3",
2706 "EventCode": "0x24",
2707 "EventName": "UNC_M_WPQ_WRITE_HIT",
2708 "PerPkg": "1",
2709 "Unit": "iMC"
2710 },
2711 {
2712 "BriefDescription": "Not getting the requested Major Mode",
2713 "Counter": "0,1,2,3",
2714 "EventCode": "0xC1",
2715 "EventName": "UNC_M_WRONG_MM",
2716 "PerPkg": "1",
2717 "Unit": "iMC"
2718 },
2719 {
2720 "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
2721 "Counter": "0,1,2,3",
2722 "EventCode": "0xB8",
2723 "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
2724 "PerPkg": "1",
2725 "Unit": "iMC"
2726 },
2727 {
2728 "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
2729 "Counter": "0,1,2,3",
2730 "EventCode": "0xB8",
2731 "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
2732 "PerPkg": "1",
2733 "UMask": "0x1",
2734 "Unit": "iMC"
2735 },
2736 {
2737 "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
2738 "Counter": "0,1,2,3",
2739 "EventCode": "0xB8",
2740 "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
2741 "PerPkg": "1",
2742 "UMask": "0x2",
2743 "Unit": "iMC"
2744 },
2745 {
2746 "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
2747 "Counter": "0,1,2,3",
2748 "EventCode": "0xB8",
2749 "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
2750 "PerPkg": "1",
2751 "UMask": "0x3",
2752 "Unit": "iMC"
2753 },
2754 {
2755 "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
2756 "Counter": "0,1,2,3",
2757 "EventCode": "0xB8",
2758 "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
2759 "PerPkg": "1",
2760 "UMask": "0x4",
2761 "Unit": "iMC"
2762 },
2763 {
2764 "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
2765 "Counter": "0,1,2,3",
2766 "EventCode": "0xB8",
2767 "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
2768 "PerPkg": "1",
2769 "UMask": "0x5",
2770 "Unit": "iMC"
2771 },
2772 {
2773 "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
2774 "Counter": "0,1,2,3",
2775 "EventCode": "0xB8",
2776 "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
2777 "PerPkg": "1",
2778 "UMask": "0x6",
2779 "Unit": "iMC"
2780 },
2781 {
2782 "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
2783 "Counter": "0,1,2,3",
2784 "EventCode": "0xB8",
2785 "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
2786 "PerPkg": "1",
2787 "UMask": "0x7",
2788 "Unit": "iMC"
2789 },
2790 {
2791 "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
2792 "Counter": "0,1,2,3",
2793 "EventCode": "0xB8",
2794 "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
2795 "PerPkg": "1",
2796 "UMask": "0x8",
2797 "Unit": "iMC"
2798 },
2799 {
2800 "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
2801 "Counter": "0,1,2,3",
2802 "EventCode": "0xB8",
2803 "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
2804 "PerPkg": "1",
2805 "UMask": "0x9",
2806 "Unit": "iMC"
2807 },
2808 {
2809 "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
2810 "Counter": "0,1,2,3",
2811 "EventCode": "0xB8",
2812 "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
2813 "PerPkg": "1",
2814 "UMask": "0xA",
2815 "Unit": "iMC"
2816 },
2817 {
2818 "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
2819 "Counter": "0,1,2,3",
2820 "EventCode": "0xB8",
2821 "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
2822 "PerPkg": "1",
2823 "UMask": "0xB",
2824 "Unit": "iMC"
2825 },
2826 {
2827 "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
2828 "Counter": "0,1,2,3",
2829 "EventCode": "0xB8",
2830 "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
2831 "PerPkg": "1",
2832 "UMask": "0xC",
2833 "Unit": "iMC"
2834 },
2835 {
2836 "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
2837 "Counter": "0,1,2,3",
2838 "EventCode": "0xB8",
2839 "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
2840 "PerPkg": "1",
2841 "UMask": "0xD",
2842 "Unit": "iMC"
2843 },
2844 {
2845 "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
2846 "Counter": "0,1,2,3",
2847 "EventCode": "0xB8",
2848 "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
2849 "PerPkg": "1",
2850 "UMask": "0xE",
2851 "Unit": "iMC"
2852 },
2853 {
2854 "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
2855 "Counter": "0,1,2,3",
2856 "EventCode": "0xB8",
2857 "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
2858 "PerPkg": "1",
2859 "UMask": "0xF",
2860 "Unit": "iMC"
2861 },
2862 {
2863 "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
2864 "Counter": "0,1,2,3",
2865 "EventCode": "0xB8",
2866 "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
2867 "PerPkg": "1",
2868 "UMask": "0x10",
2869 "Unit": "iMC"
2870 },
2871 {
2872 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
2873 "Counter": "0,1,2,3",
2874 "EventCode": "0xB8",
2875 "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
2876 "PerPkg": "1",
2877 "UMask": "0x11",
2878 "Unit": "iMC"
2879 },
2880 {
2881 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
2882 "Counter": "0,1,2,3",
2883 "EventCode": "0xB8",
2884 "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
2885 "PerPkg": "1",
2886 "UMask": "0x12",
2887 "Unit": "iMC"
2888 },
2889 {
2890 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
2891 "Counter": "0,1,2,3",
2892 "EventCode": "0xB8",
2893 "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
2894 "PerPkg": "1",
2895 "UMask": "0x13",
2896 "Unit": "iMC"
2897 },
2898 {
2899 "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
2900 "Counter": "0,1,2,3",
2901 "EventCode": "0xB8",
2902 "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
2903 "PerPkg": "1",
2904 "UMask": "0x14",
2905 "Unit": "iMC"
2906 },
2907 {
2908 "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
2909 "Counter": "0,1,2,3",
2910 "EventCode": "0xB9",
2911 "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
2912 "PerPkg": "1",
2913 "Unit": "iMC"
2914 },
2915 {
2916 "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
2917 "Counter": "0,1,2,3",
2918 "EventCode": "0xB9",
2919 "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
2920 "PerPkg": "1",
2921 "UMask": "0x1",
2922 "Unit": "iMC"
2923 },
2924 {
2925 "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
2926 "Counter": "0,1,2,3",
2927 "EventCode": "0xB9",
2928 "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
2929 "PerPkg": "1",
2930 "UMask": "0x2",
2931 "Unit": "iMC"
2932 },
2933 {
2934 "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
2935 "Counter": "0,1,2,3",
2936 "EventCode": "0xB9",
2937 "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
2938 "PerPkg": "1",
2939 "UMask": "0x3",
2940 "Unit": "iMC"
2941 },
2942 {
2943 "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
2944 "Counter": "0,1,2,3",
2945 "EventCode": "0xB9",
2946 "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
2947 "PerPkg": "1",
2948 "UMask": "0x4",
2949 "Unit": "iMC"
2950 },
2951 {
2952 "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
2953 "Counter": "0,1,2,3",
2954 "EventCode": "0xB9",
2955 "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
2956 "PerPkg": "1",
2957 "UMask": "0x5",
2958 "Unit": "iMC"
2959 },
2960 {
2961 "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
2962 "Counter": "0,1,2,3",
2963 "EventCode": "0xB9",
2964 "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
2965 "PerPkg": "1",
2966 "UMask": "0x6",
2967 "Unit": "iMC"
2968 },
2969 {
2970 "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
2971 "Counter": "0,1,2,3",
2972 "EventCode": "0xB9",
2973 "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
2974 "PerPkg": "1",
2975 "UMask": "0x7",
2976 "Unit": "iMC"
2977 },
2978 {
2979 "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
2980 "Counter": "0,1,2,3",
2981 "EventCode": "0xB9",
2982 "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
2983 "PerPkg": "1",
2984 "UMask": "0x8",
2985 "Unit": "iMC"
2986 },
2987 {
2988 "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
2989 "Counter": "0,1,2,3",
2990 "EventCode": "0xB9",
2991 "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
2992 "PerPkg": "1",
2993 "UMask": "0x9",
2994 "Unit": "iMC"
2995 },
2996 {
2997 "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
2998 "Counter": "0,1,2,3",
2999 "EventCode": "0xB9",
3000 "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
3001 "PerPkg": "1",
3002 "UMask": "0xA",
3003 "Unit": "iMC"
3004 },
3005 {
3006 "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
3007 "Counter": "0,1,2,3",
3008 "EventCode": "0xB9",
3009 "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
3010 "PerPkg": "1",
3011 "UMask": "0xB",
3012 "Unit": "iMC"
3013 },
3014 {
3015 "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
3016 "Counter": "0,1,2,3",
3017 "EventCode": "0xB9",
3018 "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
3019 "PerPkg": "1",
3020 "UMask": "0xC",
3021 "Unit": "iMC"
3022 },
3023 {
3024 "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
3025 "Counter": "0,1,2,3",
3026 "EventCode": "0xB9",
3027 "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
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4224 "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
4225 "Counter": "FIXED",
4226 "EventCode": "0xff",
4227 "EventName": "UNC_M_CLOCKTICKS_F",
4228 "PerPkg": "1",
4229 "Unit": "iMC"
4230 },
4231 {
4232 "BriefDescription": "PMM Occupancy",
4233 "Counter": "0,1,2,3",
4234 "EventCode": "0xE0",
4235 "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
4236 "PerPkg": "1",
4237 "UMask": "0x4",
4238 "Unit": "iMC"
4239 },
4240 {
4241 "BriefDescription": "PMM Read Queue Cycles Not Empty",
4242 "Counter": "0,1,2,3",
4243 "EventCode": "0xE1",
4244 "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
4245 "PerPkg": "1",
4246 "Unit": "iMC"
4247 },
4248 {
4249 "BriefDescription": "PMM Read Queue Cycles Full",
4250 "Counter": "0,1,2,3",
4251 "EventCode": "0xE2",
4252 "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
4253 "PerPkg": "1",
4254 "Unit": "iMC"
4255 },
4256 {
4257 "BriefDescription": "RPQ GNTs",
4258 "Counter": "0,1,2,3",
4259 "EventCode": "0xEA",
4260 "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
4261 "PerPkg": "1",
4262 "UMask": "0x10",
4263 "Unit": "iMC"
4264 },
4265 {
4266 "BriefDescription": "Underfill GNTs",
4267 "Counter": "0,1,2,3",
4268 "EventCode": "0xEA",
4269 "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
4270 "PerPkg": "1",
4271 "UMask": "0x20",
4272 "Unit": "iMC"
4273 },
4274 {
4275 "BriefDescription": "Misc GNTs",
4276 "Counter": "0,1,2,3",
4277 "EventCode": "0xEA",
4278 "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
4279 "PerPkg": "1",
4280 "UMask": "0x40",
4281 "Unit": "iMC"
4282 },
4283 {
4284 "BriefDescription": "Misc Commands (error, flow ACKs)",
4285 "Counter": "0,1,2,3",
4286 "EventCode": "0xEA",
4287 "EventName": "UNC_M_PMM_CMD1.MISC",
4288 "PerPkg": "1",
4289 "UMask": "0x80",
4290 "Unit": "iMC"
4291 },
4292 {
4293 "BriefDescription": "Opportunistic Reads",
4294 "Counter": "0,1,2,3",
4295 "EventCode": "0xEB",
4296 "EventName": "UNC_M_PMM_CMD2.OPP_RD",
4297 "PerPkg": "1",
4298 "UMask": "0x1",
4299 "Unit": "iMC"
4300 },
4301 {
4302 "BriefDescription": "Expected No data packet (ERID matched NDP encoding)",
4303 "Counter": "0,1,2,3",
4304 "EventCode": "0xEB",
4305 "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
4306 "PerPkg": "1",
4307 "UMask": "0x2",
4308 "Unit": "iMC"
4309 },
4310 {
4311 "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)",
4312 "Counter": "0,1,2,3",
4313 "EventCode": "0xEB",
4314 "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
4315 "PerPkg": "1",
4316 "UMask": "0x4",
4317 "Unit": "iMC"
4318 },
4319 {
4320 "BriefDescription": "Read Requests - Slot 0",
4321 "Counter": "0,1,2,3",
4322 "EventCode": "0xEB",
4323 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
4324 "PerPkg": "1",
4325 "UMask": "0x8",
4326 "Unit": "iMC"
4327 },
4328 {
4329 "BriefDescription": "Read Requests - Slot 1",
4330 "Counter": "0,1,2,3",
4331 "EventCode": "0xEB",
4332 "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
4333 "PerPkg": "1",
4334 "UMask": "0x10",
4335 "Unit": "iMC"
4336 },
4337 {
4338 "BriefDescription": "PMM ECC Errors",
4339 "Counter": "0,1,2,3",
4340 "EventCode": "0xEB",
4341 "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
4342 "PerPkg": "1",
4343 "UMask": "0x20",
4344 "Unit": "iMC"
4345 },
4346 {
4347 "BriefDescription": "PMM ERID detectable parity error",
4348 "Counter": "0,1,2,3",
4349 "EventCode": "0xEB",
4350 "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
4351 "PerPkg": "1",
4352 "UMask": "0x40",
4353 "Unit": "iMC"
4354 },
4355 {
4356 "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode",
4357 "Counter": "0,1,2,3",
4358 "EventCode": "0xEC",
4359 "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC",
4360 "PerPkg": "1",
4361 "UMask": "0x1",
4362 "Unit": "iMC"
4363 },
4364 {
4365 "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode",
4366 "Counter": "0,1,2,3",
4367 "EventCode": "0xEC",
4368 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC",
4369 "PerPkg": "1",
4370 "UMask": "0x4",
4371 "Unit": "iMC"
4372 },
4373 {
4374 "BriefDescription": "PMM Major Mode",
4375 "Counter": "0,1,2,3",
4376 "EventCode": "0xEC",
4377 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER",
4378 "PerPkg": "1",
4379 "UMask": "0x20",
4380 "Unit": "iMC"
4381 },
4382 {
4383 "BriefDescription": "PMM Major Mode",
4384 "Counter": "0,1,2,3",
4385 "EventCode": "0xEC",
4386 "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT",
4387 "PerPkg": "1",
4388 "UMask": "0x40",
4389 "Unit": "iMC"
4390 },
4391 {
4392 "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC",
4393 "Counter": "0,1,2,3",
4394 "EventCode": "0xED",
4395 "EventName": "UNC_M_MAJMODE2.DRAM_CYC",
4396 "PerPkg": "1",
4397 "UMask": "0x2",
4398 "Unit": "iMC"
4399 },
4400 {
4401 "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER",
4402 "Counter": "0,1,2,3",
4403 "EventCode": "0xED",
4404 "EventName": "UNC_M_MAJMODE2.DRAM_ENTER",
4405 "PerPkg": "1",
4406 "UMask": "0x8",
4407 "Unit": "iMC"
4408 },
4409 {
4410 "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER",
4411 "Counter": "0,1,2,3",
4412 "EventCode": "0xED",
4413 "EventName": "UNC_M_MAJMODE2.PMM_ENTER",
4414 "PerPkg": "1",
4415 "UMask": "0x4",
4416 "Unit": "iMC"
4417 },
4418 {
4419 "BriefDescription": "PMM Write Queue Cycles Full",
4420 "Counter": "0,1,2,3",
4421 "EventCode": "0xE6",
4422 "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
4423 "PerPkg": "1",
4424 "Unit": "iMC"
4425 },
4426 {
4427 "BriefDescription": "PMM Write Queue Cycles Not Empty",
4428 "Counter": "0,1,2,3",
4429 "EventCode": "0xE5",
4430 "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
4431 "PerPkg": "1",
4432 "Unit": "iMC"
4433 },
4434 {
4435 "BriefDescription": "PMM Occupancy",
4436 "Counter": "0,1,2,3",
4437 "EventCode": "0xE4",
4438 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
4439 "PerPkg": "1",
4440 "UMask": "0x2",
4441 "Unit": "iMC"
4442 },
4443 {
4444 "BriefDescription": "PMM Occupancy",
4445 "Counter": "0,1,2,3",
4446 "EventCode": "0xE4",
4447 "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
4448 "PerPkg": "1",
4449 "UMask": "0x4",
4450 "Unit": "iMC"
4451 },
4452 {
4453 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT",
4454 "Counter": "0,1,2,3",
4455 "EventCode": "0xE8",
4456 "EventName": "UNC_M_PMM_WPQ_PCOMMIT",
4457 "PerPkg": "1",
4458 "Unit": "iMC"
4459 },
4460 {
4461 "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
4462 "Counter": "0,1,2,3",
4463 "EventCode": "0xE9",
4464 "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
4465 "PerPkg": "1",
4466 "Unit": "iMC"
4467 },
4468 {
4469 "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode",
4470 "Counter": "0,1,2,3",
4471 "EventCode": "0xEC",
4472 "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC",
4473 "PerPkg": "1",
4474 "UMask": "0x2",
4475 "Unit": "iMC"
4476 },
4477 {
4478 "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC",
4479 "Counter": "0,1,2,3",
4480 "EventCode": "0xED",
4481 "EventName": "UNC_M_MAJMODE2.PMM_CYC",
4482 "PerPkg": "1",
4483 "UMask": "0x1",
4484 "Unit": "iMC"
4485 },
4486 {
4487 "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
4488 "Counter": "0,1,2,3",
4489 "EventCode": "0xDD",
4490 "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
4491 "PerPkg": "1",
4492 "UMask": "0x10",
4493 "Unit": "iMC"
4494 },
4495 {
4496 "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
4497 "Counter": "0,1,2,3",
4498 "EventCode": "0xDD",
4499 "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
4500 "PerPkg": "1",
4501 "UMask": "0x20",
4502 "Unit": "iMC"
4503 },
4504 {
4505 "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
4506 "Counter": "0,1,2,3",
4507 "EventCode": "0xDD",
4508 "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
4509 "PerPkg": "1",
4510 "UMask": "0x40",
4511 "Unit": "iMC"
4512 },
4513 {
4514 "BriefDescription": "Scoreboard Inserts; Persistent Mem writes",
4515 "Counter": "0,1,2,3",
4516 "EventCode": "0xD6",
4517 "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
4518 "PerPkg": "1",
4519 "UMask": "0x08",
4520 "Unit": "iMC"
4521 },
4522 {
4523 "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes",
4524 "Counter": "0,1,2,3",
4525 "EventCode": "0xD5",
4526 "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
4527 "PerPkg": "1",
4528 "UMask": "0x08",
4529 "Unit": "iMC"
4530 },
4531 {
4532 "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads",
4533 "Counter": "0,1,2,3",
4534 "EventCode": "0xD5",
4535 "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
4536 "PerPkg": "1",
4537 "UMask": "0x04",
4538 "Unit": "iMC"
4539 },
4540 {
4541 "BriefDescription": "Scoreboard Inserts; Persistent Mem reads",
4542 "Counter": "0,1,2,3",
4543 "EventCode": "0xD6",
4544 "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
4545 "PerPkg": "1",
4546 "UMask": "0x04",
4547 "Unit": "iMC"
4548 }
4549 ]
